Statistical Full-Chip Leakage Analysis Considering Junction Tunneling Leakage

Statistical Full-Chip Leakage Analysis Considering Junction Tunneling Leakage

Tao Li Tao Li Zhiping YuZhiping Yu

Institute of MicroelectronicsInstitute of MicroelectronicsTsinghua UniversityTsinghua University

2

OutlineOutline

MotivationMotivation

Junction Tunneling Leakage – Circuit Level AnalysisJunction Tunneling Leakage – Circuit Level Analysis– Simple inverterSimple inverter– Multi-input gateMulti-input gate

Statistical Full-Chip Leakage Analysis TechniqueStatistical Full-Chip Leakage Analysis Technique– Modeling of process-induced parameter variationsModeling of process-induced parameter variations

PCA & ICAPCA & ICA– Sum of leakage componentsSum of leakage components

Experimental ResultsExperimental Results

SummarySummary

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Leakage and Process VariationsLeakage and Process Variations Leakage power becomes a major component ofLeakage power becomes a major component of

the total power.the total power.

Process variation has a significant impact on leakage.Process variation has a significant impact on leakage.

50

100

150

200

250

00.25 0.18 0.13 0.1

Leakage PowerActive Power

Pow

er (W

)

Feature SizeScale Down

0.18 μm 0.09 μm 65 nm

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Major Leakage componentsMajor Leakage components

Subthreshold leakageSubthreshold leakage

Gate oxide leakageGate oxide leakage

Junction tunneling leakageJunction tunneling leakage

Gate

Source

n+n+

Bulk

Drain

Subthreshold Leakage Isub

Gate Leakage Igate

Junction tunneling leakage

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Overview of Related WorksOverview of Related Works

Previous works on statistical full-chip Previous works on statistical full-chip leakage computationleakage computation– Computation of PDF of full-chip leakageComputation of PDF of full-chip leakage

Approximate process variations asApproximate process variations asGaussian distributionsGaussian distributions

Finding full-chip leakage by summing upFinding full-chip leakage by summing upindependent lognormalsindependent lognormals

R. Rao ISLPED03,H. Chang ICCAD 03,R. Rao ISLPED03,H. Chang ICCAD 03,H. Chang H. Chang DAC05, X. Li DAC06, DAC05, X. Li DAC06, et alet al..

Most of the previous works ignoredMost of the previous works ignored– Effect of Non-Gaussian parametersEffect of Non-Gaussian parameters– Junction tunneling leakageJunction tunneling leakage

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OutlineOutline

MotivationMotivation

Junction tunneling leakage – Circuit level analysisJunction tunneling leakage – Circuit level analysis– Simple inverterSimple inverter– Multi input gateMulti input gate

Statistical Full-chip leakage analysis techniqueStatistical Full-chip leakage analysis technique– Modeling of process-induced parameter variationsModeling of process-induced parameter variations

PCA & ICAPCA & ICA– Sum of leakage componentsSum of leakage components

Experimental ResultsExperimental Results

SummarySummary

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Simple InverterSimple Inverter

When input = 0VWhen input = 0V– NMOS: maximum & NMOS: maximum &

Can be independently Can be independently calculated and added calculated and added for total leakagefor total leakage

– PMOS: gate oxide leakage PMOS: gate oxide leakage – small and ignored– small and ignored

When input =When input =– NMOS: gate oxide leakageNMOS: gate oxide leakage– PMOS: subthreshold PMOS: subthreshold

leakage and junction leakage and junction tunneling leakagetunneling leakage

subIjuncI

ddV

juncI

subI

ddV

ddV

00

gateI

& sub juncI I

ddV

ddV

00

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Multi input gate: general approachMulti input gate: general approach

If all inputs have a high stateIf all inputs have a high state– Analysis is similar to the that of the inverterAnalysis is similar to the that of the inverter

At least one input is lowAt least one input is low– Combination of , ,andCombination of , ,and– Approach: distinguish 6 different scenariosApproach: distinguish 6 different scenarios

gateIjuncI subI

tt

an

mt

bn

bt

outputn outputn outputn outputn outputn outputn

DDV

DDV

0 0

0

0

0

0

0 0

0

DDV

DDV

DDV DDV

DDV

DDV

DDV

tt

an

mt

bn

bt

tt

an

mt

bn

bt

tt

an

mt

bn

bt

tt

an

mt

bn

bt

tt

an

mt

bn

bt

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Total leakage current of a chip:Total leakage current of a chip:

Computation of Total Chip LeakageComputation of Total Chip Leakage

gate gate

total sub gate junc , ,sub , ,gate , , junc1 1 input _ state _

( ) ( )N N

i i ii j j i j j i j j

j j i

I I I I P I P I P I

Input pattern independent approachInput pattern independent approach– Direct computation: Direct computation: 22kk input vector states for a input vector states for a kk-input gate -input gate – Applying Applying dominant statesdominant states of of

Leakage of stack at state Leakage of stack at state i i is not always independentis not always independent– Interactions ofInteractions of IIsubsub,, IIgategate and and IIjuncjunc need to be considered need to be considered– Analyzing leakage current of stack by input stateAnalyzing leakage current of stack by input state

: probability of input vector state: probability of input vector state i i of the of the jjthth gate gatejiP ,

,sub ,gate , junci i ij j jI I I

totalI can be either the leakage for a fixed input vector or the can be either the leakage for a fixed input vector or the average leakage currentaverage leakage current

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Dominant States of Leakage CurrentDominant States of Leakage Current

Case (a) (c): dominate states of Case (a) (c): dominate states of IIgategate

NMOS-Transistor Stack

Interaction between Interaction between IIsubsub and and IIgategate

total sub(b) I I

total gate(c) I I

total sub gate(a) I I I

D. Lee et. al. at DAC03

C. Oh et. al. at DAC99

D. Lee et. al. at DAC03

Dominant states of junction tunneling leakage IDominant states of junction tunneling leakage I juncjunc

– States with the “on” transistors connected to the output nodeStates with the “on” transistors connected to the output node(stack effect )(stack effect )

– Only k dominant states for a k-input gateOnly k dominant states for a k-input gate

Case (a) (b): dominate states of Case (a) (b): dominate states of IIsubsub

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Results: Leakage estimation for 4-NANDResults: Leakage estimation for 4-NAND

The error of the proposed analysis method over SPICEThe error of the proposed analysis method over SPICE

Average ~1.5% over all input statesAverage ~1.5% over all input states Maximum error = 4.5% @1110Maximum error = 4.5% @1110

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 11110

2

4

6

8

10

12

14

To

tal L

ea

kag

e (

nA

)

-3

-2

-1

0

1

2

3

4

% E

rro

r

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OutlineOutline

MotivationMotivation

Junction tunneling leakage – Circuit level analysisJunction tunneling leakage – Circuit level analysis– Simple inverterSimple inverter– Multi input gateMulti input gate

Statistical Full-chip leakage analysis techniqueStatistical Full-chip leakage analysis technique– Modeling of process-induced parameter variationsModeling of process-induced parameter variations

PCA & ICAPCA & ICA– Sum of leakage componentsSum of leakage components

Experimental ResultsExperimental Results

SummarySummary

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Proposed Analysis Method HighlightsProposed Analysis Method Highlights

Incorporates both Gaussian and non-Gaussian parameters

Non-Gaussian and Gaussian variables transformed to independent basis with PCA/ICA

Uses closed form PDF/CDF expressions

Moments matching-based PDF/CDF extraction

Fast algorithm for the sum up of leakage components

Three kinds of leakage components are considered

Inputs are moments of varying process parameters

Easier to obtain moments from process data files

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OutlineOutline

MotivationMotivation

Junction tunneling leakage – Circuit level analysisJunction tunneling leakage – Circuit level analysis– Simple inverterSimple inverter– Multi input gateMulti input gate

Statistical Full-chip leakage analysis techniqueStatistical Full-chip leakage analysis technique– Modeling of process-induced parameter variationsModeling of process-induced parameter variations

PCA & ICAPCA & ICA– Sum of leakage componentsSum of leakage components

Experimental ResultsExperimental Results

SummarySummary

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Experimental ResultsExperimental Results

Comparison of our results with Monte Carlo simulationsComparison of our results with Monte Carlo simulations

Comparison with Gaussian modeling of parametersComparison with Gaussian modeling of parameters

Benchmark Our Method Error ((Our-MC)/MC)% Gaussian Error ((Old-MC)/MC)%

Name #Cells #Grids µ σ 95% Pt 5% Pt µ σ 95% Pt 5% Pt

C7552 5235 64 -1.63 3.02 3.84 3.91 6.32 23.44 24.66 4.56

C5315 3768 64 -1.07 -2.82 -4.09 -3.68 5.69 17.56 20.31 4.89

C6288 2552 16 -1.15 -2.14 3.52 3.61 5.98 14.63 14.89 3.11

C3540 2491 16 0.71 1.56 2.97 2.88 4.96 10.23 15.34 -3.16

C2670 1854 16 -0.81 1.34 2.90 2.77 4.78 8.84 11.13 2.34

C1908 1197 16 -0.64 -0.98 -2.45 2.12 3.45 8.02 8.98 4.34

C880 556 4 -0.23 -0.59 -1.26 -1.32 2.12 6.14 9.32 1.23

C432 273 4 -0.07 -0.23 -0.98 -0.84 1.29 5.99 4.14 -2.01

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OutlineOutline

MotivationMotivation

Junction tunneling leakage – Circuit level analysisJunction tunneling leakage – Circuit level analysis– Simple inverterSimple inverter– Multi input gateMulti input gate

Statistical Full-chip leakage analysis techniqueStatistical Full-chip leakage analysis technique– Modeling of process-induced parameter variationsModeling of process-induced parameter variations

PCA & ICAPCA & ICA– Sum of leakage componentsSum of leakage components

Experimental ResultsExperimental Results

SummarySummary

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SummarySummary

A fast approach to compute total leakage currentA fast approach to compute total leakage current– Considering , ,andConsidering , ,and– Average error 1.5%Average error 1.5%

Both Gaussian and Non-Gaussian parameters are Both Gaussian and Non-Gaussian parameters are consideredconsidered– PCA and ICA are employed as preprocessing stepsPCA and ICA are employed as preprocessing steps

Sum the leakage to get a final resultSum the leakage to get a final result

Algorithm has a complexity of Algorithm has a complexity of

juncI gateIsubI

O G

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Thanks!Thanks!