state of the art in the analog cmos circuit

State of the Art in the Analog CMOS Circuit Design

~~~ ~~ ~~~ ~~ ~ ~ ~ ~~~ ~ ~~ ~~~ ~ ~~ ~~ ~~

ERNST HABEKOITE, MEMBER, IEEE, BERND HOEFFLINGER, HANS-WALTER KLEIN, MEMBER, IEEE, AND MICHIEL A. BEUNDER

Invited Paper

This paper is not intended to cover CMOS analog circuit design exhaustively. Yet, it describes how much CMOS technology has been involved in analog circuit design despite the general opinion that CMOS is only suited for digital design. After some developments in the CMOS technology have been discussed, the analog building block scene is covered.

The analog building blocks can roughly be divided into two subgroups: the switched-capacitor and the non-switched-capacitor building blocks. Following this subdivision different approaches are briefly looked at. Several tables conclude this review and indicate that new analog developments in CMOS circuit design are still to be expected.

Next, the CAD tool development for analog CMOS is discussed, showing that there is still a lot to be done in the field of automated analog design. In conclusion, some ideas concerning analog CAD or, concerning CAD in a more general sense are described.

INTRODUCTION

Activities in analog CMOS have been rather limited as in many cases analog bipolar solutions were preferred, because bipolar devices provide several specific advantages for analog circuit design, such as:

an inherent low input referred noise, low input offset voltage, high voltage gain, high output drive, high frequency capability.

Analog CMOS has also been hampered bythegeneral opinion that only bipolar devices are well-suited for analog circuits and that CMOS devices are only to be used for digital circuits.

Yet, the CMOS technology today is becoming one of the most important technologies especially in the domain of digital circuits. This is due to the following main advantages:

low power consumption, high packing density,

Manuscript received October 10, 1986; revised November 15,

The authors are with lnstitut f u r Mikroelektronik Stuttgart,

IEEE Log Number 8714502.

1986.

D-7000 Stuttgart 8 0 , Federal Republic of Germany.

high noise immunity, ease of design, relative ease of scaling.

Theseadvantageswill gain importanceas the minimum feature sizes of CMOS devices are still being shrunk allowing complex electronic systems to be integrated on one chip.

Therefore, during the last years a lot of effort has been invested in digital CMOS and the necessary design tools (CAD) in order to be able to cope with these complex digital designs. Further, today the difference between analog and digital is diminishing, because it is recognized that many analog functions can be realized with digital circuitry and sometimes even better than with an analog solution.

It is, however, due to the increase of system complexity that integrating analog and digital functions on one chip is becoming necessary. The emphasis lies in this case on the monolithical combination of digital and analog. This means that in many cases very high performance analog functions are not that much required and a greater number of mod- erate performance analog functions are preferred. Thus today combined analog and digital CMOS is in the center of interest. This involves three developments: First, there is the development of very well controlled CMOS technologies; second, there is the development of an analog CMOS cell library, and finally, there is the development of analog CMOS design tools (CAD). These three developments can be summarized as follows.

The integration of analog building blocks in a CMOS technology demands very good control of the many different process steps in this CMOS technology. Very good process control is necessary in order to achieve analog process requirements such as

minimum pn-junction leakage, good matching properties for active and passive components, precise resistor and capacitor ratioswith minimal voltage and temperature dependancy, reproducible and well-described (ac, dc, temperature dependant) behavior of the different active and passive components,

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00189219/87/060(M816$01.00 0 1987 IEEE

PROCEEDINGS OF THE IEEE, VOL. 75, NO. 6, JUNE 1987

reproducible and well-described lateral and vertical with an accent on the analog requirements. Hereafter, a bipolar devices. shortdescriptionofthestateoftheartinanaloaMOSbuild-

This describes in a nutshell which special requirements are demanded from an analog CMOS process.

In reference to analog CMOS building blocks and analog CMOS CAD, the state of the art can be summarized as follows.

Until recently, almost every analog CMOS function had to be designed completely by hand for i ts specific application. However, due to

man-power limitations, more stringent specifications, the high risk that the first design will not function cor-

increasing complexity, rectly,

it is necessary to automate the design process. The first step inthisdirectionisananalogCMOScelllibrarywhichmakes the design more reliable and allows shorter design times. The second step is the development of analog design tools (CAD) allowing to exploit an analog cell library to i ts full potential. One step further is the introduction of parameterized cells. The parameters permit the design of analog functions which are specific for an application, although these functions are still based on a cell library.

In this development, the time-discrete circuits such as switched-capacitor filters and converters played an impor- tantrole.Duetothegainedexperienceinthefieldofanalog CMOS so far, there is now also a general interest for continuous-time analog CMOS such as continuous-time RCfil- ters. Hence, there has been and still is a lot of activity in the field of analog building blocks and parameterized blocks.

Parallel to the development towards analog CMOS functions, there is adevelopment of mixed bipolar and ((3)MOS (BIMOS) technologies. The development of BIMOS technologies opens the way to new circuit designs combining MOS and bipolar on the same chip allowing optimal use of the different analog features of both active devices. There are many advantages to be expected with BIMOS processes. Several companies around the world are making major investments in mixed-processing technology, as described by Cole in a special report in Electronics [I]. Also, several universities aredeveloping BIMOS processes, such as the University of Waterloo, Ont., Canada.

It is interesting to note that the first mixed-technology activities date back to 1973 when RCA developed BIMOS techniques. RCA presented MOSlbipoIar operational amplifiers as early as in 1976.

It will be evident that this development by different research groups involves different variants of mixed-processing technologies, such as

a combination of a buried twin-well CMOS structure

* a bipolar-enhanced CMOS, or a combination of CMOS with an epitaxial bipolar pro-

with bipolar transistors on-chip,

cess.

Although we should not underestimate the impact BIMOS will have on circuit design especially if analog and digital are involved, wewill l imit ourselves in this report to analog CMOS. Therefore, Section I will only cover CMOS technology in relation to combined analog and digital design

ing blocks, fixed and parameterized, wil l beiiven in the following section (Section II) based on a subdivision into two types of analog MOS building blocks:

switched-capacitor building blocks (Section Il-A) and non-switched-capacitor building blocks (Section 11-B).

This division into two different groups of building blocks is, however, not very strict since, for example, amplifiers as non-switched-capacitor building blocks will be used in switched-capacitor filter modules. The third section will review the existing CAD tools for analog CMOS design. In the fourth section, some new proposals for analog CMOS CAD will be discussed.

I . STATE OF THE ART IN CMOS TECHNOLOGY

Today, all major semiconductor producers are introduc- ing 2-p-17 technologies into production or have done so in the previous year. A technology with such a feature size may handle circuits with a complexity of a 256-kbit dynamic RAM (DRAM). However, the learning curve for high yield and high reliability is still to be evaluated as so far there is not enough statistical information available.

The following generation in CMOS technologies with the smallest feature size somewhere between 1.5 and 1.25 p n is currently being evaluated in several process lines. Here, it should be possible to produce circuits with a complexity of a I-Mbit DRAM.

Tomorrow’s generation of circuits will need I-pn feature sizes or even less. The herefore needed technologies are under development at different manufacturing sites throughout the world as described in [2], [3].

Japanese IC producers seem to be in the front lines in this racetowards small featuresizes since they havealready presented different prototypes of I-Mbit dynamic RAMS at the ISSCC in 1985. Apart from a few American activities there is a gap between Japanese and the American and the Euro- pean IC producers. Recent efforts of European manufac- turers aim to make this gap smaller or even to eliminate it. Different laboratories are developing submicrometer technologies, which will permit to realize circuits with 4Mbi t DRAM complexity or even higher. These technologies will be available for production lines at the end of this decade.

Due to the developments described above it is important to use dimensionless design rules in terms of the length unit lambda.The minimum feature size is usually2 lambda. In this way, the design rules need not to be altered when the minimum physical feature size in the technology has advanced. The digital designs realized with the lambda design rules should scale automatically with the new lambda, though the implementation is less straightfonvard due to not-scalable spacings, for exampleconcerning latch- up. Special new technological solutions such as epitaxial materials, trench isolation, and indirectly, retrograde tubs will help to reduce latch-up sensitivity. Further, these solutions allow denser circuits. These and other different alter- natives of CMOS such as the choice between p- and n-well or twin-tub and the different types of isolation between the activecomponents are discussed in detail in Chen’s review- ing article [4]. This article gives a good presentation of the state of the art and the future trends.

H A B E K O ~ E et a/.: ANALOG CMOS CIRCUIT DESIGN 817

Table 1 Example of Analog Scalmg 1871 -_ - .- ~ _ _ _ _ .

Standard Analog V voltage K - ' I current K - l

W channel width K T K ' L channel length K - I K - I

t". oxide thickness K - ' K - '

CL total (thin) oxide capacitor - ( WL)/to, K - ' K - l

A T translstor area - (WL) K - Z K - l A, capacitor area - l/CO& - to, K - l K - '

- /( - 112

Cox thm oxide unit capacitance - l / tox K" K t '

weak inversion - / / (KT /@ transconductance gm strong inversion - JiiZTJ 1 K * l i l

swltchlng time - VCJ/ K - I

K - I 1

- i i l

A voltage gain weak inversion strong inversion

I- energy P power disslpation Plarea power disblpationlarea V i - noise voltage strong inversion v:,( equivalent low-frequency

noise voltage

- equivalent thermal weak inversion

The influence of the technology on the design of analog MOS circuits has been discussed in detail by Allstot and Black in a tutorial paper in the PROCEEDINGS OF THE IEEE [5]. They describe the components which can be realized in an NMOS or a CMOS process. Further, they discuss the achievable matching properties of these components. Noise, maximum voltage gain, offset voltage, common- mode range, power dissipation, power-supply noise rejec- tion, and more are discussed as well. Thus the technology influences the design of analog MOS circuits. One important conclusion is that for high gain and low noise the channel lengths of the MOS load transistors should be long. Fur- ther, the matching between transistors with similar layout geometry but in different locations is better with larger geometries.

Apparently, analog CMOS does not fit very well in the emerging VLSl technology. It i s less suited for scaling than digital CMOS, since it suffers more from shortthannel effects than digital CMOS. Table 1 gives an example of scaling. In order to cope with these problems it is necessary to have an analytical model allowing quantitative scaling into the submicrometer regime, for example the one described by Hoefflinger [6]. Apart from good analytical models for short-channel MOS transistors in analog designs it i s necessary to have a guaranteed stable process. Some of the most important requirements in relation tothis havealready been mentioned in the Introduction. Several authors, for example, Demler, Milkovic, Ribner, and Matsui, report analog MOS designs compatible with a short-channel VLSl technology (1 to 1.5 pm) in spite of the above mentioned problems [;7-[IO]. These analog designs, a 10-bit N D converter, a high-frequency amplifier with 1WMHz unity gain bandwidth, high-frequency switched capacitor filters, and video filters, show the high performanceavailablewith analog VLSI. The high-frequency amplifier proposed by Mil- kovic is depicted in Fig. l. Moreover, it is important to notice that the ditference in performance of PMOS and NMOS devices gets smaller as the transistor dimensions are reduced. This suggests the possibility of well-balanced active devices in submicrometer CMOS.

m- 'vDo

INPUT

Fig. 1. High-frequency amplifier [8].

Analog CMOS design will become more sophisticated and more competitive with analog bipolar design, as new possibilities for better process control are offered by the advanced I-pm and submicrometer CMOS technologies.

11. MOS ANALOG BUILDING BLOCKS

Two important remarks have to be madeconcerning most analog MOS building blocks described in the literature:

1) The building blocks are fixed on one technology and have to be redesigned (full custom and handcrafted) if the technology changes; therefore, they are not technology independent.

2) Most building blocks represent a fixed design which is not adaptable to specific demands. This is, however, necessary for correct analog design; therefore, they are not optimal in the implementation.

A. Switched-Capacitor Analog Building Blocks

MOS technology provides, especially in the field of sampled analog design, unique properties for the charge stor- age and transfer:


* MOS amplifier with negligible input current, MOS bidirectional (analog) switch, (MOS) capacitor.

It is due to these unique properties that in the switched- capacitor field many analog building blocks have already been proposed.

MOS amplifiers are surely one of the first analog MOS building blocks,which will beclearfrom thetutorial papers on MOS amplifier design such as those written by Tsividis [ I l l and Gray and Meyer [12]. More recently, Degrauwe, Mil- kovic, and Ribner show in their papers [13], [8], [9] that there are still new developments in this field. These MOS amplifiers together with MOS transmission gates as analog switches and combinations of unitcapacitors in arrays form the basic elements for switchedtapacitor filters. For the design of switched-capacitor filters the conventional filter design methods with reference filters can be directly exploited. The switchedcapacitor filter design approach has been described by many authors, for example by Brod- ersen eta/. and Gregorian eta/. in tutorial papers in the PRO- CEEDINGS OF THE IEEE [14], [15]. Also in NMOS technology, analog building blocks for a PCM Codec Filter chip have been developed as described by Senderowicz eta/. in [16].

This development of switched-capacitor filters has led to switched-capacitor filter blocks which can be exploited in larger filter systems, such as a programmable switched- capacitor bandpass filter, described by Hosticka eta/. [ I q . Some general-purpose first- and second-order switched- capacitor filter blocks have been proposed by Hoekenek and Moschytz [18].

Other switched-capacitor, non-filter-building blocks ranging from square-wave oscillators, AID and DIA converters, to balanced modulators, etc., have been described in the above mentioned tutorial paper by Gregorian et a/. [15]. McCreary, Suarez, McCharles, Demler, and Habekotte describe different approaches for AID or DIA conversion with switched-capacitor techniques [q, [19]-[22]. A recent paper describing a low-voltage high-resolution CMOS AID converter shows that currently still new converter designs or improvements of older designs are under development [23]. Goodenough reports in Electronic Design new archi- tectures and processes for advanced monolithic AID converters [24]. Especially the autocalibration techniques referred to in this report allow the MOS-based converters to reach very high resolution of 14 to 16 bits with short conversion times of about 20 to 60 ps.

Gregorian et a/. also present in their tutorial paper [I51 many examples of switchedcapacitor filter and non-filter switched-capacitor building blocks, implemented in larger systems such as a coder-decoder, a dial-signal receiver, a speech synthesis system, or a tracking filter. Two other recent papers, one by Oswald [25] on a dual-tone and modem frequency generator and one by White [26] on a dual-tone frequency receiver, show again the possibilities of analog switched-capacitor building blocks. This holds in particular for the switched-capacitor voltage reference circuit which is described by Oswald eta/. Another nice and recent example of cell-based semicustom analog design technique for switchedcapacitor filters, AID and DIA conversion systems, and interfacecircuitry has been presented by Pletersek et a/ . [27.

A very important aspect of switched-capacitor design is

the possibility of compensating offset and low-frequency noise by double-correlated sampling. The low-frequency noise introduced by the MOS signal-processing circuit can also be shifted towards higher frequencies by frequency multiplication so that it can be avoided in the baseband. These compensation techniques are discussed by Grego- rian et a/ . [I51 and show the importance of the switched- capacitor design approach as they relax the limitations of MOS for analog circuits to a certain extent. Abe et a/ . give another good example of using chopper compensation techniques in their paperon an ultra-low driftamplifierwith a MOSFET chopper [28]. Another author, Klein, reported noise reduction for CMOS amplifiers with chopper tech- niquesin hispresentationattheESSClRC1984inEdinburgh [29]. At the ESSCIRC 1986 in Delft, a chopper amplifier with a second-order low-pass selective amplifier was presented by Enz [30]. In order to limit the contribution of the spikes due to charge injection, the spectrum of these spikes at the odd harmonics of the chopper frequency is effectively low- pass filtered by the selective amplifier. This chopper amplifier is shown in Fig. 2.

Fig. 2. CMOS chopper amplifier [30].

Proposals for switchedcapacitor solutions have also been made in the field of nonlinear circuit design. For example, a German research group developed several nonlinear analog switched-capacitor building blocks for a switched- capacitor FSK modulator and demodulator [31], [32].

So far, standard analog cell approach has been described. There are, however, gate or more appropriately transistor array approaches for analog switched-capacitor circuits. One very interesting transistor array was described by Kash in a presentation at the Conference on Custom and Semi- Custom ICs [33]. It allows digital circuits and analog circuits to be realized on one and the same prefabricated chip. These analog building block% realizable with one metal mask on the transistor array include amplifiers, a bandgap reference, comparators, and switchedtapacitor filters. Another array presented by Caillon at the ESSCIRC [34] permits only switched-capacitor filters with a universal switchedcapacitor structure using foldedcascode amplifiers as basic building blocks for sampled data filter design as mentioned before. Although it does not really belong in a review of IC-design building blocks it isworth mentioning that several universal programmable switched-capacitor filter chips in a dual-in-line package are available today, for example, the one described by Lacanette recently in an issue of Electronic Design News [35]. This suggests the possibility of programmable building blocks.

HABEKOlTE et a/.: ANALOG CMOS CIRCUIT DESIGN 819

In conclusion to the discussion on switchedcapacitor building blocks, Figs. 3 and 4 give two other examples of switched capacitor solutions for particular applications, referred to in the next section on non-switchedcapacitor building blocks. Fig. 3 concerns a switchedeapacitor current source and Fig. 4 shows the principle of a switched- capacitor temperature measurement.

Fig. 3. Current reference [59].

Fig. 4. CMOS SC temperature measurement [52].

B. Non-Switched-Capacitor Building Blocks

Although the exploitation of switchedcapacitor circuits as building blocks has spread out widely, one should not forget the efforts directed towards non-switchedcapacitor, analog building blocks such as the I b i t building block for 20-MHz AID converters or the pulsedensity modulator for high-resolution AID converters both developed by Fiedler [36], [371 and the designs for operational amplifiers (especially those for resistive loads) [MI-[42]. A recent presentation at the ESSCIRC 1986 by Fischer describes a highly linear CMOS buffer amplifier for resistive loads down to 100 n (431, which is depicted in Fig. 5.

One important difference between an amplifier for continuous-time and discretetime applications is the constraint on the linearity and the offset. In discrete-time applications, for example, it is unimportant how the output of the amplifier slews and settles to i ts final output level. It is onlyimportantthattheamplifiersettleswithinacertaintime slot given an allowed error.

Other examples of continuous-time building blocks are programmablevoltage sources, comparators, and bandgap voltage references as described by Stone et a/. in (441 and Vittoz in his presentation at the ESSCIRC 1984 in Edinburgh

vB2 0 I

V B I 0 I'i Fig. 5. Highly linear CMOS buffer amplifier [43].

(451. Bandgap voltage references in CMOS exploit the exis- tence of parasitic vertical or lateral bipolar transistors with the well as base. A good example of such a bandgap reference is described by Degrauwe et a/. in a recent paper [46]. The principle of this reference is shown in Fig. 6. Other

T

"REF

Fig. 6. Voltage reference [ a ] .

references use the difference between the threshold volt- ages of different types of MOS transistors, as described in (471. Vittoz and Fellrath propose special voltage references based on the weak-inversion mode of MOS transistors in their paper (481. The channel current of an MOS transistor in theweak-inversion modedepends logarithmicallyon the input voltage in a similar way as with bipolar transistors. Voltage and current references are important for an opti- mum setting of transistor bias points, which is critically important for high-performance CMOS analog circuits. A central bias generator circuit producing a referencevoltage and adistribution of this reference across the chip through slave bias cells is therefore important in every analog standard CMOS cell library as discussed at the ClCC Confer- ence in 1986 (491. For voltage references there are intrinsic physical values, which can be extracted by adequate circuits as described above. However, semiconductor physics do not provide any "built in" current. Therefore, current references have to be derived from voltage references by converting the reference voltage into a current with a resistor. This results in an inaccurate current reference due to theerrors introduced bythe resistor. Klein presented agood switched-capacitor solution for an accurate current reference at the ESSCIRC 1983 in Lausanne [50] (Fig. 3).

820 PROCEEDINGS OF THE IEEE, VOL. 75, NO. 6, JUNE 1987

The possibility to create a reference voltage on an MOS chip implies that it is possible to measure the temperature. This is in many cases necessary for correct on-chip temperature compensation such as described by Shenton in [51] for temperature compensation of onchip Hall sensors. Habekotte discusses different approaches for temperature measurement in CMOS [52].

The weak-inversion mode as described above is only practical at low current levels (<I-5 PA), so that it does not allow high-frequency performance. However, high-gain amplifiers with very low current consumption can be realized using the input transistor(s) in weak inversion. This is especially of interest for battery-powered electronics. Tee1 and Wayne describe a standard cell approach utilizing subthreshold building blocks for implantable medical electronic devices [53].

Other time-continuous building blocks getting attention nowadays are the fully integrated active RCfilters. They do notsufferfromnoisealiasedfromthefrequencybandabove the sampling frequency because they are continuous-time. Thus anti-aliasing filters and on-chip clock generators can be avoided. Yet, a totally differential filter structure is needed in order to minimize second- (even-) order distor- tion components with balancing techniques. In these filters, MOS transistors in the linear part of their output characteristics are exploited as resistors. In order to guarantee a correct time constant, an on-chip tuning circuit adjusts the channel resistance by changing the gate voltage of the used transistors. Fine tuning is realized by adjusting the gate voltage so that an on-chip oscillator realized with the same continuous-time filter structures i s tuned to an exter- nal clock. Banu andTsividis[54] introduced such afullyinte- grated active RCfilter in 1983. Pennock eta/. demonstrated in their presentation [55] at the ClCC Conference some advantages of integrated continuous-time filters over switched-capacitor filters.

In the non-switched-capacitor area there are gate arrays which permit to realize analog functions as well. Watson, for example, proposes several analog building blocks in his paper [56] for a CMOS gate array where it is possible to realize analog functions, such as comparators or amplifiers, in the periphery. Another transistor array described by Pick- erell allows to implement analog functions throughout the

whole gate array whether they are switched-capacitor or not [57l.

Several silicon foundries do offer cell libraries with analog building blocks. They allow to use comparators, amplifiers, and voltage references in their standard cell design, as explained in publications such as [58]. Not many vendors allow the use of weak inversion for very low power consumption and offer special cells for this purpose. And only in some cases also switched-capacitor building blocks and A/D and DIA converters are being offered in the standard cell documentation besides cell libraries with the classical analog functions such as comparators, amplifiers, and references.

C. Summary

Although the subject of building blocks have not been discussed exhaustively, it will be summarized in the following six tables:

Table 2 gives several specifications of a few MOS amplifier building blocks found in the literature.

Table 3 shows the most important characteristics of a few MOS amplifiers for resistive loads.

Table 4 gives an overview of existing switched-capacitor building blocks.

Table 5 presents examples of integrated systems using switched-capacitor building blocks.

Table 6 presents examples of analog integrated circuits, which do not exploit switched-capacitor techniques.

9 Table 7presents several advanced monolithicND converters [24].

Thesetables indicate how much building blocks are being used for integrated circuit design. Further, they suggest how effective a library of building blocks can be.

However, another very interesting trend is set by the self- adjusting or self-calibrating circuit technique. Compared to earlier techniques, where laser trimming and better matching of bipolar devices were used to realize high-performance analog circuits, self-adjusting techniques open a new area of high-precision ICs. One representative example is the clock-controlled continuous-time RCactive filter [54].Anotherimpressiveexampleisaone-chipfullyselfcal- ibrating 12-bit ADC [24]. These techniques allow high- precision analog ICs, even in a VLSl environment. And

Table 2 Several Characteristics of Some MOS Amplifiers Found in the Literature

Slew Bias Unity-Gain Rate Gain Current BW, C load

Reference Configuration (V/PS) (dB) (PA) (MHz) (pF)

current mirrors 200 69 50 70, 1.0 Milkovic’M [8] one-stage with stacked

Stone’M [MI two-stage strong and 1.8 91 5 1.0, 1.2 weak inversion 0.039 107 0.2 0.058, 0.5

Degrauwe’M [13] adaptive biasing cascode output strong and 1 .o 60 0.74 0.1, 10.0 weak inversion 3.3 60 0.22 0.05, 10.0

Ribner’85 [9] foldedcascode 68.5 250 80, 1 .o Tee1‘85 1531 two-stage in weak

inversion pchannel input 0.038 101 0.01 0.11, 5.0 nchannel input 0.022 107 0.01 0.11, 5.0

HABEKOTE et a/.: ANALOG CMOS CIRCUIT DESIGN 821

Table 3 Several Specifications of Some MOS Amplifiers for Resistive Loads Found in the Literature

DC Quiescent Unity-Gain Output power Gain Power BW, C load

Reference Configuration (mW in resist.) (dB) (mW) (kHz) (pD

Maeding’83 [MI class B 160 in 100 Q 78 7 260, ?

Saari’83 [39] three stage 30 in600Q 84 8 80% 160

Brehmer’83 [a] class AB 36 in 300 Q 83 5 420, loo0

Fixher’85 [41] class AB 24 in 200Q 93 12.7 1200, lo00

Fischer’86 [42] mixed PMOS and 100 in 100 Q 82 19 3500, ? n-MOS folded- casc. inputstage + output buffer

Hosticka’82 [32]

Gregorian‘83 [15]

Table 4 List of Several Switched-Capacitor Building Blocks Found in the Literature

Reference Building Block

Martin’81 [59] phase-lock loop tracking filter programmable equalizer synchronous demodulator adaptive channel equalizer

Schmitt trigger phase comparator interpolative N D converter phase reverser

biquad and ladder filter blocks digital-to-analog converter analog-to-digital converter voltagecontrolled oscillator continuous-time peak detector balanced modulator full-wave rectifier

Hoekenek’83 (18) first- and second-order filter blocks

Oswald’84 [X] voltage reference

Klein‘83 [MI current reference

Habekotte [52] temperature measurement

moreover, the overhead due to integrated controllers or similar building blocks is further reduced due to this technological advance. Local intelligence has brought the important breakthrough in the digital areawhen manyyears ago the integrated microcontroller or microprocessor was introduced. Today, the implementation of self-adjusting or selfcontrolling analog circuits may be the breakthrough for analog high functional density circuit techniques.

Ill. CAD FOR ANALOG MOS DESIGN

Before discussing CAD for analog MOS design an overview of CAD for digital MOS design will be given to dem- onstrate i ts current state of the art.

A. State-of-theArt Digital MOS Design

i n the current digital CAD market a large number of vendors is active, offering products ranging from simple layout editors to completed integrated design systems. Current CAD packages can be divided into two separate groups:

design tools, covering only a specific part of the design path,

Table 5 Examples of Integrated or Discrete Systems Using Switched-Capacitor Building Blocks

Area Reference Function ( m m 3

White‘79 [261

Senderowicz’82 [16]

Martin’83

Oswald’84

Hosticka’M

Fotouhi’84

Tsu kada’85

Hauser’85

Levy ‘85

Matsui‘85

Dingwall’85

dual-tone multifrequency

PCM codec filter (NMOS)

spectral line enhancer

dual-tone and modem frequency generator

receiver

FSK modulator FSK demodulator

analog front-end for high-speed modems

abit 2EMHz flash ND converter

MOS AID converter and filter

four-channel call progres detector

video filters

&MHz subranging &bit N D converter

30.0

24.0

discrete

9.1

1.3 6.6

31.5

21.6

4.5

-

32.4

7.0

Table 6 Examples of Non-Switched-Capacitor Analog Integrated Circuit Designs

Area Reference Fun’ction (mm2)

latched comparator

Soo’85 1661 750 megasamples/s

Sau1’85 [67l &bit video DAC

Band85 1681 elliptic continuous-time filter

1.0 (active)

4.0 (active)

Babnezhad’85 [69] fourquadrant analog multiplier

design systems, covering the complete design path

A n intermediate between these two groups is the toolbox concept:

from schematic entry down to CIF tape.


Table 7 Some Features ot Advanced Monolithic A/D Converters with Autocalibration ~ 4 1

Conversion Resolution Time (25 C) Sampling

(bits) On-Board

( 1 s ) Capability Clock Reference Principle Process

16 20 Yes no no succ. approx. CMOS 14 20 Yes no no 12

succ. approx. CMOS 20 Yes no no succ. approx. CMOS

12 1 Ye5 no no two-step CMOS

12 25 Yes Yes succ. approx. BlMOS Yes Yes Yes Ye5 succ. approx. BIMO5 12 15

a number of separate design tools are packed together. Suitable interfaces are added to enable the transfer of data between the different tools.

For design tools, well-defined interfaces to an existing design environment are of extreme importance. For design systems, this is a less severe constraint, or sometimes it is even undesired. The only interface important for an integrated design system is i t s interface to the foundry.

Almost all current state-of-the-art CAD packages support a hierarchical design approach which is usually carried out insuchawaythatthedesignisspecifiedinatop-downfash- ion. Depending on the implementation chosen, the data can either be transferred to the foundry in the form of a netlist (gate-array implementation), or the designer can use the topdown specified circuit data in a bottom-up fashion to design and/or assemble the layout of the circuit. In this case, atape containing geometrical datawill be handed over to the foundry. Currently, no design systems are available which allow adesigner to work in a strict top-down fashion. Des@ systems leaning towards such an approach are sold under the name of silicon compilers.

The first step in the design of a circuit is usually the schematic entry of the circuit. As it has already been stated pre- viously, the specification will be done in a top-down fashion. If available, a high-level functional simulator will be used to verify the correctness of the circuit specification. During this phase the designer is confronted with several choices concerning the implementation of the different functions:

Using megacells for implementing complex functions. CurrentIy,anumberofsiliconvendorsofferawiderange of megacells, ranging from simple peripheral circuits UP to complete microprocessor cores. Using standard cell libraries. Using parameterized cells, to compile different func-

Using full custom functions, constructed with a geo-

Using a gate-array implementation.

tions (e.g., ROM, shift registers, PIAS, etc.).

metrical layout editor or a stick editor.

The application of the different concepts either mixed or constrained to one concept only, will depend on factors such as:

the design system or tools used, the foundry which will manufacture the circuit, the circuit application demands, how fast it should be implemented, etc.

The designer will evaluate the applicability of the different concepts on a per-function and per-level base accord-

HABEKOTTE et a/.: ANALOG CMOS CIRCUIT DESIGN

ing to his system partitioning results. This will start at the system level, where he encounters functions such as mem- ory, ALUs, etc., [70]. One can state that currently no tools or design systems are available which support the designer in this decision process. Usually, the designer will make thesedecisions basedon"back-of-the-enve1ope"sketches. Some work is under way to fill this gap [71].

The designer will ideally.choose on a per-function base which implementation concepts he wants to use. After the designer has chosen how to implement a function (or decompose it again in a number of subfunctions), he can use different tools to realize these implementations, such as:

a layout editor, either symbolic or geometrical; acell compiler, acceptinga parameterized description as input, resulting in a layout description (with or without a simulation model); a standard cell placement and routing tool; a full custom placement and routing tool, placing and routing ordinary sized blocks.

Using a layout editor to realize a certain function will usually only happen at the lowest levels of the hierarchy: con- structing leaf cells. At these levels, the designer can also compare the performance of the different functions with their predicted behavior using an extractor and a timing simulator (e.g., SPICE). At subsequent levels (as stated before we are following a bottom-up construction in the layout of the circuit), the place and route tools will be used. Analysis of realized functions with the help of a timing simulator will become too tedious. Along this process of bottom-up construction, the designer will also use tools such as design rule checkers, netlist compare, and electrical rule checkers. If possible, a critical path extraction and analysis will be done.

More advanced design tools or systems also support the designer in the preparation of test vectors. Support for scan test may beavailable, with or without automatic test pattern generation.

Concluding, one could state that the state-of-the-art design tools and systems show the following deviations from what would currently be seen as the ideal design environment:

support on the system design level, advising the designer during system partitioning on items such as test strategy, floorplanning, and design tradeoffs;

a higher degree of technology independence, especially in the area of cell libraries, parameterized cells, and simulation models;

823

significantly more support on the implementation of different types of test strategies;

enabling the designer to change from one foundry to another without significant problems.

In spite of the enormous development of computerized digital design tools and the state of the art as described in the previous paragraph, analog CAD has not evolved in the same way. This is due to the fact that in analog circuits the signals have a continuum of values for amplitude and time and, hence, the components also have a continuum of Val- ues. This makes the modeling of analog circuits far more complex than the modeling of digital circuits, where the signal is at least limited to a finite number of values (usually two: 0 and 1) with a discrete elapse of time.

Today, some developments towards analog CAD can be recognized apart from the already existing simulation programs such as SPICE with all i ts different versions [72] at component level, or SWITCAP [73], which is specifically meant for discrete-time circuits, and DIANA [74], which allows simulations at component level but also at system level due to its so-called mixed mode.

Computer-aided design of analog integrated circuits was reviewed by Allen in a tutorial paper at the ClCC Confer- encein1986[75].Thispaperdiscussesfirstthedifferentana- log design methodologies which can be divided into five different categories:

single-component arrays, circuit arrays,

* standard blocks (megacells), parameterized blocks, programmable chips.

In many cases, the CAD is limited to placing and routing standard fixed cells using the metal interconnection mask. Schematic entry of the design is usually possible and the design can be simulated with one of the above mentioned simulation programs. Only the parameterized blocks allow some adaptation of the blocks to the specific application. The programmable chips provide only a very narrow range of applications, an inefficient use of area, and a limited performance. They do not really fit in this discussion.

Analog CAD has mainly developed in the field of switched-capacitor building blocks, because in the discrete-time domain the design is relatively straightforward andisinmostcaseslimitedtothecorrectchoiceofbuilding blocks and the calculation of the capacitor ratios (values). Severalauthorsclaim in theirpaperstodescribeaswitched- capacitor filter compiler, and show proven designs [76]-[79], but it would probably be more appropriate to call these programs assemblers.

Kimble et a/. proposed additionally a strategy for autorouted analog VLSl in a presentation at the ClCC Confer- ence in 1985 [80]. This analog router keeps sensitive terminals, which have to be interconnected with other blocks, within special analog routingchannelssothat parasiticcou- pling can be minimized. Other sensitive terminals are kept inside the analog building blocks in order to avoid unwanted parasitic coupling. The authors provide four examples of chip designs realized with this assembler.

The calculation of the capacitor ratios introduces parameterized blocks into the design methodology. Some special approaches are described by Pletersek et a/. in their

paper [27]. These special approaches allow interesting layout solutions for the capacitor arrays, where capacitors are grown from a "capacitor seed."

Before concluding this section on analog CAD two other analog silicon assemblers should be mentioned. One assembler [78] permits the generation of a layout descrip tion of an AID or a D/A converter from resolution and linearity specifications. The assembler exploits charge redistribution techniques as described by McCreary et a/. [I91 and Suarez et a/. [20]. Thus the assembler is restricted to 'converterswith a successiveapproximation using a resistor string to decode the more significant bits and a binary weighted capacitor array to decode the less significant bits or the other way around. The assembler will determine the best configuration, if at all possible, depending on the achievable matching within the string and the array and given a certain resolution and linearity for the converter. The layout is realized with the same program which is used for switched-capacitor filter design [81].

Especially the description of a program presented by Degrauwe at the ISSCC 1984 is of interest in the discussion on analog MOS building blocks [82]. It permits to dimen- sion an MOS amplifier selected from a limited number of possible amplifiers according to what is actually needed. In every new design the environment of an amplifier changes, which means that the amplifier block has to be redesigned in order to be optimal in the given application. By taking different amplifier configurations and recalcu- lating the dimensions of the MOS transistors it is possible to have adaptable cells in a larger system. The layout for the amplifier is generated with the new dimensions of the transistors using a symbolic layout, which is in this case a stick diagram. This stick diagram fixes only the relative position of the different transistors to each other and guarantees similar layouts for one and the same amplifier for different applications. This is, however, only possible within a limited range of (WIL) ratios of the MOS transistors due to oth- erwise too inefficient use of silicon real estate.

It is, in fact, necessary to every analog building block to beadapted to itsenvironment, but sofar new specifications still mean to redesign a new full custom analog cell or to accept the limitationsof afixed analog building block. Even the switchedcapacitor parameterized cells are not really adaptable since a change of the feedback capacitor should be followed by adaptation of the amplifier design to this new load.

B. Future CAD for Analog M O S Design

If we draw a parallel to the current developments in the area of digital CAD and compare them with the results in the literature study of the state-of-the-art analog MOS CAD, future analog/digital MOS design tools should develop the following capabilities:

system level support for the designer, including high- level functional simulation; extended use of parameterized cells; place and routing tools which will take analog design constraints into account; suitable test strategies; a higher degree of technology independence; the possibility to introduce autocalibration techniques.

824 PROCEEDINGS OF THE IEEE, VOL. 75, NO. 6, JUNE 1987

An essential part of mixed analogldigital design will be the floorplanning. Because of the far-ranging implications of analog cells on the floorplanning operation, it will no longer be feasible for a designer to perform manual place and route operations. This will lead towards a strict topdown approach, where circuit partitioning and floorplan- ningare parallel operations. When thedesigner has reached the lowest level of specification, bottom-up construction of the circuit will consist only of filling up the empty floorplan modules. Such a“true” hierarchical approach towards circuit design would also support the implementation of a straightforward test strategy. Currently, the only feasible test strategy consists of isolating the analog from the digital functions, enabling separate testing of both worlds.

The usage of parameterized cells has several advantages over the usage of full custom cells:

It provides an implementation concept, which enables a more technology-independent approach.

It will ease the test problem slightly because of the

Only in this way it is possible to adapt the building block to the actual implementation and to give a certain guarantee that the first silicon will be correct. Future CAD tools, however, should also permit a topdown design of mixing analog and digital systems. In order to realize top-down design, a hierarchical approach has to be implemented in the CAD tool. One very important part of such a tool will be the high-level verifier (simulator) which allows to get a feeling of the performance of the total system without directly going into details. If the design corresponds with the specifications at this high level, one can fill in details of the different blocks in the design. This will be done by going down in the hierarchy and by simulating, for example, a switchedtapacitor filter with SWITCAP or an amplifier with SPICE as local simulators. Certain details, such as noise or limited gain-bandwidth, found with the local simulator can be reintroduced in the high-level simulator in order to verify the validity of the total system. Further, it should be possible to adapt the analogldigital building blocks to the actual technology in which they have to be realized.Thiswouldallowadevelopmentinthetechno1ogy without a redesign of the cells whenever the technology advances. As the blocks have to be adapted to the actual implementation through its parameters, synthesizers are needed. Fig. 7 gives an impression of the hierarchical configuration of the CAD tool as described above. Fig. 8 shows the basic concept of the database with the cells and the synthesizers. The different types of cells may need different simulators, but the whole system should be simulated with an overall verifier (simulator).

The parameterized cells may include amplifiers, comparators, oscillators, or larger building blocks such as filters and converters. Their use implies, however, a limited number of fixed configurations, since they have to stay adaptable. Although it .is not optimal to design with a limited number of fixed configurations, such a library of cells allows fast turn-around times.

The performance of this CAD tool can be summarized as a topdown design of integrated circuits implementing a library of analogldigital building blocks which can be adapted to the technology in which these have to be realized. This involves the following:

usage of “test libraries.”

Tf”’:”’:”””l CONCEPT

DATA BASE describing

of BUILDING BLOCKS

BUILDING BLOCKS

of BUILDING BLOCKS wilh PARAMETRICAL ADJUSTMENT

POSSIBRITIES

i t

BUILDINGS BLOCKS BLOCK LAYOUT STICKDIAGRAMS

I TECHNOLOGY DESCRIPTION

Fig. 7. Hierarchical conJguration of a CAD tool.

ELECTRICAL MSCRIPTION (FUNCTION) (REALISATION)

\r‘

h

1 r h h DATA BASE

EUILOING BLOCKS I I ITYPElI I

I ‘ i l

SILICON SYNTHESIZER

OVERALL SIMULATOR BUILDIUG BLOCKS

i SVNTHESIZER I

SYNTHESIZER II LOCAL SIMULATORS

4 I

[LAYOUT] i

Fig. 8. Basic concept of analogldigital silicon synthesizer.

High-level functional simulation allowingthedesigner to estimate the validity of a design concept at an early stage of the design.

The use of different “local” simulators (such as SPICE or SWITCAP). This permits to extract details of the electrical performance of the implemented building blocks and their influence on the design concept. These details can be reintroduced in the functional simulator in order to verify their influence on the total system behavior; an example is the frequency behavior of an amplifier calculated by SPICE as local simulator.

The introduction of synthesizers makes it possible to adapt the building block to its electrical and physical environment, permitting a technologically independent CAD system (restricted, however, to CMOS technologies).

For a realistic and fast CAD system, a limited number of building blocks with general electrical, general performance, and general physical (stick-diagram) descriptions have been defined in the database.

The system has a modular structure so that at any time, when a new type of building block is found necessary, it can be added to the database with the necessary descriptions. The synthesizer for this new building block has to be introduced as well.

For proper choice and correct definition (standards)

HABEKOlTE et a/.: ANALOG CMOS CIRCUIT DESIGN 825

of the building blocks and database, at f irst a study is necessary in order to model and correctly characterize the CMOS technology. Hereafter, the necessary parameters to characterize the building blocks can be chosen; this is meant to be routinely used (standard CMOS analog/digital building blocks).

Realization and evaluation of building b locksand the i r implementation in an evaluation circuit of greater com- p lex i ty than only o n e building block a l lows to ver i fy the results both of C A D tools and database as we l l as i ts management.

D u e to the l im i ted per fo rmance of these cells with f ixed configuration, it cannot be expected that h igh-performance analog or d ig i ta l c i rcui ts in front-end designs can be realized with them. Especially, high-performance analog f rontend des ignsare handicapped.Therefore, theCAD tool has to permi t a design with analog primit ives such as transistors biased as common source or common drain, etc. Nordhol t descr ibes a straightforward synthesis approach using bipolar primitives[83].This synthesis has proven itself with many high-performance analog bipolar designs [84]- [861.

ACKNOWLEDGMENT

Theauthorsare indebted toEurosi l (Germany)and Sagan- tec (The Netherlands) for discussions concerning analog CMOS CAD. They a lso wish to thank S. Kruger for typing the manuscript, C. Weisskopf for making thedrawings, and H. Schmidbauer for taking the photographs of the authors.

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HABEKOlTt et a/.: ANALOG CMOS CIRCUIT DESIGN 027

E. H. Nordholt and L. P. de long, “The design of extremely Information Sciences Center at the University of Minnesota, Min- low-noise camera-tube preamplifiers,” /E€€ Trans. Instrum. neapolis, MN. He became Head of the School of Electrical Engi- Meas., vol. IM-32, no. 2, pp. 331-336, June 1981. neering at Purdue University, West Lafayette, IN, in 1984. In the fall 5. Wong and C. A. T. Salama, “Impact of scalingon MOS ana- of 1985, he was appointed Director of the Institute for Microelec- log performance,” /E€€ 1. Solid-State Circuits, vol. SC-18, no. tronics, a public research foundation, in Stuttgart, West Germany. 1, pp. 106-114, Feb. 1983. He has authored or coauthored over 100 publications and has

Dr. Hoefflinger received the 1968 Award of the German Nach- edited and co-authored two books on microelectronics.

Bernd Hoefflinger was born in 1939 in Bucharest, Romania. He studied physics in Goettingen and Munich, West Germany, and received the diploma degree from the University of Munich in 1964, and the Doc- tor rer.nat. degree from the Technical Uni- versity of Munich in 1967.

From 1964 to 1967, he was associated with the Siemens Research Laboratory in Mun- ich.From1%7to1970,hewasAssistantPro- fessor in the School of Electrical Engineer-

ing, Cornell University, Ithaca, NY. From 1970 to 1972, he was Manager of the MOS Integrated Circuits Department, Semicon- ductor Division Siemens AG, Munich. In 1972, he became Profes- sor of Electrical Engineering and the founder and first dean of the Electrical Engineering Department at the University of Dortmund, West Germany. There he was also director of the Electron Devices Laboratory. During 1979-1980, he spent a half-year sabbatical with the Electronics Research Laboratory at the University of California, Berkeley. From 1981 to 1983, he was head of the Department of Electrical Engineering and codirector of the Microelectronics and

richtentechnisihe Gesellschaft and the 1969 IEEE ISSCC Outstand- ing Paper Award. He is theco-recipient of the 1980 Darlington Prize of the IEEE Circuits and Systems Society and of the 1982 Electronics Letters Premium of the British IEE. He became a member of the Dusseldorf Academy, one of the five German Academies of Sci- ence, in 1981. From 1973 to 1977, he was an Associate Editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES.

Michiel A. Beunder was born in Merauke, Dutch New Guinea, on October 31, 1959. He received the masters degree in electrical engineering and in computer science in June 1985.

He had his first VLSl experience during the VLSl Program of Dr. Craig Mudge in Adelaide, Australia. From 1984 till July 1985 he worked at Philips Telecommunications Industry, Hilversum, The Netherlands, on VLSl design strategies based on the usage

of quality factors. He joined the Institute for Microelectronics Stuttgart, West Germany, in September 1985. He currently holds the position of group leader VLSl Design and Computer Services. HisinterestsareVLSl system design, siliconcompilation,operating systems, and computer architecture.

a28 PROCEEDINGS OF THE IEEE, VOL. 75, NO. 6, JUNE 1987

state of the art in the analog cmos circuit

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