• State Machines

• Timing

• Computer Bus

• Computer Performance

• Instruction Set Architectures

• RISC / CISC Machines

Combinational vs. Sequential Logic

• There are two types of “combination” locks

4 1 8 4

30

15

5

1020

25

Combinational:Success depends only onthe values, not the order in which they are set.

Sequential:Success depends onthe sequence of values(e.g, R-13, L-22, R-3).

A Computer is an example of a Sequential Circuit

Information Storage:

D Flip Flop (D Latch)

D | Qn+10 | 01 | 1

Register

• A register stores a multi-bit (vector) value.– We use a collection of D-latches, all controlled by a common write

enable pulse, call it WE.– When the write enable WE=1, the n-bit value D is written to register.

Timing Diagram ConventionsTiming Diagram Conventions

Back to our Sequential Logic

This one.

4 1 8 4

30

15

5

1020

25

Combinational:Success depends only onthe values, not the order in which they are set.

Sequential:Success depends onthe sequence of values(e.g, R-13, L-22, R-3).

A Finite State Machine

• Combinational logic– Determine outputs at each state. – Determine next state.

• Storage elements– Maintain state representation.

State Machine

CombinationalLogic Circuit

StorageElements

Inputs Outputs

Clock

The Clock• Frequently, a clock circuit triggers transition fromone state to the next.

• At the beginning of each clock cycle, the state machine makes a transition, based on the current state and the external inputs (Synchronous).

– Not always required. In lock example, the input itself triggers a transition (Asynchronous).

“1”

“0”

timeOneCycle

State

• The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken.

Finite State Machine

• A description of a system with the following components:

1. A finite number of states2. A finite number of external inputs3. A finite number of external outputs4. An explicit specification of all state transitions5. An explicit specification of what determines each external

output value

• Often described by a state diagram: - The set of all possible states.

- Inputs that trigger state transitions.- Outputs associated with each state (or with each

transition).

State of Sequential Lock

Our lock example has four different states, labelled A-D:

A: The lock is not open,and no relevant operations have been performed.

B: The lock is not open,and the user has completed the R-13 operation.

C: The lock is not open,and the user has completed R-13, followed by L-

22.

D: The lock is open.

State Diagram

• Shows states (e.g. A) and actions (e.g. R-13) that cause a transition between states.

Another Example of a State Machine

Repeat Forever:

• Fetch Instruction

• Fetch Operand(s)

• Execute Operation

• Store Result

• Check for Interrupt

Computer Bus

Buses are composed of three sets of lines

Not all devices will use all lines in each category

Synchronous Timing Diagram

Asynchronous Timing – Read Diagram

Asynchronous Timing – Write Diagram

Assessing Computer Performance

• Clock Speed ?• Response time ?• Throughput ?• Response Time or Throughput for what type of

application(s) ?• Power Consumed ?• Cost ?• Reliability ?• Ease of Use ?• Applications Supported ?• Portability ?• Access ?• ?

Instruction Set ArchitecturesWhat impacts a machine language instruction format ?

• Operation codes• Number of Operands (Source and Destination)• Address Modes• Address Range• Address Granularity (Byte, Word, etc)• Number of Registers (and Register Sets)• Types of Processing (String, integer, FP, Arrays,..)• Machine Word Length• Variability of Instruction Length• Context Switching Support• Stack Support• Interrupt Support • Operating System Support• Applications (Computation, Control, Embedded System, Data base, • HLL Languages Supported• Hierarchy of “Versions”• Speed Requirements• I/O Support• Instruction mix•

Number of Operands

• 3 Operands

• 2 Operands

• 1 Operand

• 0 Operands

Addressing modes

• Immediate• Direct• Indirect• Relative• Register Indirect• Displacement (Base-Register, Indexing, Pre/Post

indexed)• Stack

Designing an ISA

• 8 Bit words

• 16 Bit words

• 32 Bit words

• Multiple words

CPU HardwareWhat might be added ?

• Register Sets

• Stack

• Longer Instruction Register

• Address Registers

• Context Switch Registers

• Cache

• Partition Pointer Registers

• CISC – Complex Instruction Set Computer

• RISC – Reduced Instruction Set Computer

• Superscalar – Multiple similar processing units are used to execute instructions in parallel

• Multicore – Multiple Processors executing instruction in a complementary way

•

Some Classes of Today’s Computer Architectures

Driving force for CISC• Software costs far exceed hardware costs• Increasingly complex high level languages• A “Semantic” gap between HLL & ML• Word size was increasing.

• This Leads to:– Large instruction sets– More addressing modes– Hardware implementations of HLL

statements

Intention of CISC

• Ease compiler writing

• Improve execution efficiency

• Support more complex HLLs

RISC

Key features:

– Large number of general purpose registers

(or use of compiler technology to optimize register use)

– Limited and simple instruction set

– Emphasis on optimising the instruction pipeline & memory management, i.e. leverage newer hardware complexities now potentially available.

RISC Characteristics

• A Single Instruction size, typically 4 bytes

• A small number of data addressing modes, typically less than 5

• No indirect Addressing that requires two memory accesses

• No operations that combine load/store with arithmetic

• No more than one memory addressed operand per instruction

• No arbitrary data alignment for load/store operations

• Large number of instruction bits for integer register addressing, typically at least 5

• Large number of instruction bits for FP register addressing, typically at least 4

Which is better?• Is the execution of large special purpose

instructions more efficient than execution of many simple instructions ?

• Which programs are really “shorter” ?• Which are really faster ?• What is the impact of having to support many

languages?• What are the legacy challenges ?• What are the cost tradeoffs ?• Can compilers be better made to exploit CISC or

RISC better ? Complexity ?• Which can better exploit hardware features ?

Characteristics of Some Example Processors