spanish contribution to aida and other related issues. december 16 th ita, zaragoza. iván vila...
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Spanish contribution to AIDA and other related issues.
December 16th ITA, Zaragoza.
Iván Vila Álvarez
Instituto de Física de Cantabria (CSIC-UC)
Outline— Quick recall of our contributions.— What can be improved after the first year.— Follow-up on the new ILD-focus R&D collaboration.
2I.Vila, [email protected] - DESY, 25th Nov. 2011.
What AIDA can do for you
— Money: all members should have received the refinancing installment (BUT CSIC institute due to BIG administrative mistake from the Spanish Treasure.
— The financial report is approaching I will help as much as a I can (video meeting starting next year).
— My personal impression, so far we are NOT profiting much from TA funds.
— This year there were not any Spanish application to this funds. We should change this.
4I.Vila, [email protected] - DESY, 25th Nov. 2011.
Our contribution
— WP3: µelectronics and interconnection (CNM, UB)— WP8.5 General Infrastructure for TB and Irradiation
facilities (IFIC)— WP9.3 Precise Pixel Detectors (IFAE, IFCA, IFIC, USC)— WP9.4 Silicon Tracking (CNM, IFCA, IFIC, UB)— WP9.5 High Granularity Calorimetry (CIEMAT)
5I. Vila, 6th Workshop on Future Accelerators, Granada
May. 16th 2011
AIDA is co-funded by the European Commission within the Framework Programme 7 Capacities Specific Programme, Grant Agreement 262025
AIDA activity @ IFICM.Vos: Leader of WP9
WP9.3 → off-beam infrastructure
WP9.4 → mechanics for u-strip setup
A. Cervera → WP8, MIND & TASD
Build on the existing Belle-II thermo-mechanical mock-up
Hiring Nacho Garcia (January/February 2012)
Create setup to evaluate the implications of power pulsing on ultra-light devices
Equip with FOS by IFCA → WP9.3 off-beam
Later: C-fiber structures → WP9.4
The contribution of the University of Barcelona in AIDA is in WP3 with the design of a 3D array based on APD photodiodes and in WP9 with the design of a multichannel Si-strip readout chip.
5 persons collaborate in the Electronics Department: A.Diéguez, R. Casanova, A. Montiel, O. Alonso, E. Vilella.
Up to Dec’11 the work has been centered mostly in WP9:
Current readout planned with APV25 by Hephy in the kick-off meeting.
Specs defined roughly by Thomas Bergauer (Hephy) during 2011:shaping time: 0.3 us - 3 us / range: 0-100 MIPS / noise baseline: ENC < 1000e- @ 2us shaping time The ASIC structure is an analog readout per channel (preamp + shaper + sparsification + analog event buffering + digitalization) + digital control.
The following activities have been done:Definition of preamp&shaper characteristics by functional simulation of the whole channelFix process: TSMC and several IBM technologies were studies but IBM is not longer available for MPW. TSMC 65nm chosen (used also for DHP in Belle II …share blocks)Modules designed: T indep current source for ADCs+preamps and schematic of the preamplifier
IFAE in AIDA
— Our work this year has been concentrated in the modules for the IBL
— The tests of these modules are also a pre-requisite for the construction of the telescope with FE-I4 readout chip
— In our test-beams we have installed up to four modules together
— Work on the software for track reconstruction is ongoing— In our case, there is a total synergy between our
activities and the activities needed to accomplish our AIDA deliverables
El CIEMAT participa en el WP9.5 de AIDA, contribuyendo al diseño y ensamblaje de la estructuras mecánicas para calorimetría. Contribuyendo a los siguientes milestones: D9.7 Infraestructura integrada para calorímetros de alta granularidad D9.8 Prestaciones y utilización de la infraestructura
Este trabajo se integra dentro del trabajo del grupo SDCHAL de CALICE.
A día de hoy se dispone ya de una estructura mecánica que pemirte integrar distintos tipos de detectores y distintos tools de transporte y movimiento.
La financiación recibida es de ~26kEuros.Además nos hemos beneficiado del presupuesto que AIDA tiene para participación en tests beams en el CERN
Participación del CIEMAT en AIDA
Trigger Logic Unit (TLU)
16/12/2011 Abraham Gallas (USC-IGFAE) 10
A Timepix Telescope arm is an AIDA deliverable
Trigger Logic Unit: currently we use 2 NIM crates and a VME TDC to perform timing tasks Controlling the Shutter – e.g.
selecting X particles per frame Providing triggers to external
systems Measuring the phase between
synchronized and unsynchronized triggers
The development of a trigger logic unit common to the EUDET and Timepix telescope under consideration. Already got in touch with David Cussans (developer of previous EUDET TLU) to build a portable based TLU replacement
TDC NIM 1
NIM 2
TELL1 RO
Trigger Logic Unit(II)
16/12/2011 Abraham Gallas (USC-IGFAE) 11
The first idea was to build a TLU only for the Timepix telescope design based on VHDL and Altera (Stratix II) development board:• Embedded system, remote
configurable, GBE data output, several on-chip TDCs…
• A solution was presented to the collaboration
But, finally, the idea to converge to a common TLU has prevailed:• Moved to Xilinx SPARTAN-6 FPGA
development board, the same as the future EUDET TLU
• Currently studying how to integrate both systems
WP 9.4 Task implementation
12I. Vila, 6th Workshop on Future Accelerators, Granada
May. 16th 2011
BaselineDeliverable
Two orthogonal layers of u-strips
HPK SiLC sensors ?
AVP25 based hybrid
Conventional mechanics
Integration with
CaloDAQ
Offline software
Provide precise
entry point to
calorimeter
Deliverable 2nd QT 2014
Advanced Deliverable
(ILD focused)
Ultra-light strip layer of thin sensors (230 um)
Integrated PA or 2D-
Poly silicon or short
strip sensors.
APV25 based hybrid
Light mechanics
with embedded Fiber Optic Sensors
Integration with
caloDAQ
Offline Software
Demonstrator of ILD silicon tracker
No deadline
14I.Vila, [email protected] - DESY, 25th Nov. 2011.
Proposal supported by
— HEPHY, Prague, (US. AIDA WP9.4 groups)— First phase of SiLC relaunching completed.— Need to define now our involvement and interest
better.— Deadline first week of May at DESY
15I.Vila, [email protected] - DESY, 25th Nov. 2011.