spacer lithography
DESCRIPTION
Spacer Lithography. EE C235 Tim Bakhishev. Spacer Process. Pattern [Dummy] Gate. Deposit Conformal SiO 2. SiO2. Dummy. Poly-Si. Si - Substrate. Isotropic Etch of SiO 2. [Remove Dummy Gate]. Feature Size. Advantages of Spacer Process. Feature Size Conformal Deposition - PowerPoint PPT PresentationTRANSCRIPT
Spacer Lithography
EE C235
Tim Bakhishev
Si - Substrate
Poly-Si
Dummy
SiO2
Spacer Process
Pattern [Dummy] Gate Deposit Conformal SiO2
Isotropic Etch of SiO2 [Remove Dummy Gate]
Feature Size
Advantages of Spacer Process
• Feature Size Conformal Deposition Good Control of Film Thickness
• Double Feature Density• Reduced Variation
Drawback: One Line WidthCan be worked around !
Y.K. Choi, et al “Spacer Patterning Technology for Nanoscale CMOS”, TED 2002
Sacrificial SiGe
FinFET Process Flow
LPCVD PSGas thin as 10nm
Remove SiGe S/D Pad Mask
Large Line Width Mask (optional)
After Gate Formation
UTBFET Process Flow
Sacrificial SiGeLPCVD PSG
as thin as 10nm
Spacer Mask Final Spacer
Gate Pad and Large L Mask
After Gate Formation
Double/Quadruple Fin Process
Standard (Double) Fin
Quadruple Fin
R. Rooyackers, et al “Doubling or quadrupling MuGFET fin …”, IEDM 2006
SiGe Pattern Spacer FormationSiGe Removal
Active Layer Pattern
Second Spacer S/D Mask Active Layer Pattern
Conclusion
With S/D Pads With Gate
Advantages:• Greatly Scaled Feature Size• Improved CD Uniformity• Possibilities Beyond Lithography
Drawbacks:• Process Complexity• Layout Concerns• Highly Selective Etch Processes Necessary