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Implementation Methodology

for Dual-Mode GPS Receiver

David Tester, Founder & CTO, Air Semiconductor

Jon Young, Chris Atkinson & Tom Ryan, Synopsys

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Overview of Presentation

- GPS 101Quick overview of GPS

- AirGlimpse into life inside a start-up

- Low Power Methodology ChallengesAspects of low power IC implementation

that we care about that may interest you

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GPS 101Receive Power is -130dBm to -160dBm … 20dB to 50dB below the Thermal Noise Floor!

Regional geo-stationary

augmentation satellites

WAASWide Area Augmentation System – USA

EGNOSEuropean Geostationary Navigation Overlay

System – Europe

Earth radius

6378 km

19100 km

20200 km

23222 km

Galileo

GPSOrbit 11 hours 58 minutes

13900 km/h

GLONASS

MoonApprox. 400000 km

35786 km

Geo-stationary

GPS6 orbital planes; 55° to equator

Galileo3 orbital planes; 56° to equator

GLONASS3 orbital planes; 65° to equator

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GPS 101Triangulation allows Receiver Position to be Calculated

r4

r1

r 3

r2

5

300m

3x108 ms

-11µs

1_.@ DEF32ABC

4GHI MNO65JKL

7PQRS WXYZ98TUV

#0+*

MOBILE

GPS 101Satellite transmits essential information required for Receiver Positioning

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Air Invents Continuous Adaptive GPS … offers both Low-Power & Position Accuracy

Competitor

Air

Low-Power

Ac

cu

rac

y

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airwave architecture enables useful geofences

A-GPS geofence

Air geofence

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View from the office window of a start-up…

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David TesterCo-Founder & CTO

Stephen GrahamCo-Founder & VP Marketing

Staff

Employee #1 (20 years experience)

Employee #2 (20 years experience)

Contract

Contract #1 (15 years experience)

Contract #2 (15 years experience)

Staff

Employee #3 (20 years experience)

Employee #1 (20 years experience)

Staff

Employee #4 (10 years experience)

Employee #5 (15 years experience)

Employee #6 (15 years experience)

Contract

Contract #3 (20 years experience)

Contract #4 (20 years experience)

Contract #5 (20 years experience)

2x Synopsys IC layout contractors

Staff

Employee #7 (20 years experience)

Employee #8 (15 years experience)

Contract

Contract #8 (20 years experience)

Contract #9 (15 years experience)

RFIC Design System Design ASIC Design Software Design

ex-CEO Andromedia (acquired Macromedia ‘99)

ex-CEO Frictionless Commerce (acquired SAP ‘06)

Andy HeatonVP Operations & Development

ex-CEO PortalPlayer (NASDAQ: PLAY)

ex-CEO S3 (NASDAQ: SIII)

Kent Godfrey

Michael Gera

David Tester

Board of Directors

Gary Johnson

Pond Ventures

Independent

Pond Ventures

ex-CEO TapRootHugh Thomas

Hugh ThomasCEO

Support Staff

1x General Admin

1x Finance ManagerCTO

CEO

The A Development Team

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Concept to Engineering Sample Silicon

Red Herring 100 Europe 2008

April „08

Series-A Termsheet

April „06

Prof Izzet Kale joins Technical Advisory Board

October „08

Demonstrate GPS technology

July „08

Recruit external CEO

May „08

Exit stealth mode

Announce 1st

product

January „08

Gary Johnson joins Board of Directors

2x NASDAQ CEO (PortalPlayer & S3)

May „07

A1225 RFIC (v1)

April „07

A1250 single die GPS receiver

January „09

A1225 RFIC (v2)

February „08

J F M A M J J A S O N D

J F M A M J J A S O N D

J F M A M J J A S O N D

J F M A M J J A S O N D

2006 2007

J F M A M J J A S O N D

J F M A M J J A S O N D

J F M A M J J A S O N D

J F M A M J J A S O N D

2008 2009

Air Inc + Ltd incorporated

May „06

Development starts!

June „06

Engage with TSMC for silicon

Sept „06

IET Start-Up of the Year 2008

November '08

Electra Start-Up of the Year 2008

November „08

RFIC + FGPA platform

May „08

Air tracks GPS satellites with RFIC

March „08

Air tracks GPS satellites with RFIC + FPGA

June „08

Air first PVT, confirms lab in Swindon

June „08

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Concept to Engineering Sample Silicon

Red Herring 100 Europe 2008

April „08

Series-A Termsheet

April „06

Prof Izzet Kale joins Technical Advisory Board

October „08

Demonstrate GPS technology

July „08

Recruit external CEO

May „08

Exit stealth mode

Announce 1st

product

January „08

Gary Johnson joins Board of Directors

2x NASDAQ CEO (PortalPlayer & S3)

May „07

A1225 RFIC (v1)

April „07

A1250 single die GPS receiver

January „09

A1225 RFIC (v2)

February „08

J F M A M J J A S O N D

J F M A M J J A S O N D

J F M A M J J A S O N D

J F M A M J J A S O N D

2006 2007

J F M A M J J A S O N D

J F M A M J J A S O N D

J F M A M J J A S O N D

J F M A M J J A S O N D

2008 2009

Air Inc + Ltd incorporated

May „06

Development starts!

June „06

Engage with TSMC for silicon

Sept „06

IET Start-Up of the Year 2008

November '08

Electra Start-Up of the Year 2008

November „08

RFIC + FGPA platform

May „08

Air tracks GPS satellites with RFIC

March „08

Air tracks GPS satellites with RFIC + FPGA

June „08

Tracking DSP

Architecture

Acquisition DSP

Architecture

Air first PVT, confirms lab in Swindon

June „08

Acquisition DSP

Implementation

Tracking DSP

ArchitectureTracking DSP

Implementation

J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D

Radio IC

Implementation

PVT &

Kalman Filter

Tracking DSP

Implementation

Radio IC

ImplementationA1250

IC design

Dual-Mode GPS

system design

Dual-Mode GPS

software design

A1250 silicon evaluation

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airwave1 system development platform

and engineering sample silicon module

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airwave1 engineering siliconQFN bonding photo

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GPS with airwave1 silicon

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Air Technical Demonstration Platform … in Japan

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Low-Power Implementation ChallengesWhat is necessary for low-power silicon implementation of a system?

- Low-Power is no exception and requires …

- Example: airwave1 and low-power GPS optimization

- Today we will not discuss GPS system implementation!

- Instead let‟s look at silicon methodology and challenges

Let‟s consider an alternative question:

“How did you create the silicon implementation of a

low power architecture? What are the challenges?”

Q1. Lazy is OK. How do you know when you‟re done?

Q2. Did you survive (or avoid) the pain a PMK can offer?

Q3. Can clock tree power consumption be predicted?

Q4. Multi-DVDD chips – Where EDA meets reality …

Q5. Is timing-optimized and power-optimized the same?

Here are five … not in any order and not an exhaustive list …

Disruptive products demand system-level optimizations

-

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Optimize Power Everywhere, Earlier is BetterEfficient algorithms provide more power saving than optimized circuits

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System

Design &

Verification

Simplified Air System + Silicon Design Flow(Does not include any analog or custom IC aspects!)

System-Level

Simulation

FPGA

Prototype

Silicon

Platform

Logical

Design &

Verification

Physical

Design &

Verification

System-Level

Architecture

Trial P&R

for blocks

Trial CTS

for blocks

Trial STA

(Post-P&R)

Final P&R

for blocks

Final CTS

for blocks

Final STA

(Post-P&R)

Trial P&R

(top level)

Trial CTS

(top-level)

Trial STA

(top level)

Final P&R

(top level)

Final CTS

(top-level)

Final STA

(top level)

DRC

(top level)

LVS

(top-level)

Trial Logic

Synthesis

Pre-P&R

Circuit Sim

Final Logic

Synthesis

Pre-P&R

Circuit Sim

Logic Level

Architecture

Logic Level

RTL Design

Logic Level

Simulation

Logic Level

Verification

Power Level

Verification

Top-Level

Floorplan

Pad Ring

Design

Firmware

Design

Firmware

Design

More

Firmware

GDSII

Power

Domains

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airwave1 engineering siliconQFN bonding diagram

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airwave1 engineering siliconDevice Floorplan (No Global Routing)

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airwave1 engineering siliconDevice Floorplan (with Global Routing)

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airwave1 engineering silicon44 independent digital power domains

2 3 45

76 89

1110 1213

1514 1617

44

34 35 36 37 38

39 40 41

2524

3332

2322

3130

2120

2928

1918

2726

1

4243

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airwave1 engineering siliconRadio Macro + Analog Support Macro

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Quick Review on Where Power is ConsumedDynamic (switching) and static (leakage) power from DVDD to DVSS

Example circuit taken from:Source: http://www.dti.unimi.it/~liberali/papers/c63.pdf

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Routing Capacitance is the Enemy Parasitic capacitance significantly alters logic switching power

How can you verify post-layout parasitic routing capacitance is acceptable?

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Stop when “Low-Power” is low enough?Products need to get to market …

Stop when you‟ve verified it‟s good enough

“I‟d like the lowest possible power consumption, please”

“I‟d also like to get that product to market on time, please”

Do you have a power budget? When should verification STOP ?

Track and predict power performance at all levels of abstraction:

- Architecture / Algorithm / System Partitioning

- Pre-Synthesis RTL and Post-Synthesis Gates

- Pre-Layout and Post-Layout

“… but verification is never really complete…”

True… what is the milestone for sufficient

confidence that power meets budget?

Can you spot the conflict between the following two statements?

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Less Complexity, Less Transitions = Low Power Reduce depth of logic and switching activity to minimise power

How to verify switching

activity level on budget?

How to verify the original

complexity assumptions?

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“Custom” Cells rather than “Standard” Cells?„Optimized for Power‟ and „Optimized for Timing‟ might not be the same

Example

- Custom flip-flop used in airwave1 datapath

- Relaxed timing enabled >40% power improvement!

- Also provided die area and P&R enhancements

- Knowledge of “use” offer options for power optimized gates

- Power optimized and timing optimized are not always the same

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What‟s Your Methodology to Build Clock Trees?Not all clock tree‟s are low power … can you trust the tools?

- Power depends on conflicting constraints: skew, rise time, load, etc

- CTS tools build functional but over-designed, high-power clock trees

- Can‟t verify power until P&R started ... but is that too late for market?

- Clock tree can pass functional verification but fail power verification!

Example:

airwave1 contains

400+ clock domains

More a clock forest

than a clock tree ...

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Power Management Kit - Handle Carefully!… rather like a chainsaw with all the safety features removed …

- Standard cell library assumes single DVDD supply voltage

- Power management library enables multiple voltage domains

- Voltage domain control cells – DVDD and DVSS switch

- P&R “optimisation” can pull cells from PMK library by mistake!

- Can simulation identify these problems?…

- Signal isolation cells (for crossing voltage domains)

- Must verify P&R didn‟t “optimise” these!

- PMK also adds more back-end DRC and LVS

verification issues simulation can‟t solve…

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Multi-DVDD Silicon: Where EDA meets Reality!Circuit level functionality that needs to be verified at RTL level

- How, and when, are cells instanced in the design?

- Manually by logic designer or layout team?

- Automatically by EDA tool? Do you trust it?

- Yet another task to verify before tape-out !!!

- Control signal active sense depends on cell used:

- Active low for PMOS but active high for NMOS

- Are control signal wired correctly?

- How many cells for each domain?

- “Power Aware” design flows try to plug the hole!

… but don‟t address all the issues !!!Example:

airwave1: 44x digital, 8x analog voltage domains

- DVDD functionality in “HEAD” and “FOOT” cells

… but DVDD not represented in non-UPF flow logic simulation!

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DVDD and DVSS power routingmetal5 and “thick” metal6 reserved for power routing

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airwave1 engineering silicon44 independent digital power domains

2 3 45

76 89

1110 1213

1514 1617

44

34 35 36 37 38

39 40 41

2524

3332

2322

3130

2120

2928

1918

2726

1

4243

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Power Domains - Some Issues to WatchDon‟t forget substrate, N-well and control signal polarity

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Power Domains - Some Issues to WatchDon‟t forget substrate, N-well and control signal polarity

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Automatic vs Manual Cell PlacementP&R placement algorithm is not always optimum

Manual Placement

Automatic Placement

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Impact of UTM metal on P&R efficiencyMetal pitch + spacing rules directly impact P&R result

“thin”

metal5

“thick”

metal6

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Post-P&R Optimization? Roll the Dice Again!Development on-schedule and on-budget?

“Here‟s the final netlist,

it meets the power spec‟s

and just needs to go through P&R”

- Pre-Layout gate level power estimates are estimates

- Routing capacitance impacts both timing and power

- P&R optimization resizes gates to close timing

… almost certainly ignoring circuit power

… so power estimates on pre-P&R netlist

are exactly that, estimates

Verification Issue:

How to verify post-layout power still hits

the target specification …

… and hit your schedule

P&R “optimization” can solve that…

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“Blind Faith and Ignorance”

Low-Power can be broken anywhere:

- Architecture

- Hardware (RTL) or Software

- Logic Synthesis

- P&R and CTS

- Cell library and macros choices

- Process technology

Each step needs differing levels of implementation and verification

activity, but verification of power needs more than just logic

simulation and must include power budgets and circuit simulation

CPU power alone can‟t solve the problems, brain power is needed!

or “Informed Decision”?

Don‟t forget to be paranoid about power, if you care about power

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