Why ledge on the CLK for SLI interface?

Compliance Engineering

June 4th , 2008

12/7/2013 1

What is SLI?

12/7/2013 2

Problem Statement

12/7/2013 3

Large clock dispersion causing failure of SLI

Page 4

DDR1-266/333 DQS exampleDQS is single-ended 90-deg phase shifted w.r.to DQ

– DQ/DQS Status--• DQ/DQS crosstalk problem: Multiple curves of DQS coz

of the DQ coupling & PDN around it (even, odd, or stay-H/L)– Sims and Lab data confirms problem

– Fix identified—more spacing for DQS and maybe guardbands—impact to brd routing constraints

DDR266 DDR333Passing

Below Threshold Marginal

12/7/2013

12/7/2013 5Page 5

WR Eye Diagram – DQ58

Vref=1.15v

VIH

VIL

Robust data window:

0.91 + 0.94 = 1.85ns

Jedec

Intel

DQ58: odd DQ58: odd DQ58: even DQ58: even

tDS+tDH=1.23+1.35=2.58ns tDS+tDH=0.91+1.51=2.42nstDS+tDH=1.50+1.13=2.63nstDS+tDH=1.60+0.94=2.54ns

Three sets of curves for DQS showing such

even/odd/stay-H/L cases on DQS signal

V:200mv H:500ps

BGRVP: FabB201#251, HiZo; MCH: A0-SS, 2.30v, 90’c; BIOS:14; DDR333

DIMM0/1= Samsung x8DS / Hyunix x8DS (2.30v, RT); S/W: MARS

DDR1-400 Example showing same three-sets of curves with even/odd/stay-H/L activity on DQ

bus

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Rs-DIMM=22-ohms

Ls-DIMM=8nH

SLI interface similarity with DDR1 interface

12/7/2013 7

Clock signal SLI interface behaves similarly to DDR1 DQS that is also single-ended and also phase-shifted w.r.to DQ signals surrounding itBoth x-talk and PDN spreads the waveform as seen in the scope capture: it is a claim

What about the layout?

12/7/2013 8

Looking @ the clock signal: it is also surrounded by DQ signals, depends on the activity on DQ: even, vs. odd, vs. stay-H/L, we see such spread of Clock signal waveform: it is both X-talk and PDN impact.

Claim is: The spread happening on the Clock signal is caused by the even/odd/stay-H/L

activity on DQ signals: How to prove it?

• Sims: Extract using ADS the clock signal along with the DQ signals surrounding it, then simulate the clock phase-shifted and prove the spread of the clock waveforms as in the lab capture

• Lab: using MODS, control the data pattern and active-bits around the clock to see the impact of even/odd/stay-H/L activity on the clock signal

12/7/2013 9

If the Claim is true: what is the proposed soln space?

• Use Guard-band traces around the clock to support reduced x-talk as well as improved PD isolation for the clock

• Require GND-stitching every 1” of the guard-band trace.

12/7/2013 10

Post-Layout Sims for testing the claim that x-talk+PDN are causing

such spread in waveform of CLK for SLI interface

12/7/2013 11

SLI sims on P729-B02

Simulated nets:)P 729-B02

• odd-ports @ connector side, even-ports @ chip side

– MIOB_CLKOUT: P1-P2 – D_13: P3-P4– D_14: P5-P6– D_3: P7-P8– D_4: P9-P10– D_5: P11-P12– D_6: P13-P14– D_7: P15-P16– D_8: P17-P18

Insertion Loss

-3dB @ 970MHz

NEXT w.r.to CLKOUT

-15dB @ 1GHz of NEXT w.r.to CLKOUT

FEXT w.r.to CLKOUT

-17dB for FEXT @ 1GHz

Why NEXT is max for P2-to-P4?

P2

P4

Two vias coupling maximize the x-talk between P2-to-P4We should move the GND via in between signal vias

Why NEXT is max for P2-to-P4?, Cntd.

Two vias coupling maximize the x-talk between P2-to-P4We should move the GND via in between signal vias

Why NEXT is max for P2-to-P16?

Wrong-clock pad causes extra coupling with P16

Why NEXT is max for P2-to-P16?

Wrong-clock pad causes extra coupling with P16

Even on P977 Wrong Clock-pad!!!

Wrong-clock pad causes extra coupling with P16

Summary and Proposed Solution

Moment-Method CorrelationTransistor model

> 250mV improvement

lLab Capture

Guard-band

Adding Guard-band to clock on Flex causes successful operation of the SLI interface