signal integrity analysis using statistical methods · signal integrity analysis using statistical...

Signal Integrity Analysis Using Statistical Methods

J u l y 2 0 1 2

Signal Integrity Analysis Using Statistical Methods | July 2012

© 2011, HCL Technologies, Ltd. Reproduction prohibited. This document is protected under copyright by the author. All rights reserved.

TABLE OF CONTENTS

Abstract ............................................................................................. 3

Abbreviations .................................................................................... 4

Introduction........................................................................................ 5

Why DOE? ........................................................................................ 6

Signal Integrity Flow .......................................................................... 6

Case Study – SATA Interface ........................................................... 7

Design of Experiments (DOE) ........................................................... 8

Response Surface Modeling (RSM) ................................................. 9

Prediction Profiler ............................................................................ 10

Conclusion....................................................................................... 12

References ...................................................................................... 13

Author Info ....................................................................................... 13



3

Abstract

The current electronics industry drive for miniaturization of electronic products will eventually call for smaller IC package design, high speed interfaces and complex, dense PCB designs. The recent advancements in PCB designs have facilitated the manufacturing of high-density, multi-layer PCBs, where interface speeds can vary from 1.5Gbps to 12Gbps and more. The need for comprehensive analysis of these interfaces during the early stages of design becomes very critical in order to avoid signal integrity and EMI/EMC-related issues during system testing and certification.

This paper presents a method to leverage the advantages

of statistical methods for signal integrity analysis. This paper will describe how we can simplify signal integrity analysis by analytically reducing the number of simulation iterations and predicting the worst and best case conditions and results for validating the high speed interfaces using statistical tools such as JMP

® and

Minitab

®.



4

Abbreviations

Sl.

No.

Acronyms Full form

1 dB Decibel

2 EMI/EMC Electromagnetic Interference /Electromagnetic Compatibility

3 Gbps Gigabits per second

4 IC Integrated Circuit

5 IO Input Output

6 PCB Printed Circuit Board

7 RX Receiver

8 SATA Serial Advanced Technology Attachment

9 SI Signal Integrity

10 TX Transmitter



5

Introduction

Statistical tools like JMP®

and Minitab® provide a

comprehensive toolset to perform design of experiments and statistical quality control in a single package. When performing signal integrity analysis of any multi-GHz interface, we need to analyze the effect of the IC package, PCB trace impedance variations during manufacturing tolerances and other effects including buffer corner, termination tolerances, etc., on signal quality and timing parameters. Taking all these factors into consideration poses a huge challenge in terms of complexity as well as time while performing SI analysis. Also, the timeframe available for SI analysis during both pre- and post- layout is limited due to crunch product schedules and market pressures. Failing to perform an in-depth analysis during the design phase leads to poor design yields, which increase cost, field failures and customer returns.



6

Why DOE?

Design of Experiments (DOE) allows the simultaneous investigation of the effects of various factors/variables, thereby facilitating design optimization. DOE techniques provide powerful and efficient methods to identify the vital factors in the most efficient manner, and then direct the process to its best setting to meet the ever-increasing demand for improved quality and increased productivity. Some of the advantages of using DOE are stated below.

Systematically identifying relationships between cause and effect of a number of independent and dependent variables of interest

Providing an understanding of interactions among contributing variables

Comparing alternative factors to achieve best or comparable output

Identifying the significant and trivial factors affecting an output

Determining the levels at which to set the controllable factors in order to optimize reliability

Improving the robustness of the design or process to variations. DOE can be leveraged to a greater extent to reduce design

costs by speeding up the design process, reducing late engineering design changes, reducing rework and scrap. DOE allows us to design and conduct experiments with a minimal number of iterations that will result in the creation of an accurate linear model based on the results provided to the statistical tools.

Once an accurate linear model with a good fit is created,

modeling techniques such as Response Surface Modeling (RSM) can be used to predict the behavior of our system in response to arbitrary combinations of factors. The RSM is a commonly used technique in engineering and R&D experiment design. This modeling technique can be used for predicting the worst- and best-case output values for any given combination of input variables, using the prediction profiler available in the statistical tool.

Signal Integrity Flow

The traditional signal integrity process needs to be modified to apply statistical methods and obtain results effectively. This modified flow has two additional stages – pre- and post-processing – in addition to the HSPICE

® simulations stage.



7

Figure 1 : Design of Experiments - SI Flow

The flowchart above shows the various steps that need to

be performed during signal integrity analysis using DOE. In the pre-processing stage, we need to identify various variables and their range which will influence the final results. Then we create a DOE table using a statistical tool which provides us with the minimal number (n) of iterations needed to perform the simulations using HSPICE

®. Then, like the conventional way, we create ‘n’ number of

HSPICE® simulation decks and perform simulations, except here

the number of iterations is much less when compared to the exhaustive simulations performed previously. In the post- processing stage, we extract these results and provide them to the statistical tool to create a statistical model in order to predict the worst and best case conditions and results. The predicted result is compared to the acceptable limits as specified by the interface specifications with sufficient margins, then the final report is prepared.

Let us consider a SATA Gen 2 topology as shown in Figure

2 as a case study to explain the application of statistical methods in signal integrity analysis. The methods explained here can be applied to any high-speed interface for an effective and detailed SI analysis.

Case Study – SATA Interface

The topology below shows a SATA port routed on a four-layer PCB using both top and bottom signal layers, and connected to a standard SATA connector. The receiver is assumed to be a standard 50 Ohms termination.

Figure 2 : SATA TX and RX Topology



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For this topology, several variables need to be considered,

including a TX Buffer corner, package variations, transmission line impedance variations due to manufacturing tolerance and termination variations to validate signal quality parameters such as Tmargin and Vmargin near the receiver. The table below shows the possible variables with their respective sweep ranges. Several other variables including package length, AC coupling capacitor tolerance, TL1,TL2, TL4 and TL5 length, etc., are neglected to simplify the explanation of the case study in this paper.

S. No. Variables Min Typ Max Remarks

1 IBIS_fts slow Typ fast TX buffer corners

2 TL_type low Typ high Transmission line variations

3 Pkg_type min Typ max Package variations

4 TL3_len [inches] 2 6 10 TL3 transmission line length

5 Tx_vdd [Volt] 0.9 1.0 1.1 IO power supply

6 R_buff[Ohms] 80 90 100 Driver buffer setting

7 de_emp[dB] 3.5 4.75 6 Driver de-emphasis setting

8 rterm [ohms] 45 50 55 Receiver differential termination

Table 1 : Variable List with Range

Design of Experiments (DOE)

To perform an exhaustive simulation with all the above variables, with their sweep ranges included, using simulation tools like HSPICE,

® would require running a minimum of 6,561 iterations

to understand the individual and combined effects of all variables on final signal quality. This would be a huge effort, both in terms of resources needed as well as the time required to simulate and interpret the results. The DOE comes to our rescue here. Using a statistical tool, we can obtain the minimal iterations required to create a statistical model which can be used to predict the response for all the variable’s individual and combined effects for all iterations. This way, we can save time and resources without compromising on the quality of analysis.

From our observations, we could infer that by using DOE,

the required number of iterations has come down drastically from 6,561 to just 192, for which we can perform the simulations and provide the statistical tool with measured Tmargin and Vmargin values. The table below shows a sample of measured response values provided to the statistical tool

for some of the 192 iterations

for which simulations were performed.



9

Figure 3 : Simulation Results – DOE Table

Response Surface Modeling (RSM)

Once the response values (Tmargin and Vmargin) are provided against the DOE table, the statistical tool can be used to create an RSM model with which the prediction can be done. But the model created by the statistical tool needs to be validated before use because the data points provided to the tool may not be sufficient to predict properly with minimal variance. The model verification can be done by checking the analysis of variance (ANOVA) table, as shown below, for each of the required responses/output separately.



10

Figure 4 : ANOVA Table - Vmargin

Several factors of the ANOVA table need to be validated,

including the R2, R

2adj, P value and F ratio value before using the

model because the standard deviation of a poorly-fitted model will be large and won’t correlate with the simulation results. In the case of a poorly-fitted model, the data point count can be increased from 192 to 256 to check whether the statistical tool can fit the model correctly.

Prediction Profiler

The statistical tools have a built-in Prediction Profiler which can be used to predict worst and best case response values based on the RSM model previously created. The worst and best case Vmargins predicted for the given SATA topology using Prediction Profiler are shown below.

Figure 5 : Worst Case Condition – Vmargin



11

Figure 6 : Best Case Condition – Vmargin

It is observed from Figures 5 and 6 that the worst and best

case Vmargin predicted by the statistical tool is 86.5mV and 268.6mV, respectively, with a standard deviation (obtained separately) of ±3.7mV. The same SATA topology is simulated for the entire 6,561 iterations, and the worst and best case Vmargin is observed to be 83.6mV and 268.9mV, respectively, which is very much within the predicted value variance. Similarly, worst and best case Tmargin can also be predicted and compared with the actual simulation result.

The Prediction Profiler can also be used to understand the

influence of any particular factor on the end response. For example, if we refer to Figures 5 and 6, the effect of tx_vdd on Vmargin is more when compared to pkg_type because the slope of tx_vdd vs. Vmargin is steeper than the slope of pkg_type vs. Vmargin. Also, Prediction Profiler can be used to interpolate or extrapolate any factor to check the corresponding response value. For example, we can check what the value of Vmargin will be when we increase the len_tl3 from 10 inches to 12 inches or more. This way we can determine the maximum length the interface can be routed without violating the specification requirement of Vmargin.



12

Conclusion

The Prediction Profiler results show how accurately the statistical tools can predict the results with minimal simulation runs. Using this method, we can save valuable time, effort and resources, but still achieve comprehensive signal integrity analysis. The application of these statistical methods becomes very crucial when the number for variables and their range increases, thereby increasing the number of simulation iterations needed. Suppose the number of variables increases for 8 to 12, with each variable having 3 levels, then the total number of simulations needed to be performed will increase from 6,561 to ~0.5 million -- definitely very difficult to perform and analyze the results.

The application of statistical methods in the field of signal

integrity is not new, and has been in use in various simulation tools

such as FastEye® from Mentor Graphics® and StatEye® from

Synopsis® for performing statistical eye diagram generation. In this

paper, we have discussed an entirely different application of

statistical methods, with the use of statistical tools in performing pre-

and post-simulation rather than for eye diagram generation. By

effectively using these principles, we can simplify signal integrity

analysis without compromising on effective and in-depth analysis,

and with less time and effort.

Further research can be performed in improving the

modeling efficiency and result correlation by using other statistical

modeling techniques like Stepwise regression and Taguchi

methods.



13

References

1. Advanced Signal Integrity for High-Speed Digital Design, by

Stephen H. Hall and Howard L. Heck, John Wiley & Sons,

Inc.

2. Design of Experiments Guide, JMP Version 9.0.2.

Author Info

Deepak Anand G is a Project Lead in the System Design Services division of HCL Technologies, Ltd. He has seven years of experience in high-speed PCB design. He is responsible for board design and signal integrity analysis for various high-speed products.

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