Shifters and Adders

Somayyeh KoohiDepartment of Computer Engineering

Sharif University of TechnologyAdapted with modifications from lecture notes prepared by author

Modern VLSI Design: Chap6 2 of 22Sharif University of Technology

Combinational shifters

n Useful for arithmetic operations, bit field extraction, etcvMultiple shifts per clock cyclevA multiple-shift shifter requires additional

connectivityn Latch-based shift register can shift only one bit

per clock cycle

Modern VLSI Design: Chap6 3 of 22Sharif University of Technology

Barrel shifter

n Can perform n-bit shifts in a single cycle

n Efficient layoutn Requires transmission gates

and long wiresn Accepts 2n data inputs and n

control signals, producing ndata outputs

data

1da

ta 2

n bits

n bits

outp

ut

n bits

Modern VLSI Design: Chap6 4 of 22Sharif University of Technology

Barrel shifter operation

n Selects arbitrary contiguous n bits out of 2n input butsn Examples:

v Right shift: data into top, 0 into bottomv Left shift: 0 into top, data into bottomv Rotate: data into top and bottom

Modern VLSI Design: Chap6 5 of 22Sharif University of Technology

Barrel shifter layout and cell

n Two-dimensional array of 2nvertical X n horizontal cells

n Input data travels diagonally upward

n Output wires travel horizontally

n Control signals run verticallyv Exactly one control signal is

set to 1, turning on all transmission gates in that column

Modern VLSI Design: Chap6 6 of 22Sharif University of Technology

Barrel shifter in action

n Large number of cellsv but each one is small

n Delay is largev Due to long wires

Ø Large delayv Each signal traverse only one

transmission gate from input to outputØ Small delay due to

transmission gates

Modern VLSI Design: Chap6 7 of 22Sharif University of Technology

Adders

n Adder delay is dominated by carry chainn Carry chain analysis must consider transistor

and wiring delayn Modern VLSI favors adder designs which have

compact carry chains

Modern VLSI Design: Chap6 8 of 22Sharif University of Technology

Full adder

n Computes one-bit sum, carry:v si = ai XOR bi XOR civ ci+1 = aibi + aici + bici

n Various adder architectures differ from each other in carry generation circuitv Ripple carry adderv Carry-lookahead adderv Carry-select adderv Carry skip addervManchester carry chainv Serial adder

Modern VLSI Design: Chap6 9 of 22Sharif University of Technology

Ripple carry adder

n n-bit adder built from cascading 1-bit full addersvDelay of ripple-carry adder goes through all carry

bitsn Efficient in FPGAs v Implement carry chain

Ø E.g. : Xilinx XC4000

n The worst in ASICs

Modern VLSI Design: Chap6 10 of 22Sharif University of Technology

Carry-lookahead adder

n First compute carry propagate, generate:vPi = ai + bi

vGi = ai bi

n Compute sum and carry from P and G:vsi = ci XOR Pi XOR Gi

vci+1 = Gi + Pici

Modern VLSI Design: Chap6 11 of 22Sharif University of Technology

Carry-lookahead expansion

n Can recursively expand carry formula:v ci+1 = Gi + Pi(Gi-1 + Pi-1ci-1)v ci+1 = Gi + PiGi-1 + PiPi-1 (Gi-2 + Pi-1ci-2)

n Recursively expanded formula does not depend on intermerdiate carriesv Can be computed from inputs directly

n Allows carry for each bit to be computed independently

Modern VLSI Design: Chap6 12 of 22Sharif University of Technology

Depth-4 carry-lookahead

Modern VLSI Design: Chap6 13 of 22Sharif University of Technology

Analysis

n Increased complexity and area, reduced delay for small adder (e.g. 4-bit adder)

n Deepest carry expansion requires gates with large faninv So, slowv Limit number of inputs to 4 (depth-4 carry-lookahead) for each carry

lookahead adderØ So, hierarchical structure

n Carry-lookahead unit requires complex wiring between adders and lookahead unitv Values must be routed back from lookahead unit to adder

n Layout is even more complex with multiple levels of lookaheadv Use ripple carry or carry-lookahead structure between different levels

Modern VLSI Design: Chap6 14 of 22Sharif University of Technology

Carry-skip adder

n Looks for cases in which carry-out of a set of bits is identical to carry in

n Typically organized into m-bit stages

n If a i ≠bi for every bit in stagev Bypass gate sends stage’s

carry input directly to carry output

v O.W : generate carryn Figure : two-bit carry-skip

structure

Modern VLSI Design: Chap6 15 of 22Sharif University of Technology

Carry-select adder

n Computes two results in parallelv Each for different carry input assumptions

n Uses actual carry-in to select correct resultn Reduces delay to multiplexern Carry-select adder can be divided to m-bit sub addersv Sub adder implemented as carry select adderv Carry ripple between sub adderv 32-bit adder : 8 mux-stage delay

Modern VLSI Design: Chap6 16 of 22Sharif University of Technology

Carry-select structure

Modern VLSI Design: Chap6 17 of 22Sharif University of Technology

Manchester carry chainn Precharged carry chain which uses P and G signals

v Propagate signal connects adjacent carry bitsv Generate signal discharges carry bit

n Storage node holds the complement of the carryn Worst-case discharge path goes through entire carry chainn Widest transistor should be at the least-significant bit stage

v They see the largest load

Modern VLSI Design: Chap6 18 of 22Sharif University of Technology

Serial adder

n May be used in signal-processing arithmetic v Fast computation is important

n Requires many clock cycle to add two n-bit numbersv But with very short cycle time

n Simple and smalln Data format (LSB first):

0 1 1 0

LSB

Modern VLSI Design: Chap6 19 of 22Sharif University of Technology

Serial adder structure

LSB control signal clears the carry shift register:

Modern VLSI Design: Chap6 20 of 22Sharif University of Technology

ALUs

n ALU computes a variety of (bit-wise) logical and arithmetic functions based on opcodev Opcode together with carry-in determine the function

n May offer complete set of functions of two variables or a subset

n ALU built around adder, since carry chain determines delay

Modern VLSI Design: Chap6 21 of 22Sharif University of Technology

Function block circuit and ALU

n Takes 2 data inputs and their complement along with 4 control signals v Can compute all 16

possible functions of the 2 data inputs

n Function block may be used to compute required intermediate signals for a full-function ALU

n Requires little area

Modern VLSI Design: Chap6 22 of 22Sharif University of Technology

ALU structure and design

n 3 function blocksv Require a total of 12 opcode

n P and G compute intermediate values from inputsv May not correspond to carry

lookahead P and G for non-addition functions

n Add unit is adder of choicen Output unit computes from

sum, propagate signal