Sequential Design

10תרגול

Y86 Processor Simulator

The Computer Simulation of a Central Processing Unit Based on the Intel IA32, or X86, Instruction Set.

תמר שרוט, נועם חזון 2

Y86 Instruction SetByte 0 1 2 3 4 5

pushl rA A 0 rA 8

jXX Dest 7 fn Dest

popl rA B 0 rA 8

call Dest 8 0 Dest

rrmovl rA, rB 2 0 rA rB

irmovl V, rB 3 0 8 rB V

rmmovl rA, D(rB) 4 0 rA rB D

mrmovl D(rB), rA 5 0 rA rB D

OPl rA, rB 6 fn rA rB

ret 9 0

nop 0 0

halt 1 0

addl 6 0

subl 6 1

andl 6 2

xorl 6 3

jmp 7 0

jle 7 1

jl 7 2

je 7 3

jne 7 4

jge 7 5

jg 7 6

4

Tracing the execution of SEQ

Six Stages Fetch - Reads the command bytes from memory using the PC. Extracts icode

and ifun and if needed fills rA, rB and valC. Also calculates valP = length(instruction) + PC.

Decode - Reads two values from registers and inserts them into valA and valB.

Execute - According to the ifun either the ALU executes the command or calculates the new stack pointer. The result will be put into valE. For a jump instruction checks condition codes and branch conditions.

Memory - Reads or writes from memory. The value will be put into ValM.

Write Back - Writes up to two results into the registers.

PC Update - Now updates the PC for the next command.

5

6

subl, line 3

7

irmovl, line 4

pushl, line 6

popl, line 7

SEQ Hardware Key

Blue boxes:

predesigned hardware blocks E.g., memories, ALU

Gray boxes:

control logic Describe in HCL

White ovals: labels for signals

Thick lines:

32-bit word values Thin lines:

4-8 bit values Dotted lines:

1-bit values

Instructionmemory

Instructionmemory

PCincrement

PCincrement

CCCC ALUALU

Datamemory

Datamemory

NewPC

rB

dstE dstM

ALUA

ALUB

Mem.control

Addr

srcA srcB

read

write

ALUfun.

Fetch

Decode

Execute

Memory

Write back

data out

Registerfile

Registerfile

A BM

E

Registerfile

Registerfile

A BM

E

Bch

dstE dstM srcA srcB

icode ifun rA

PC

valC valP

valBvalA

Data

valE

valM

PC

newPC

11

Is this equivalent to our tables? Explicit control over sequencing,

PC CC Date memory Register file

The key idea: The processor never needs to read back the state updated by an instruction in order to complete the processing of this instruction!

Examples: Pushl does not use the updated %esp No operation set and read the Condition Codes

12

Handling ambiguities What is the result of pushl %esp?

What is the result of popl %esp?

Which port will get priority in popl?