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  • i

    Semiconductor TCAD Fabrication Development for BCD Technology

    A Major Qualifying Project Report:

    submitted to the Faculty

    of the

    WORCESTER POLYTECHNIC INSTITUTE

    in partial fulfillment of the requirements for the

    Degree of Bachelor of Science

    by

    ____________________________

    Matthew Hazel

    _____________________________

    Marc Cyr

    Date: March 13, 2006

    Submitted to:

    _____________________________

    Professor John McNeill, Co-Advisor

  • ii

    Abstract

    As semiconductor devices evolve, it is important to understand the fabrication

    processes and issues that arise with each new generation of transistor technology.

    Through research, and the use of the SILVACO simulation tools, we successfully

    simulated and tested a series of Bipolar, CMOS, and DMOS devices, and optimized them

    in order to minimize issues such as leakage current and punch through. Additionally,

    comparisons between actual, and theoretical device characteristics were made.

  • iii

    Acknowledgements We take this opportunity to thank the people that have supported us over the

    course of our project. Without their help and guidance, we would not have been able to

    complete this effort in a timely manner.

    Professor Shela Aboud (Project Advisor): Whose knowledge of BCD

    technologies as well as the Silvaco simulation tools was a significant help

    during the completion of our project.

    Professor John McNeill (Project Advisor): For graciously taking on the role of

    our project advisor for the third term, and completion of our MQP.

    Jim McClay: Whose research paper on device fabrication proved to be the

    foundation of this project.

  • iv

    Table of Contents Abstract...........................................................................................................................ii

    Acknowledgements ........................................................................................................iii

    Table of Contents ........................................................................................................... iv

    List of Figures..............................................................................................................viii

    List of Tables ..................................................................................................................x

    Executive Summary .......................................................................................................xi

    1. Introduction..............................................................................................................1

    2. Background ..............................................................................................................3

    2.1. Evolution of the Transistor in BCD Technology ................................................3

    2.2. The Fabrication Process.....................................................................................4

    2.2.1. Lithography ................................................................................................5

    2.2.2. Oxidation of Silicon....................................................................................5

    2.2.3. Diffusion and Ion Implantation ...................................................................6

    2.2.4. Ion Implantation..........................................................................................6

    2.2.5. Film Deposition ..........................................................................................7

    2.3. BCD Masking Process .......................................................................................7

    2.3.1. Locos Isolation ...........................................................................................8

    3. Silvaco Software Suite............................................................................................ 10

    3.1. How to Code with Athena................................................................................ 10

    3.1.1. Overview .................................................................................................. 10

    3.1.2. Research ................................................................................................... 12

    3.1.3. Line-By-Line Analysis.............................................................................. 13

    3.2 How to Code with Atlas.................................................................................... 13

    3.2.1. Overview .................................................................................................. 13

    3.2.2. Research ................................................................................................... 15

    3.3. Deviance from Ideal Simulation Examples....................................................... 16

    3.3.1. Mesh Lines ............................................................................................... 16

    3.3.2. Oxidation.................................................................................................. 16

    3.3.3. Masking.................................................................................................... 18

  • v

    3.3.4. LOCOS Isolation process.......................................................................... 20

    3.3.5. Contacts.................................................................................................... 27

    3.4. Conclusion....................................................................................................... 29

    4. CMOS Transistor ................................................................................................... 30

    4.1. Problem Statement........................................................................................... 30

    4.2. Theoretical Device Characteristics................................................................... 31

    4.2.1. Oxide Thickness ....................................................................................... 31

    4.2.2. Threshold Voltage..................................................................................... 32

    4.2.3. I-V Characteristics .................................................................................... 33

    4.3. Walkthrough of CMOS Fabrication ................................................................. 34

    4.3.1. PMOS Fabrication Summary .................................................................... 36

    4.3.2. NMOS Device Process.............................................................................. 37

    4.4. Final Device Characteristics and Comparison .................................................. 43

    4.4.1. Gate Oxide................................................................................................ 43

    4.4.2. Threshold Voltage..................................................................................... 44

    4.4.3. I-V Relationship........................................................................................ 45

    4.5. Conclusion....................................................................................................... 46

    5. Bipolar Junction Transistor..................................................................................... 48

    5.1. Problem Statement........................................................................................... 48

    5.2. Theoretical Device Characteristics................................................................... 49

    5.2.1. Gummel Plot............................................................................................. 49

    5.2.2. I-V Characteristics .................................................................................... 50

    5.3. Walkthrough of BJT Fabrication...................................................................... 51

    5.3.1. BJT Device Process .................................................................................. 53

    5.4. Final Device Characteristics and Comparison .................................................. 58

    5.4.1. Gummel Plot............................................................................................. 59

    5.4.2. I-V Characteristics .................................................................................... 61

    5.5. Conclusion....................................................................................................... 62

    6. LDMOS Transistor................................................................................................. 62

    6.1. Problem Statement........................................................................................... 62

    6.2. Theoretical Device Characteristics................................................................... 63

  • vi

    6.2.1. Threshold Voltage..................................................................................... 64

    6.2.2. Leakage Current........................................................................................ 64

    6.2.3. Off-State Leakage Current ........................................................................ 65

    6.2.4. Breakdown Voltage .................................................................................. 66

    6.2.5. On-Resistance........................................................................................... 67

    6.2.6. On-State Drain Current .................................................

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