Semi-Detailed Bus Routing with Variation Reduction

Fan Mo, SynplicityRobert Brayton, UC Berkeley

Presented by:Philip Chong, Cadence

Outline

• Why bus routing.

• The “orientation determination” problem.

• Bus routing flow overview.

• The algorithm.

• Experimental results.

• Future work.

Why Bus Routing• Bit-wise wire length/delay matching.

• Save runtime.– Routing a representative bit (what we call

virtual net).

• Usually better routability– Less twisting and entangling.

• Better variation immunity.– All bits receive similar variations.

Existing Bus Routers• Route a representative bit rather than all bits.

– Persky and Tran, DAC 84

• Fanout-1 bus

– Rafiq et al, ISPD 02

• 0-bend, 1-bend, 2-bend bus topologies.

– Xiang et al, DAC 03

– Law and Young, ISPD 05

– Chen and Chang, ISPD 05

The Turning Points!

normal routingblockage

bused pin

turning points

• The arrangement of the turning points is the key to successful bus routing.

The Node Orientation

• The virtual net– An abstract view of the

bus.– Bused pins become pin

nodes.– All other points become

non-pin nodes.

• The arrangement of the bits at a node is called the “orientation”.

– The direction from LSB towards MSB.

non-pin node

pin node

Orientation and Orientation Set• A pin node has a fixed orientation.

– Always 0o or 90o (N, W, S or E)

• A non-pin node may have several possible orientations.

– Always 45o (NE, NW, SE, SW)

• All possible orientations of a node form an orientation set.

N E S W

pin nodesOr.Set

(single orientation)

non-pin nodesOr.Set

NW NE SW SE NH EV SH WV TP TN AL

Orientation and Orientation Set• Adjacent nodes must have compatible orientation

sets.

N

S

SW

NW

SH

AL

W

WV

N

S

NW

N

??

empty orientation set

Orientation and Orientation Set

invalid

TP TP

TN TN

TP

TN

TP TP

<W

invalid invalid valid

• Special case: “Interlocking”.– When two non-pin nodes are connected by a short

segment, the connection must be a Z-shape.– The orientation sets of the two nodes are interlocked.

What is short? Distance less than the all-bit routing width of the bus.

Bus Routing Flow

done

succeed?

orientation determinationdeviation minimization

virtual netrouting

orientation setgeneration

fixes

virtual net tobus translation

fail

enoughiterations?

preparation

yes

yes

no

no

succeed?

yes

no

start

done

check only bus routing & minimization

The Algorithm

done

succeed?

orientation determinationdeviation minimization

virtual netrouting

orientation setgeneration

fixes

virtual net tobus translation

fail

enoughiterations?

preparation

yes

yes

no

no

succeed?

yes

no

start

done

check only bus routing & minimization

The Algorithm• Step 1: Preparation

P0

normal routingblockage

bussed pin

LSB

MSB

P0

W

W

W

addedblockage

pair

expansion ofnormal blockage

W/2

The Algorithm• Step 2: Virtual net routing

P0

The Algorithm• Step 3: Orientation set generation

E

NN

N

NW

SP0

interlocking

NH

ALNH

AL

NH

ALEV

WV

The Algorithm• Step 4: Fix

– Add extra blockage to avoid using certain segments.

– Re-route (Step 2).– Redo orientation set generation (Step

3).– Try a few times. If still fails, abort.

The Algorithm• Step 5: Orientation determination and

deviation reduction– A forward propagation from the driver pin

node can determine the orientation for each node (from its orientation set).

– Flexibility may exist, if for certain nodes, more than one orientation are valid choices.

– Such flexibility allows minimization of bit-wise driver-load wire length/delay deviation.

Bit-wise wire length deviation = the (absolute) difference between MSB driver-load length and LSB driver-load length.

The Algorithm• Step 5: Orientation determination and deviation

reduction– No minimization: One round of forward propagation

determines the orientations for all nodes. Complexity O(U), where U is number of nodes.

P0

2

2

2

3 E

NN

N

NW

S

NW

NWALNH

NH

ALEVAL

WVP0

NH

orientation sets no minimization

The Algorithm• Step 5: Orientation determination and deviation

reduction– Minimizing total/maximum deviation: Implicitly enumerate

possible combinations and pick the best one. Complexity O(F×U), where F is fanout.

P00

0

0

3

P00

2

2

minimizing max deviationminimizing total deviation

The Algorithm

method total deviation

max deviation

no minimization 11Δ 3Δ

minimizing total deviation 5Δ 3Δ

minimizing max deviation 7Δ 2Δ

• Step 5: Orientation determination and deviation reduction

Experimental Results 1• 1024 unit-tests (single bus routing)

– Bit-width=8,16,32,64.– Fanout=1~16.– 0~2 random routing blockages.

• Our bus router (this) is compared with a bus-aware reference router (rrouter).

Experimental Results 1• Success rate.

both routers succeedthis succeed only

rrouter succeed onlyboth fail

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

bit-width=8 bit-width=16

succ

ess

rate

fanout fanout

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

bit-width=32 bit-width=64

fanout fanout

succ

ess

rate

Experimental Results 1“this” vs “rrouter”

• Run time: 20X faster.

• Wire length: Better when fanout<11; 2% longer when fanout approaches 16.

• Ave. driver-load wire length deviation: 188% less.

• Max. driver-load wire length deviation: 469% less.

• Ave. driver-load delay deviation: 286% less.

• Max. driver-load delay deviation: 273% less.

Experimental Results 1• Under variation.

0.1%/um0

“rrouter” has max bit-wise delay deviation of 25ps, while “this” has only 7ps.

Experimental Results 2

Comparison of two flows- the reference router (rrouter)- our router routes bus, forward annotate and then the reference

router finishes the rest (this+rr)

  total wire length (m) #via runtime (min:sec)

design rrouter this+rr rrouter this+rr rrouter this+rr

A1 425823 421889 4257 3621 3:25 3:27

A2 779634 781627 7213 6092 5:11 4:45

A3 1013562 1000581 8605 6669 1:25 1:10

A4 7472888 7453371 6894 4927 3:59 3:54

A5 5770986 5755639 27482 22471 3:57 4:08

Total wire length and via number

• 5 real designs.

0.5% shorter 25% less 7.5% faster

Experimental Results 2

  average deviation maximum deviation max dev w/ variation

design rrouter this+rr rrouter this+rr rrouter this+rr

A1 24.1 6.57 64.1 19.3 68.0 19.3

A2 42.5 8.34 113 18.9 121 19.7

A3 33.2 9.49 79.5 22.0 84.1 28.4

A4 54.1 7.95 265 21.1 542 70.6

A5 45.9 9.16 162 22.8 266 40.9

Average/max driver-load delay deviations (ps)(buses only)

3X smaller 6X smaller

Experimental Results 2Final routing of design “A4”

by rrouter

Experimental Results 2Final routing of design “A4”

by this+rr

Future Work• Embed the algorithm in floorplanning,

global routing …

• Bus validity checking for designers manually floorplanning modules.