scaling and reliability issues of extremely scaled fully ...€¦ · scaling and reliability issues...

Oct-02 TRC on Reliability D.E. Ioannou 1

Scaling and Reliability Issues of Extremely Scaled Fully (FD) Depleted SOI MOSFETs*

Dimitris E. IoannouECE Dept., George Mason University

Fairfax, VA 22030; [email protected]

*Funded by NSF grant # ECS-9900464


Outline

Basic features of SOI and FD-SOI MOSFET Latest simulation results from SOI-02

with intrinsic gate and undoped silicon film ITRS targets can be achieved for both HP and LOP down to the 65 nm technology node

Hot carriers can get hot below 1 Volt ESD I/O protection challenging (again!) Gate tunneling parasitic bipolar transistor


Three Basic Features of SOI

G1

G21

23

Back gate

channel coupling

floating body


Fully Depleted SOI MOSFET

Suzuki et al TED-02, p. 345


Threshold Voltage Control VT depends on gate work function SOI thickness tSi Carrier energy quantization Short Channel Effects (CS and DIBL) For L down to 0.25 m, moderately thin SOI

(~50 nm), relatively thick BOX (~200 nm) and dual- poly gates VT control was achieved by high channel doping


S/D to BOX fringing fields SCE

Highly doped substrate (Ground Plane), coupled with thin BOX controls this effect

T. Ernst, SOI-99


Scaling and field fringing

Scaling (Young, TED-89, p.339):

SOI and BOX thickness (Fossum, SOI-02):

L t tSiox

Si ox2 2> =

sb BOX Si oxeff

ff DSt t t

LV V= +( ) ( )3

3


Field fringing control Scaling tBOX will undermine charge coupling

advantages of FD SOI MOSFET Scaling tSi will suppress field fringing and SCE,

but will diminish depletion chargechannel doping can no longer be used for

threshold voltage control Best solution to use undoped SOI film and

control threshold voltage through gate workfuncton(s)

need exotic gate materials


2002 IEE Intern. SOI Conference

Numerical simulations of deeply scaled FD MOSFETs were presented by several groups (Luyken et al, Fossum et al, Vandooren et al, and others) which examine the role of the gate workfunction; tox and kox; SOI doping and tSi; tBOX and kBOX; gate length, spacer width, S/D doping profiles and back gate bias down to L=18 nm and tSi=5 nm


(Drift diffusion simulations (Silvaco Atlas); Luyken et al, SOI-02)

tSi

Gate

Source Drain

Back Electrode

Buried Oxide

Ls s

gradientd

100nm

Technology node (nm) 90 65 45Year of production 2004 2007 2010Gate length HP (nm) 37 25 18Operating voltage HP (V) 1.0 0.7 0.6Gate oxide thickness HP (nm) 1.3 0.8 0.8Gate length LOP (nm) 53 32 22Operating voltage LOP (V) 1.1 0.9 0.8Gate oxide thickness LOP (nm) 1.8 1.2 1.1

Si-body thickness tSi (nm) 5, 10lateral doping profilegradient d (nm/dec)

Abrupt (0), 3, 5, 7

spacer width s (nm) 0, 5, 10, 15, 25

ITRS (2001) specs used

Parameters varied in the simulations

ND = 2*1020 cm-3

NA = 1015 cm-3

Device structure and simulation parameters


Influence of spacer width and doping profile

1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-40,0

0,5

1,0

1,5

2,0

Ioff=0.1A/m

Ion=900mA/m

ITRS high performance (HP)

Step profile 3nm/ dec 5nm/ dec 7nm/ dec

Ion

(mA/

m)

Ioff (A/m)

Lg = 37nmtSi = 10nmtox = 1.3nmVdd= 1VWf = 4.71eV

Simulation of 20 transistorsSpacer varied from0 nm to 25 nm

Doping profile variedfrom step to 7nm/dec


1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-50,0

0,2

0,4

0,6

0,8

1,0

1,2

1,4

1,6

Wf 4.71eV

Ioff=0.1A/m

Ion=0.9mA/m


Wf 4.51eVWf 4.61eV

Wf 4.81eVIo

n (m

A/

m)

Ioff (A/m)

Design space for HP device with Lg=37 nm and tSi=10 nmwith varying gate workfunction (WF) value

Lg = 37nmtSi = 10nmtox = 1.3nmVdd= 1V

Simulation of 80 transistors

Variation of gate workfunction


1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5

0,2

0,4

0,6

0,8

1,0

1,2

1,4

1,6

Wf 4.71eVIoff=0.1A/m

Ion=0.9mA/m


Wf 4.51eVWf 4.61eV

Wf 4.81eVIo

n (m

A/

m)

Ioff (A/m)

Design space for high performance (HP) device with Lg=37 nm and tSi=5 nm

Lg = 37nmtSi = 5nmtox = 1.3nmVdd= 1V


Gate work-function varied


1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-40,0

0,2

0,4

0,6

0,8

1,0

1,2

1,4

1,6

Wf 4.71eV

Ioff=0.7A/m

Ion=0.9mA/m


Wf 4.51eVWf 4.61eVWf 4.41eV

Ion

(mA

/m

)

Ioff (A/m)

Design space for high performance (HP) device with Lg=25 nm and tSi=5 nm

Lg = 25nmtSi = 5nmtox = 0.8nmVdd= 0.7V


Gate work-function varied


1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-30,0

0,2

0,4

0,6

0,8

1,0

1,2

1,4

1,6

1,8

2,0

Ion=1.2mA/m

Ioff=3A/m

ITRS highperformance (HP)

DoubleGateWf=4.51eV SOI

Wf=4.51eV

Ion

(mA

/m

)

Ioff (A/m)

High performance (HP) device with Lg=18 nm and tSi=5 nm:comparison with double gate device

Lg = 18nmtSi = 5nmtox = 0.8nmVdd= 0.6V


Gate work-function optimized


Hot Carrier Reliability carriers can get hot by a two-step process through

electron-electron scattering (G. La Rosa, IRPS-01 tutorial notes) or thermally assisted impact ionization (P. Su et al, EDL, Sept. 02) at voltages well below 1.2 V.

This possibility and the complicated nature of hot carrier induced degradation of SOI MOSFETs (D.E. Ioannou et al, TED, May 98) suggests that a careful look needs to be taken on the hot carrier reliability of deeply scaled FD-SOI MOSFETs.


Opposite Channel Based Injection

-N+ N+P - +

VG2= -30 V

VS= 0 V VG1= 2 V VD= 7 V

D.E. Ioannou et alTED May 1998


Dit(t)=Atn : pure vs. mixed injection

1 E - 1 2

1 E - 1 1

1 E - 1 0

1 E - 9

1 E + 1 1 E + 2 1 E + 3 1 E + 4 1 E + 5

T im e ( s )

1 0 -1 1

1 0 -9

1 0 -1 0

1 0 -1 2

1 0 51 0 31 0

I C

P (A

)

e le c tro n + h o le in j .n = 0 .5

p u re h o le in j .n = 0 .2 5

p u re e le c tro n in j .n = 0 .2 5

T im e (s )



gm: back accumulated vs. depleted

1

1 0

1 0 0

S t re s s T im e ( s )

G D

egra

datio

n (%

)

1 0 2 1 0 41 0 1 1 0 3 1 05

B a c k D e p le t e d (n = 0 . 5 )

B a c k A c c u m u la t e d (n = 0 . 2 5 )

S t r e s s :V g = V t + 0 . 2 VV d = 7 V ; V g b = 0



HC degradation at L=70nm

0.0 0.2 0.4 0.6 0.8 1.00.0

2.0x10-10

4.0x10-10

6.0x10-10

8.0x10-10

1.0x10-9

L=70nm, Vd=2.2V

1.022E-10 A

8.66E-10 A

I CP (

A)

VSB (V)

Before Stress After Stress

PD-SOI MOSFET:

tOX=1.6nm, tBOX=100nm stressed@ISUBMAX with VD=2.2V for 5000s

Charge Pumping results

E.Zhao, SOI_02


ESD I/O Protection (I)

ESD in SOI posses unique challenges due to nature of SOI structure itself:

Active layers electrically and thermally separated from substrate

Conventional ESD protection circuits unsuitable because of vertical current and heat flow paths

Must form sufficient ESD current and heat flow paths above the active layers


ESD I/O Protection (II)

Clever solutions have been found both for PD and FD SOI CMOS, down to silicon film thickness of 50 nm.Two of the most successful use SOI MOSFETs as protection devices with

Gate-Coupled (Biased) SOI-MOSFETGate-Body Coupled SOI- MOSFET


Gate-Biased MOSFET

Drain MOS-CAP NWELL-RES Source

N+ N+N N

P-SIMOX

P-SUB


Gate-Body Coupled MOSFET


ESD I/O Protection (III)

These solutions will not in my view continue to provide ESD protection through evolution for silicon film thickness approaching 5 nm

Radically new approaches and circuit techniques will be need to be developed

For example, SOI film may need to be locally removed to fabricate protection circuit on bulk


Conclusions

Simulations show ITRS targets can be met, but:intrinsic (exotic) gate materials needed

ultrathin (~ 5 nm), undoped SOI wafers needed

Hot carrier reliability unknown: carriers can get hot at very low voltages; channel coupling and floating body complicates hot carrier degradation

ESD I/O protection: unknown and very challenging


Acknowledgements/thanks to:

D. Antoniadis and J. Hutchby for inviting me J. Fossum (University of Florida); R. Luyken

(Infineon Technologies AG); A. Vandooren (Motorola); E. Zhao (AMD):

for lending me their (SOI-02) viewgraphs My students, past and present NSF for financial support

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