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Serial ATA 2010/01

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ATA Introduction

Serial ATA2010/01

OutlineCommunication LayerA Command ExampleSATA Physical LayerSATA Link LayerSATA Transport LayerSATA FIS TypeSATA Command Layer Protocol (Command sequence)

SATA Communication Layers Application LayerTransport Layer Link LayerPhysical Layer

8b/10b streamStatusFIS8b/10b streamFISCommandSATA HOSTApplication LayerTransport Layer Link LayerPhysical Layer

8b/10b streamStatusFIS8b/10b streamFISCommandSATA DEVICE

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Command Example

4

Command & FIS

#2#1#3READ DMACommand InputCommand OuputDATA,Data Payload5dwordsFIS Command Input/OutputCommand(Input/Output)FIS

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Command Inputs

Main Field

Command FeaturesSector CountLBA

Command Outputs

Reserved for Normal Output

Main Field

Status Error

Normal OutputError OutputStatus=0x51Error=0x04CMD Abort(Command is invalid)

0x10ID Not Found(Command parameter is invalid , eg. invalid LBA)

0x40Uncorrectable data error (ECC Error)

0x80ICRC Error (Data transmitted/received has CRC error) Reissue the command.

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SATA StatusBSY (Busy) : 1 : the device is busy .DRDY (Device Ready) :1 : device is ready to accept all commands.0 : device only accepts a few commands.(DEVICE RESET, EXEUTE DEVICE DIAGNOSTIC, IDENTIFY PACKET DEVICE, PACKET).DF (Device Fault) :1 : device had a data fatal hard error . Prevents writing data. DRQ (Data request) :1 : device is ready for data transfer.ERR (Error) :1 : an error occurred during execution command.SERV (Service) :1 : device has prepared this command for service.(DMA Queued)Bit765430

Description

Status = 50 (DRDY=1,BSY=0,DRQ=0,ERR=0)Status = 51 (DRDY=1,BSY=0,DRQ=0,ERR=1)Status = 58 (DRDY=1,BSY=0,DRQ=1.ERR=0)Status = D0 (DRDY=1,BSY=1,DRQ=0,ERR=0)

bit4 = DSC (Device Seek Complete) bit. (SERV) Service bit , Deferred Write Error (DWE) bit8

Physical LayerHow to Power-On? Host sends COMREST signal to device. OOB(Out-of-band) : COMREST(H2D)COMINIT(D2H)COMWAKE

Power-On Sequence Timing Diagram

HostCOMRESTDeviceCOMINIT

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Link LayerResolves arbitration conflicts if both host and device request transmission.Inserts frame envelope around Transport layer data (i.e. SOF, EOF, HOLD, etc.).Receives data in the form of DWORDs from the Transport layer.Calculates CRC on Transport layer data to do error checking .8b/10b encoding/decoding Byte + Control .

PrimitiveDescriptionSOFStart of frameEOFEnd of frameHOLDHold datatransmissionHOLDASend ack. while HOLD is receivedCONTContinuerepeatingpreviousprimitive.

SOFFIS1HOLDFIS1(cont.)CRCEOF

Link Layer FIS1FIS2FIS3

Transport Layer

Dword

DwordDwordDwordsDwordDwordsSIZE FIS(Frame Information Structure)

CRC(Cyclic Redundancy Check)8b/10b DC-balancedSOF(Start of frame)EOF(End Of Frame)FIS(Frame Information Structure)The smallest unit of communication is a Dword

Frame TransmissionWhen requested by the Transport layer to transmit a frame, the Link layer provides the followingservices: Negotiates with its peer Link layer to transmit a frame, resolves arbitration conflicts ifboth host and device request transmission Inserts frame envelope around Transport layer data (i.e., SOFP, CRC, EOFP, etc.). Receives data in the form of Dwords from the Transport layer. Calculates CRC on Transport layer data. Transmits frame. Provides frame flow control in response to requests from the FIFO or the peer Linklayer. Receives frame receipt acknowledge from peer Link layer. Reports good transmission or Link/Phy layer errors to Transport layer. Performs 8b/10b encoding Scrambles data Dwords in such a way to distribute the potential EMI emissions overa broader range9.1.2 Frame ReceptionWhen data is received from the Phy layer, the Link layer provides the following services: Acknowledges to the peer Link layer readiness to receive a frame. Receives data in the form of encoded characters from the Phy layer. Decodes the encoded 8b/10b character stream into aligned Dwords of data. Removes the envelope around frames (i.e., SOFP, CRC, EOFP). Calculates CRC on the received Dwords. Provides frame flow control in response to requests from the FIFO or the peer Linklayer. Compares the calculated CRC to the received CRC. Reports good reception or Link/Phy layer errors to Transport layer and the peer Linklayer. Descrambles data Dwords received from a peer Link layer.10

Transmission example FIS1

FIS1(Cont.)

Transmitter has data ready ,and send (X_RDY) two times .Receiver send (R_RDY) when ready to receive data.Transmitter start a data transfer when (R_RDY) is received .Receiver send (R_IP) to transmitter that receiver is still receiving data now. When transmitter not have next data ready , (HOLD) is sent to receiver.(HOLDA) will be sent by receiver as long as (HOLD) is received.(EOF) is sent when a data transfer is finished.After (EOF) is sent , the transmitter will send (WTRM) while waiting for reception status from receiver.If receiver detected this received data no error , (R_OK) is sent , otherwise (R_ERR) is sent.

CONT, is Continue previous primitivesType : FIS TypeData : FIS payload DataPrimitive handshakes HOLD HOLDA WTRM R_OK / R_ERR PMREQ_P / PMREQ_S PMACK / PMNAK

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Transport LayerConstructs Frame Information Structures (FISes) for transmissionDecomposes received Frame Information Structures

SATA FIS types

Different FISes are used for different types of commands.FIS TypeSizeFIS nameDirectionUsed for27h20Command FIS (Register FIS ,C=1) Host to DeviceNon-Data, PIO, DMA, FPDMA27h20Control FIS(Register FIS , C=0) Host to DeviceNon-Data, PIO, DMA, FPDMA34h20Response FIS(Register FIS -D2H) Device to HostNon-Data, PIO, DMA, FPDMA39h4DMA Activate FIS Device to HostDMA , DMAQ ,FPDMA41h28FPDMA Setup FISBi-directionalFPDMA46h4~8196Data FISBi-directionalPIO, DMA, FPDMA58h12BIST Active FISBi-directionalBIST5Fh20PIO Setup FISDevice to HostPIO, ATAPIA1h8Set Device Bits FISBi-directionalDMAQ , FPDMA

5Dwords Serial ATA Revision 2.6 ATA8-AST

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Register FIS Host to Device (27h)

C bit set to 1.Used for ? Host sends "Command" to device.N,H bit is not supported for SATA.

Command FIS : C bit cleared to 0.S bitSRST (Soft Reset). If set to one, the bit indicates that a Soft Reset operation has been requested by the host.

Control FIS :

Response FIS (34h) (Register FIS - D2H)When sent ? Power-On Command completion & return device statusI : Interrupt pending Bit. reflects the Interrupt Pending state of the device.If the received BSY and DRQ are both cleared host adapter shall discard the contents of the received FIS.

Response FIS :

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PIO Setup FIS (5Fh) (D2H)When sent ? Sent to host before sending a Data FIS containing PIO read. Sent to host to request a Data FIS containing PIO write data.Ending status (E_Status) : Contains the new value of the Status register at the conclusion of the subsequent Data FIS. E_Status is returned before the PIO Read data transfer.D bit indicates whether host memory is being written or read by device . 1=write (D2H) 0=read (H2D)

PIO Setup FIS :

starting status

ending status

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Data FIS (46h) (bidirectional)Contains read (device-to-host) or write (host-to-device) dataMinimum: 1 Dword + 4 bytesMaximum: 8192 bytes (2048Dwords) + 4 bytesThe high order word (word 1) of the last Dword is padded with zeros when only a partial Dword (odd number of words) is to be transmitted.

Data FIS :

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DMA Activate FIS (39h) (D2H)When sent ? When device is ready to start receive DMA write data.Must be received prior to each write Data FIS from device .Not used on DMA reads .

DMA Activate FIS :

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Set Device Bits(A1h) (D2H)Sends updated Error and Status bits to the host Does not alter BSY (bit 7) or DRQ (bit 3) of the Status register

Used for DMA Queuing To set the SERV bit in the Status register for queued commands.Used for FPDMA native queuing SActive bits indicate which commands are queued and which are completed. 32 tags supported .

Set Device Bits FIS :

SERV

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FPDMA Setup FIS(41h) (bidirectional)When sent?Used for selecting the memory buffer for data transfer . A (auto-activate) bit Device will not send a DMA Activate FIS to throttle write data; host can send Data FIS immediatelyD (direction) bit 1=write , 0=readDMA Buffer Identifier fields (Buffer ID=Tag) 32Buffer,NCQ Tag Bottom 5 bits of Low field carry the Tag (Identify the DMA buffer region in host memory ) All other bits are zero DMA Buffer Offset Random access .DMA Transfer Count Number of bytes to be read or written.First Party DMA Setup FIS :

00Tag

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Serial Transport Device Command Layer Protocol State MachinesPower-on and COMRESET protocolDevice Idle protocolSoftware reset protocolEXECUTE DEVICE DIAGNOSTIC command protocolDEVICE RESET command protocolNon-data command protocolPIO data-in (Read) command protocol PIO data-out (Write) command protocolDMA data-in (Read) command protocolDMA data-out (Write) command protocolREAD DMA QUEUED command protocol (TCQ)WRITE DMA QUEUED command protocol (TCQ)FPDMA QUEUED command protocol (NCQ)(SATA II)PACKET protocol

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Power-on and COMRESET protocolAfter completing a phy reset sequence, device runs diagnostics and transmits a FIS with the results.SATA HOSTSATA DEVICECOMRESTBegin phy reset sequenceExecute diagnosticsResponse FIS (I=0)Detect phy reset sequence completionUpdate shadow register(BSY=0)2.Interrupt host3.Host reads Status registerUpdate task file registerDetect phy reset sequence completion

ISR . IS_PHY_RDY

Software reset protocolCauses diagnostics to be run, returning the appropriate signature.SATA HOSTSATA DEVICEControl FISHost writes Control register withSRST=1Start resetResponse FIS (I=0)Host writes Control register withSRST=01. Update shadow registers(BSY=0)2. Interrupt host3. Host reads task file registersExecute diagnosticsUpdate task fileregisters with signatureGood: Error = 01hBad: Error = not 01hControl FIS

ISR . IS_SW_RST

SRST (Software Reset) bit Used to force a soft device Decodes of writes to this bit could be done by low-powerhardware in parallel ATA Not as simple for serial ATA23

Device Idle protocol

Power-On

Command FIS1Receive FIS & Check FIS23ISR . NON_DATAISR . READ_CMDISR . WRITE_CMD4

EXECUTE DEVICE DIAGNOSTIC command protocol

EXECUTE DEVICE DIAGNOSTIC(0x90)1 Send Response FIS (D2H) with good statusA Send Response FIS (D2H) with bad statusB

SerialATA_Revision_2_6_Gold.pdf ( p.392) When in this state, the device shall request that the Transport layer transmit a Register FIS to thehost, with the Interrupt bit set to one. If the device does not implement the PACKET commandfeature set the register content shall be:25

Response FIS for EXECUTE DIAGNOSTIC

Status = 50 (DRDY=1,BSY=0,DRQ=0,ERR=0)I = 0 for SW_RST or HW_RST (Power-On)Error = 1 Deivce 0 passed,Device 1 passed or not presentCount = 1 , LBA = 1 General

Send statusATAATAPI

SATAdevice0ATA_FIS_Engine(RESPONSE_FIS,FALSE,FALSE,FALSE,FALSE,1,28,0x50,0x00,FALSE,FALSE,0x01,0x01,0x00); //STATUS=50, INT=1 ,Error=1( Deivce 0 passed,Device 1 passed or not present),Count=1(Reserved for SATA),LBA=1(Reserved)

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Non-data command protocolDEVICE RESET and EXECUTE DEVICE DIAGNOSTIC commands use same sequence.SATA HOSTSATA DEVICECommand FIS1. Host initializes shadow taskfile registers (BSY=1)Parse commandResponse FIS2. Write Command register1. Update shadow registers(BSY=0)2. Interrupt host3. Host reads Status registerProcess commandSend status

Non-data command protocol

Non-data command 1ISR . IS_NON_DATA_CMD

2 Response FIS (D2H)3CFA ERASE SECTORSCFA REQUEST EXTENDED ERROR CODECHECK POWER MODEFLUSH CACHEFLUSH CACHE EXTGET MEDIA STATUSIDLEIDLE IMMEDIATEINITIALIZE DEVICE PARAMETERSMEDIA EJECTMEDIA LOCKMEDIA UNLOCKNOPREAD NATIVE MAX ADDRESSREAD NATIVE MAX ADDRESS EXTREAD VERIFY SECTOR(S)READ VERIFY SECTOR(S) EXTSECURITY ERASE PREPARESECURITY FREEZE LOCKSEEKSET FEATURESSET MAX ADDRESSSET MAX ADDRESS EXTSET MULTIPLE MODESLEEPSMART DISABLE OPERATIONSMART ENABLE/DISABLE AUTOSAVESMART ENABLE OPERATIONSMART EXECUTE OFFLINE IMMEDIATESMART RETURN STATUSSTANDBYSTANDBY IMMEDIATE*DEVICE RESET*EXECUTE DEVICE DIAGNOSTIC

DEVICE RESET command protocol

DEVICE RESET (0x08)1Status = 50 (DRDY=1,BSY=0,DRQ=0,ERR=0)I = 1 Error = 1 Deivce 0 passed,Device 1 passed or not presentCount = 1 , LBA = EB1401 General

Response FIS (D2H)2

ATA_FIS_Engine(RESPONSE_FIS,FALSE,FALSE,FALSE,FALSE,1,28,0x50,0x01,FALSE,FALSE,0x01,0xEB1401,0x00);

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Task fileThe task file is in the ATA deviceIn parallel ATA, accesses to these registers result in parallel ATA trafficIn serial ATA, a Shadow Task file register bank is also managed by the host to mirror the ATA devices task fileSerial ATAHost adapterShadow Task file

DeviceTask file

PCI BusParallel ATAHostadapterPASS

DeviceTask file

PCI BusTask file Command RegisterData RegisterDevice RegisterDevice Control RegisterStatus Register / Feature RegisterSector Count RegisterLBA RegisterSStatus,SError,SControl,SActive register

FIS(I=1)Host,Host status register (BSY=0,DRQ=0) 30

PIO Read command protocolSATA HOSTSATA DEVICECommand FIS1. Host initializes shadow taskfile registers (BSY=1)PIO Setup FIS ( I=1 ,D=1 , Status=58, E_status=D0 ) 2. Write Command register Data FIS(BSY=0,DRQ=1)(BSY=1,DRQ=0)PIO Setup FIS ( I=1 ,D=1 , Status=58, E_status=50 ) (BSY=0,DRQ=1)(BSY=0,DRQ=0)Update task file registers (BSY=0,DRQ=0)Data FIS (Final) (BSY=0,DRQ=1)(BSY=1,DRQ=0)(BSY=0,DRQ=1)(BSY=0,DRQ=0)1. Update shadow registers with PIO Setup starting contents 2. Interrupt host 3. Host reads Status register4. Host reads Data register n times5. Update shadow registers with PIO Setup ending contents >8K1. Update shadow registers with PIO Setup starting contents 2. Interrupt host 3. Host reads Status register4. Host reads Data register last times5. Update shadow registers with PIO Setup ending contents Preparing a DRQ data blockTransmit dataIf error has occurred , Send Response FISResponse FIS ( I=1,Status=51) Interrupt host (BSY=0)Preparing a DRQ data block

8K,Setup PIO FIS HostStatus = 0x58 -> (DRDY=1,BSY=0,DRQ=1.ERR=0) , I=11.BSY=0 , DRQ=1, I=1E_STATUS = 0xD0 : DRDY=1 , BSY=1 , DRQ=0E_STATUS = 0x50 : DRDY=1 , BSY=0 , DRQ=0IDENTIFY DEVICE //Temp_SATA_ISR&SATA_IS_IDENTIFY_CMDIDENTIFY PACKET DEVICEREAD BUFFERREAD LOG EXTREAD MULTIPLEREAD MULTIPLE EXTREAD SECTOR(S)READ SECTOR(S) EXTSMART READ DATASMART READ LOG SECTOR

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PIO Write command protocolResponse FIS ( I=1 , Status=50?)Data FIS1. Update shadow registers Device-to-host register FIS2. Interrupt host (BSY=0)

SATA HOSTSATA DEVICECommand FIS1. Host initializes shadow taskfile registers (BSY=1)PIO Setup FIS ( I=0 ,D=0 , Status=58, E_status=D0 ) 2. Write Command register 3.Wait Device return FIS(BSY=0,DRQ=1)(BSY=1,DRQ=0)PIO Setup FIS ( I=1 ,D=0 , Status=58, E_status=D0 ) (BSY=0,DRQ=1)(BSY=1,DRQ=0)Update task file registers (BSY=0,DRQ=0)(BSY=0,DRQ=1)(BSY=1,DRQ=0)(BSY=0,DRQ=1)(BSY=1,DRQ=0)1. Update shadow registers with PIO Setup starting contents 2. Host reads Status register3. Host Write Data register first times4. Update shadow registers with PIO Setup ending contents >8K1. Update shadow registers with PIO Setup starting contents 2. Interrupt host 3. Host reads Status register4. Host Write Data register n times5. Update shadow registers with PIO Setup ending contents 1st Data FISPrepare to receive DRQ data blockReceive dataSend statusDevice processing dataDevice processing data

BSY=1 Host , device,data

CFA WRITE MULTIPLE WITHOUT ERASECFA WRITE SECTORS WITHOUT ERASEDOWNLOAD MICROCODESECURITY DISABLE PASSWORDSECURITY ERASE UNITSECURITY SET PASSWORDSECURITY UNLOCKSMART WRITE LOG SECTORWRITE BUFFERWRITE LOG EXTWRITE MULTIPLEWRITE MULTIPLE EXTWRITE SECTOR(S)WRITE SECTOR(S) EXT32

DMA Read command protocol

SATA HOSTSATA DEVICECommand FIS (READ DMA)1. Host initializes shadow taskfile registers (BSY=1)Data FIS2. Write Command registerDMA controller receives dataResponse FIS (I=1)1. Update shadow registers2. Interrupt host(DRQ=0, BSY=0)>8KSend statusUpdate task file registers (BSY=0,DRQ=0)Send dataPrepare data

READ DMA READ DMA EXT33

DMA Write command protocolSATA HOSTSATA DEVICECommand FIS (WRITE DMA)1. Host initializes shadow taskfile registers (BSY=1)DMA Activate FIS2. Write Command register1. Activate DMA controller2. DMA controller transfers write dataResponse FIS ( I=1)1. Update shadow registers2. Interrupt host(DRQ=0, BSY=0)Data FIS

>8KSend statusReceive dataPrepare to receiveReady to receive data

WRITE DMAWRITE DMA EXT34

Read DMA Queued command protocolResponse FIS (Status=50) Response FIS ( I=1 , Status=50?) Interrupt host (BSY=0,DRQ=0)SATA HOSTSATA DEVICE1. Host initializes DMA controller(BSY=1) ( BSY=01 ,REL= Count[2]=1, I/O = Count[1] = 0 , Count[0]=1 , I=1 if release interrupt enabled ) 2. Send READ DMA QUEUED Command Count[7:3] = TAG

Response FIS ( Status=58, Count[7:3]=TAG ) (BSY=0,DRQ=1)Update task file registers (BSY=0,DRQ=0)(BSY=1)Interrupt host2. Host deactivates 3rd DMA controller3. Host issue SERVICE command>8KRead TAG & backup DMA controller contextQueue command

Command FIS (READ DMA QUEUED)Set Device Bits FIS ( SERV=1 , I=1 )Device is ready to transfer data & Service requestCommand FIS (SERVICE)Host release bus / command (BSY=0,DRQ=1)(BSY=0)more commadsData FISSend dataDMA controller receives data ( REL= Count[2]=0, I/O = Count[1] = 1 , Count[0]=0) ( REL= Count[2]=0, I/O = Count[1] = 1 , Count[0]=1)Response with command that ready to executeDevice processing dataWait for the CPU to respond to the interrupt Deactivate the 3rd party DMA engineSend statuslast command queued in(BSY=1)more queued commands not complete

When a drive was ready for a transfer, it had to interrupt the CPU, wait for the CPU to ask the disk what command was ready to execute, respond with the command that it was ready to execute, wait for the CPU to program the host bus adapter's third party DMA engine based on the result of that command, wait for the third party DMA engine to execute the command, and then had to interrupt the CPU again to notify it when the DMA engine finished the task so that the CPU could notify the thread that requested the task that the requested task was finished.

DMA Controller : DMA BufferID ,Transfer Conut READ DMA QUEUED READ DMA QUEUED EXT35

Write DMA Queued command protocolResponse FIS (Status=50) Response FIS ( I=1 , Status=50?) Interrupt host (BSY=0,DRQ=0)SATA HOSTSATA DEVICE1. Host initializes DMA controller(BSY=1) ( BSY=01 ,REL= Count[2]=1, I/O = Count[1] = 0 , Count[0]=1 , I=1 if release interrupt enabled ) 2. Send READ DMA QUEUED Command Count[7:3] = TAG

Response FIS ( Status=58, Count[7:3]=TAG ) (BSY=0,DRQ=1)Update task file registers (BSY=0,DRQ=0)(BSY=1)1. Interrupt host2. Host deactivates DMAcontroller3. Host issue SERVICE command>8KRead TAG & restore DMA controller contextQueue command

Command FIS (WRITE DMA QUEUED)Set Device Bits FIS ( SERV=1 , I=1 )Device is ready to transfer data & Service requestCommand FIS (SERVICE)Host release bus / command (BSY=0,DRQ=1)(BSY=0)more commadsDMA Activate FISReceive dataDMA controller sends data ( REL= Count[2]=0, I/O = Count[1] = 1 , Count[0]=0) ( REL= Count[2]=0, I/O = Count[1] = 1 , Count[0]=1)Response with command that ready to executeSend statuslast command queued in(BSY=1)

more queued commands not complete

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NCQ ; TCQUseREAD FPDMA QUEUED , WRITE FPDMA QUEUED Command.The SATA host bus adapter(HBA) integrated its own first party DMA engine.Device issuesFPDMA Setup FISto HBA to select memory buffer directly without third-party DMA engine and tells the HBA which command it wants to execute.Device issuesSend Device Bits FISto return status of multiple commands completed.Drastically reduces the number of required CPU interrupts.For NCQ to be enabled, it must be supported and enabled in the SATA host bus adapter.Windows Vista/7 natively supports NCQ , not Windows XP .SATA NCQ (Native-command queuing) : ATA TCQ (Tagged-command queuing) : UseREAD DMA QUEUED , WRITE DMA QUEUED Command.Available in both Parallel and Serial ATAUse ATA host bus adapter's third party DMA engine.It caused high CPU utilization without improving performance enough to make this worthwhile , because service command and responding to interrupts uses CPU time , CPU utilization rose quickly .Improve the overall performance of a hard drive device.Device can make its own decisions about how to order the requests.Up to queue 32 commands by using tag. ( IDENTIFY DEVICE word 75)

SATA 2.5SATA II3Gb/sNCQStaggered Spin-upHot PlugPort MultipliereSATAFPDMA FPDMANCQ differs from ATA TCQ in that in NCQ, the host bus adapter programmed its own first partyDMAengine with the DMA parameters that the CPU gave when it issued the command, and that in ATA TCQ, the CPU must be interrupted by the ATA device so that the CPU can ask the ATA device which command is ready to be executed so that the CPU can program the ATA host bus adapter's third party DMA engine

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FPDMA Read command protocolResponse FIS (Status=50) Interrupt host (BSY=0,DRQ=0)SATA HOSTSATA DEVICE(BSY=0) ( BSY=0 ,DRQ= 0 , I=0 )

Send READ FPDMA QUEUED Command Count[7:3] = NCQ TAG (BSY=1)

Update task file registers (BSY=0)Select the DMA engine context by TAG(DMA Buffer ID)Host loads PRD pointer into DMA engine DMA controller receives data

Command FIS (READ FPDMA QUEUED)Host sets SActive Register(BSY=0)more commadsData FISSend dataDMA Setup FISSet Device Bits FIS (BSY=0 , I=1 , SActive )(DMA Buffer ID= TAG , D=1 , I=0, Transfer count )this command not complete

Transfer count not exhaustedbit n in SActive field set to one where n = TAG for each command TAG value that has completedQueue command & store NCQ TAG in SActive Send statusMultiple commands can be indicated as complete at a time

more queued commands not completeUpdate Host copy SActive Register

Interrupt Aggregation & race-free (Returning status)Multiple commands can be indicated as complete at a time device () SDB FIS, FIS , 2interruptinterrupthost38

FPDMA Write command protocolResponse FIS (Status=50) Interrupt host (BSY=0,DRQ=0)SATA HOSTSATA DEVICE(BSY=0) ( BSY=0 ,DRQ= 0 , I=0 )

Send WRITE FPDMA QUEUED Command Count[7:3] = NCQ TAG (BSY=1)

Update task file registers (BSY=0)Select the DMA engine context by TAG(DMA Buffer ID)Host loads PRD pointer into DMA engine DMA controller sends data

Command FIS (WRITE FPDMA QUEUED)(BSY=0)more commadsDMA Activate FISReceive dataDMA Setup FISSet Device Bits FIS (BSY=0 , I=1 ,SActive)(DMA Buffer ID= TAG , D=0 , I=0, Auto-Activate=1 ,Transfer count )this command not completeTransfer count not exhaustedbit n in SActive field set to one where n = TAG for each command TAG value that has completedQueue command & store NCQ TAG in SActive

Data FIS if Auto-Activate==0 Send status

more queued commands not completeMultiple commands can be indicated as complete at a timeHost sets SActive RegisterUpdate Host copy SActive Register

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END2010/01

PIO Read command protocol

PIO READ Command1Prepare Data Block2Send PIO Setup FIS to HOST3Status = 0x58 (DRDY=1,BSY=0,DRQ=1.ERR=0) , More Data to transmitAAll Data transmit completed5If error has occurred , Send Response FIS (status=0x51)B4Send Data FIS to HOST

IDENTIFY DEVICE //Temp_SATA_ISR&SATA_IS_IDENTIFY_CMDIDENTIFY PACKET DEVICEREAD BUFFERREAD LOG EXTREAD MULTIPLEREAD MULTIPLE EXTREAD SECTOR(S)READ SECTOR(S) EXTSMART READ DATASMART READ LOG SECTOR

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PIO Write command protocol

PIO Write Command 1Prepare Data block (Buffer)2Send PIO Setup FIS to HOST34Receive Data FIS from HOSTSend Response FIS (status=50 or 51)5

CFA WRITE MULTIPLE WITHOUT ERASECFA WRITE SECTORS WITHOUT ERASEDOWNLOAD MICROCODESECURITY DISABLE PASSWORDSECURITY ERASE UNITSECURITY SET PASSWORDSECURITY UNLOCKSMART WRITE LOG SECTORWRITE BUFFERWRITE LOG EXTWRITE MULTIPLEWRITE MULTIPLE EXTWRITE SECTOR(S)WRITE SECTOR(S) EXT42

DMA Read command protocol

READ DMA READ DMA EXT43

DMA Write command protocol

WRITE DMAWRITE DMA EXT44

Read DMA Queued command protocol

READ DMA QUEUED READ DMA QUEUED EXT45

Write DMA Queued command protocol

READ DMA READ DMA EXT46

Power-on and COMRESET protocol

POWER-ON COMRESET 1Initialize HWExecute diagnostics3 Send Response FIS (D2H)4

ISR . IS_PHY_RDY2

Software reset protocol

ISR . IS_SW_RST3Control FIS (SRST=1)1Control FIS (SRST=0)2Initialize HWExecute diagnostics4 Send Response FIS (D2H)5

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