sata introduction

Serial ATA

2010/01

OutlineCommunication LayerA Command ExampleSATA Physical LayerSATA Link LayerSATA Transport LayerSATA FIS TypeSATA Command Layer Protocol

(Command sequence)

SATA Communication Layers

Application Layer

Transport Layer

Link Layer

Physical Layer

8b/10b stream

Status

FIS

8b/10b stream

FIS

Command

SATA HOST

Application Layer

Transport Layer

Link Layer

Physical Layer8b/10b stream

Status

FIS

8b/10b stream

FIS

Command

SATA DEVICE

Command Example

Command & FIS

#2

#1

#3

READ DMA Command Input Command OuputDATA

＊其實這張圖並不是很正確 , 因為 Data Payload 的 5dwords 是指 FIS 的大小，並不是 Command Input/Output 的大小，但是 Command 看到的欄位 (Input/Output) 的確　是填在 FIS 中的。

Command Inputs Main Field ：

1.Command 2.Features3.Sector

Count4.LBA

Command Outputs

Reserved for Normal Output

Main Field ：1.Status 2.Error

Normal Output Error Output

Status=0x51Error=0x04CMD Abort(Command is invalid)

0x10ID Not Found(Command parameter is invalid , eg. invalid LBA)

0x40Uncorrectable data error (ECC Error)

0x80ICRC Error (Data transmitted/received has CRC error) Reissue the command.

SATA Status

BSY (Busy) : 1 : the device is busy .

DRDY (Device Ready) : 1 : device is ready to accept all commands. 0 : device only accepts a few commands.

(DEVICE RESET, EXEUTE DEVICE DIAGNOSTIC, IDENTIFY PACKET DEVICE, PACKET).

DF (Device Fault) : 1 : device had a data fatal hard error . Prevents writing data.

DRQ (Data request) : 1 : device is ready for data transfer.

ERR (Error) : 1 : an error occurred during execution command.

SERV (Service) : 1 : device has prepared this command for service.(DMA Queued)

Bit

7

6

5

4

3

0

Description

Status = 50 (DRDY=1,BSY=0,DRQ=0,ERR=0)Status = 51 (DRDY=1,BSY=0,DRQ=0,ERR=1)Status = 58 (DRDY=1,BSY=0,DRQ=1.ERR=0)Status = D0 (DRDY=1,BSY=1,DRQ=0,ERR=0)

Physical Layer How to Power-On?

Host sends COMREST signal to device. OOB(Out-of-band) : COMREST(H2D) 、 COMINIT(D2H) 、 COMWAKE 。

Power-On Sequence Timing Diagram

HostCOMRES

TDevice

COMINIT

Link Layer Resolves arbitration conflicts if both host and device request

transmission. Inserts frame envelope around Transport layer data (i.e. SOF, EOF,

HOLD, etc.). Receives data in the form of DWORDs from the Transport layer. Calculates CRC on Transport layer data to do error checking . 8b/10b encoding/decoding Byte + Control . Primitive Description

SOF Start of frame

EOF End of frame

HOLD Hold datatransmission

HOLDA Send ack. while HOLD is received

CONT Continuerepeatingpreviousprimitive.

SOF FIS1 HOLDFIS1

(cont.)

CRC EOFLink Layer

FIS1 FIS2 FIS3Transport Layer

Dword DwordDwordDwordsDwordDwordsSIZE

FIS(Frame Information Structure)

Transmission example

FIS1

FIS1(Cont.)

1. Transmitter has data ready ,and send (X_RDY) two times .

2. Receiver send (R_RDY) when ready to receive data.

3. Transmitter start a data transfer when (R_RDY) is received .

4. Receiver send (R_IP) to transmitter that receiver is still receiving data now.

5. When transmitter not have next data ready , (HOLD) is sent to receiver.

6. (HOLDA) will be sent by receiver as long as (HOLD) is received.

7. (EOF) is sent when a data transfer is finished.

8. After (EOF) is sent , the transmitter will send (WTRM) while waiting for reception status from receiver.

9. If receiver detected this received data no error , (R_OK) is sent , otherwise (R_ERR) is sent.

Transport Layer

1. Constructs Frame Information Structures (FISes) for transmission

2. Decomposes received Frame Information Structures

SATA FIS types Different FISes are used for different types of commands.

FIS Type Size FIS name Direction Used for27h 20 Command FIS

(Register FIS ,C=1)

Host to Device Non-Data, PIO, DMA, FPDMA

27h 20 Control FIS(Register FIS , C=0)

Host to Device Non-Data, PIO, DMA, FPDMA

34h 20 Response FIS(Register FIS -D2H)

Device to Host Non-Data, PIO, DMA, FPDMA

39h 4 DMA Activate FIS

Device to Host DMA , DMAQ ,FPDMA

41h 28 FPDMA Setup FIS Bi-directional FPDMA

46h 4~8196

Data FIS Bi-directional PIO, DMA, FPDMA

58h 12 BIST Active FIS Bi-directional BIST

5Fh 20 PIO Setup FIS Device to Host PIO, ATAPI

A1h 8 Set Device Bits FIS

Bi-directional DMAQ , FPDMA

Register FIS – Host to Device (27h)

C bit set to 1. Used for ?

Host sends "Command" to device.

N,H bit is not supported for SATA.

Command FIS :

C bit cleared to 0. S bit–SRST (Soft Reset). If

set to one, the bit indicates that a Soft Reset operation has been requested by the host.

Control FIS :

Response FIS (34h) (Register FIS - D2H)

When sent ? Power-On Command completion & return device status

I : Interrupt pending Bit. reflects the Interrupt Pending state of the device.

If the received BSY and DRQ are both cleared host adapter shall discard the contents of the received FIS.

Response FIS :

PIO Setup FIS (5Fh) (D2H)

When sent ? Sent to host before sending a Data FIS containing PIO read. Sent to host to request a Data FIS containing PIO write data.

Ending status (E_Status) : Contains the new value of the Status register at the conclusion of the subsequent Data FIS. E_Status is returned before the PIO Read data transfer.

D bit indicates whether host memory is being written or read by device . 1=write (D2H) 0=read (H2D)

PIO Setup FIS :

starting status

ending status

Data FIS (46h) (bidirectional)

Contains read (device-to-host) or write (host-to-device) data Minimum: 1 Dword + 4 bytes Maximum: 8192 bytes (2048Dwords) + 4 bytes The high order word (word 1) of the last Dword is padded

with zeros when only a partial Dword (odd number of words) is to be transmitted.

Data FIS :

DMA Activate FIS (39h) (D2H)

When sent ? When device is ready to start receive DMA write data.

Must be received prior to each write Data FIS from device . Not used on DMA reads .

DMA Activate FIS :

Set Device Bits(A1h) (D2H)

Sends updated Error and Status bits to the host Does not alter BSY (bit 7) or DRQ (bit 3) of the Status register

Used for DMA Queuing To set the SERV bit in the Status register for queued commands.

Used for FPDMA native queuing SActive bits indicate which commands are queued and which are completed. 32 tags supported .

Set Device Bits FIS :

SERV

FPDMA Setup FIS(41h) (bidirectional)

When sent?Used for selecting the memory buffer for data transfer .

A (auto-activate) bit Device will not send a DMA Activate FIS to throttle write data; host can send Data FIS immediately

D (direction) bit 1=write , 0=read

DMA Buffer Identifier fields (Buffer ID=Tag) 共 32 個 Buffer, 與 NCQ Tag 對應。 Bottom 5 bits of Low field carry the Tag (Identify the DMA buffer region in host memory ) All other bits are zero

DMA Buffer Offset Random access .

DMA Transfer Count Number of bytes to be read or written.

First Party DMA Setup FIS : 0

0Tag

Serial Transport Device Command Layer Protocol State Machines

1. Power-on and COMRESET protocol2. Device Idle protocol3. Software reset protocol4. EXECUTE DEVICE DIAGNOSTIC command protocol5. DEVICE RESET command protocol6. Non-data command protocol7. PIO data-in (Read) command protocol 8. PIO data-out (Write) command protocol9. DMA data-in (Read) command protocol10. DMA data-out (Write) command protocol11. READ DMA QUEUED command protocol (TCQ)12. WRITE DMA QUEUED command protocol (TCQ)13. FPDMA QUEUED command protocol (NCQ)(SATA II)14. PACKET protocol

Power-on and COMRESET protocol After completing a phy reset sequence, device runs diagnostics and

transmits a FIS with the results.SATA HOST SATA DEVICE

COMRESTBegin phy reset sequence Execute diagnostics

Response FIS (I=0)

Detect phy reset sequence completion

1. Update shadow register(BSY=0)

2.Interrupt host3.Host reads Status register

Update task file register

Detect phy reset sequence completion

ISR . IS_PHY_RDY

Software reset protocol Causes diagnostics to be run, returning the appropriate signature.

SATA HOST SATA DEVICE

Control FISHost writes Control register with

SRST=1Start reset

Response FIS (I=0)

Host writes Control register withSRST=0

1. Update shadow registers(BSY=0)

2. Interrupt host3. Host reads task file registers

Execute diagnostics

Update task fileregisters with signatureGood: Error = 01hBad: Error = not 01h

Control FIS ISR . IS_SW_RST

Device Idle protocol

Power-On

Command FIS

1Receive FIS & Check FIS

2

3

ISR . NON_DATAISR . READ_CMDISR . WRITE_CMD

4

EXECUTE DEVICE DIAGNOSTIC command protocol

EXECUTE DEVICE DIAGNOSTIC(0x90)

1

Send Response FIS (D2H) with good statusA

Send Response FIS (D2H) with bad statusB

Response FIS for EXECUTE DIAGNOSTIC

Status = 50 (DRDY=1,BSY=0,DRQ=0,ERR=0)I = 0 for SW_RST or HW_RST (Power-On)Error = 1 Deivce 0 passed,Device 1 passed or not presentCount = 1 , LBA = 1 General

Send status

ATA ATAPI

Non-data command protocol DEVICE RESET and EXECUTE DEVICE DIAGNOSTIC commands use same

sequence.SATA HOST SATA DEVICE

Command FIS1. Host initializes shadow task

file registers (BSY=1)Parse command

Response FIS

2. Write Command register

1. Update shadow registers(BSY=0)

2. Interrupt host3. Host reads Status register

Process command

Send status

Non-data command protocol

Non-data command 1

ISR . IS_NON_DATA_CMD2 Response FIS (D2H)3

CFA ERASE SECTORSCFA REQUEST EXTENDED ERROR CODECHECK POWER MODEFLUSH CACHEFLUSH CACHE EXTGET MEDIA STATUSIDLEIDLE IMMEDIATEINITIALIZE DEVICE PARAMETERSMEDIA EJECTMEDIA LOCKMEDIA UNLOCKNOPREAD NATIVE MAX ADDRESSREAD NATIVE MAX ADDRESS EXTREAD VERIFY SECTOR(S)READ VERIFY SECTOR(S) EXT

SECURITY ERASE PREPARESECURITY FREEZE LOCKSEEKSET FEATURESSET MAX ADDRESSSET MAX ADDRESS EXTSET MULTIPLE MODESLEEPSMART DISABLE OPERATIONSMART ENABLE/DISABLE AUTOSAVESMART ENABLE OPERATIONSMART EXECUTE OFFLINE IMMEDIATESMART RETURN STATUSSTANDBYSTANDBY IMMEDIATE*DEVICE RESET*EXECUTE DEVICE DIAGNOSTIC

DEVICE RESET command protocol

DEVICE RESET (0x08)1

Status = 50 (DRDY=1,BSY=0,DRQ=0,ERR=0)I = 1 Error = 1 Deivce 0 passed,Device 1 passed or not presentCount = 1 , LBA = EB1401 General

Response FIS (D2H)2

Task file The task file is in the ATA device In parallel ATA, accesses to these registers result in parallel ATA traffic In serial ATA, a Shadow Task file register bank is also managed by the

host to mirror the ATA device’s task file

Serial ATAHost adapter

Shadow Task

file

Device

Task file

PCI Bus

Parallel ATAHost

adapter

PASS

Device

Task file

PCI Bus

Task file Command Register

Data Register

Device Register

Device Control Register

Status Register / Feature Register

Sector Count Register

LBA Register

SStatus,SError,SControl,SActive register

PIO Read command protocolSATA HOST SATA DEVICE


file registers (BSY=1)

PIO Setup FIS ( I=1 ,D=1 , Status=58, E_status=D0 )


Data FIS

(BSY=0,DRQ=1) (BSY=1,DRQ=0)

PIO Setup FIS ( I=1 ,D=1 , Status=58, E_status=50 ) (BSY=0,DRQ=1) (BSY=0,DRQ=

0)

Update task file registers (BSY=0,DRQ=0)

Data FIS (Final)

(BSY=0,DRQ=1)

(BSY=1,DRQ=0)

(BSY=0,DRQ=1)

(BSY=0,DRQ=0)

1. Update shadow registers with PIO Setup “starting” contents

2. Interrupt host 3. Host reads Status register4. Host reads Data register n times5. Update shadow registers with PIO Setup “ending” contents

>8K


2. Interrupt host 3. Host reads Status register4. Host reads Data register last times5. Update shadow registers with PIO Setup “ending” contents

Preparing a DRQ data block

Transmit data

If error has occurred , Send Response FIS

Response FIS ( I=1,Status=51) Interrupt host (BSY=0)

Preparing a DRQ data block

PIO Write command protocol

Response FIS ( I=1 , Status=50?)

Data FIS

1. Update shadow registers Device-to-host register FIS2. Interrupt host (BSY=0)

SATA HOST SATA DEVICE


file registers (BSY=1)

PIO Setup FIS ( I=0 ,D=0 , Status=58, E_status=D0 )

2. Write Command register 3.Wait Device return FIS

(BSY=0,DRQ=1) (BSY=1,DRQ=0)

PIO Setup FIS ( I=1 ,D=0 , Status=58, E_status=D0 ) (BSY=0,DRQ=1) (BSY=1,DRQ=

0)


(BSY=0,DRQ=1)

(BSY=1,DRQ=0)

(BSY=0,DRQ=1)

(BSY=1,DRQ=0)


2. Host reads Status register3. Host Write Data register first times4. Update shadow registers with PIO Setup “ending” contents

>8K


2. Interrupt host 3. Host reads Status register4. Host Write Data register n times5. Update shadow registers with PIO Setup “ending” contents

1st Data FIS

Prepare to receive DRQ data block

Receive data

Send status

Device processing data


DMA Read command protocolSATA HOST SATA DEVICE

Command FIS (READ DMA)

1. Host initializes shadow taskfile registers (BSY=1)

Data FIS


DMA controller receives data

Response FIS (I=1)1. Update shadow registers

2. Interrupt host(DRQ=0, BSY=0)

>8K

Send status


Send data

Prepare data

DMA Write command protocolSATA HOST SATA DEVICE

Command FIS (WRITE DMA)

1. Host initializes shadow taskfile registers (BSY=1)

DMA Activate FIS


1. Activate DMA controller2. DMA controller transfers

write data

Response FIS ( I=1)1. Update shadow registers

2. Interrupt host(DRQ=0, BSY=0)

Data FIS>8K

Send status

Receive data

Prepare to receive

Ready to receive data

Read DMA Queued command protocol

Response FIS (Status=50)

Response FIS ( I=1 , Status=50?) Interrupt host (BSY=0,DRQ=0)

SATA HOST SATA DEVICE1. Host initializes DMA controller

(BSY=1)

( BSY=01 ,REL= Count[2]=1, I/O = Count[1] = 0 , Count[0]=1 , I=1 if release interrupt enabled )

2. Send READ DMA QUEUED Command Count[7:3] = TAG

Response FIS ( Status=58, Count[7:3]=TAG ) (BSY=0,DRQ=1)


(BSY=1)

1. Interrupt host2. Host deactivates 3rd DMA

controller3. Host issue SERVICE command

>8K

Read TAG & backup DMA controller context

Queue command Command FIS (READ DMA QUEUED)

Set Device Bits FIS ( SERV=1 , I=1 )

Device is ready to transfer data & Service request

Command FIS (SERVICE)

Host release bus / command

(BSY=0,DRQ=1)

(BSY=0)

more commads

Data FIS Send dataDMA controller receives

data

( REL= Count[2]=0, I/O = Count[1] = 1 , Count[0]=0)


Response with command that ready to execute


Wait for the CPU to respond to the interrupt Deactivate the 3rd party DMA engine

Send status

last command queued in(BSY=1)

more queued commands not complete

Write DMA Queued command protocol


Response FIS ( I=1 , Status=50?) Interrupt host (BSY=0,DRQ=0)

SATA HOST SATA DEVICE1. Host initializes DMA controller

(BSY=1)

( BSY=01 ,REL= Count[2]=1, I/O = Count[1] = 0 , Count[0]=1 , I=1 if release interrupt enabled )

2. Send READ DMA QUEUED Command Count[7:3] = TAG

Response FIS ( Status=58, Count[7:3]=TAG ) (BSY=0,DRQ=1)


(BSY=1)

1. Interrupt host2. Host deactivates DMA

controller3. Host issue SERVICE command

>8K

Read TAG & restore DMA controller context

Queue command Command FIS (WRITE DMA QUEUED)

Set Device Bits FIS ( SERV=1 , I=1 )

Device is ready to transfer data & Service request

Command FIS (SERVICE)

Host release bus / command

(BSY=0,DRQ=1)

(BSY=0)

more commads

DMA Activate FIS

Receive dataDMA controller sends

data



Response with command that ready to execute

Send status

last command queued in(BSY=1)


NCQ ; TCQ

Use“READ FPDMA QUEUED” , “WRITE FPDMA QUEUED” Command. The SATA host bus adapter(HBA) integrated its own first party DMA engine. Device issues“FPDMA Setup FIS”to HBA to select memory buffer directly without third-

party DMA engine and tells the HBA which command it wants to execute. Device issues“Send Device Bits FIS”to return status of multiple commands completed.

Drastically reduces the number of required CPU interrupts. For NCQ to be enabled, it must be supported and enabled in the SATA host bus adapter. Windows Vista/7 natively supports NCQ , not Windows XP .

SATA NCQ (Native-command queuing) :

ATA TCQ (Tagged-command queuing) : Use“READ DMA QUEUED” , “WRITE DMA QUEUED” Command.

Available in both Parallel and Serial ATA Use ATA host bus adapter's third party DMA engine. It caused high CPU utilization without improving performance enough to make

this worthwhile , because service command and responding to interrupts uses CPU time , CPU utilization rose quickly .

Improve the overall performance of a hard drive device. Device can make its own decisions about how to order the requests. Up to queue 32 commands by using tag. ( IDENTIFY DEVICE word 75)

FPDMA Read command protocol


Interrupt host (BSY=0,DRQ=0)

SATA HOST SATA DEVICE(BSY=0)

( BSY=0 ,DRQ= 0 , I=0 )

Send READ FPDMA QUEUED Command Count[7:3] = NCQ TAG (BSY=1)

Update task file registers (BSY=0)

Select the DMA engine context by TAG

(DMA Buffer ID)Host loads PRD pointer into DMA

engine DMA controller receives data

Command FIS (READ FPDMA QUEUED)

Host sets SActive Register(BSY=0)

more commads

Data FISSend data

DMA Setup FIS

Set Device Bits FIS (BSY=0 , I=1 , SActive )

(DMA Buffer ID= TAG , D=1 , I=0, Transfer count )

this command not complete

Transfer count not exhausted

bit n in SActive field set to one where n = TAG for each command TAG value that has completed

Queue command & store NCQ TAG in SActive

Send statusMultiple commands can be indicated as complete at a time


Update Host copy SActive Register

FPDMA Write command protocol


Interrupt host (BSY=0,DRQ=0)

SATA HOST SATA DEVICE(BSY=0)

( BSY=0 ,DRQ= 0 , I=0 )

Send WRITE FPDMA QUEUED Command Count[7:3] = NCQ TAG (BSY=1)

Update task file registers (BSY=0)

Select the DMA engine context by TAG(DMA Buffer ID)

Host loads PRD pointer into DMA engine

DMA controller sends data

Command FIS (WRITE FPDMA QUEUED)

(BSY=0)

more commads

DMA Activate FIS

Receive data

DMA Setup FIS

Set Device Bits FIS (BSY=0 , I=1 ,SActive)

(DMA Buffer ID= TAG , D=0 , I=0, Auto-Activate=1 ,Transfer count )

this command not complete

Transfer count not exhausted

bit n in SActive field set to one where n = TAG for each command TAG value that has completed

Queue command & store NCQ TAG in SActive

Data FIS if Auto-Activate==0

Send status


Multiple commands can be indicated as complete at a time

Host sets SActive Register

Update Host copy SActive Register

END

2010/01

PIO Read command protocol

PIO READ Command1

Prepare Data Block

2Send PIO Setup FIS to HOST3

Status = 0x58 (DRDY=1,BSY=0,DRQ=1.ERR=0) ,

More Data to transmitA

All Data transmit completed

5

If error has occurred , Send Response FIS (status=0x51)B

4 Send Data FIS to HOST

PIO Write command protocol

PIO Write Command 1

Prepare Data block (Buffer)

2

Send PIO Setup FIS to HOST3

4 Receive Data FIS from HOST

Send Response FIS (status=50 or 51)5

DMA Read command protocol

DMA Write command protocol

Read DMA Queued command protocol

Write DMA Queued command protocol

Power-on and COMRESET protocol

POWER-ON COMRESET

1

Initialize HWExecute diagnostics

3 Send Response FIS (D2H)4

ISR . IS_PHY_RDY2

Software reset protocol

ISR . IS_SW_RST3

Control FIS (SRST=1)

1

Control FIS (SRST=0)

2

Initialize HWExecute diagnostics

4

Send Response FIS (D2H)

5