review sheet for midterm #2

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• Review Sheet for Midterm #2

Brian Bircumshawbrianb@eecs.berkeley.edu

1 Miterm #1 Review

See Table 1 on the following page for a list of the most important equations you should know fromMidterm #1.

2 Large Signal (LS) & Small Signal (SS) Concepts

Most real world circuits are broken up into both a large signal (LS) and a small signal (SS) model.LS models are used to determine the biasing conditions. They include common circuit elements(e.g., transistors, diodes, R, L, C, etc.), as well as constant voltage and current sources. From theLS model, a SS model can be created. This is done by transforming all circuit elements to their SSequivalents (e.g., transistors become voltage controlled current sources; Rs remain the same; Lsoften become open circuits; Cs often become shorts). Constant voltage sources beomce SS groundswhile constant current sources become SS open circuits. If the sources are imperfect, the sourcesresistance must be taken into account. The SS model is actually a linearized model (Taylor Seriesapproximation) of the circuit, linearized about the bias point (also known as the operating point).The SS model is extremely useful in analyzing complex circuits and determining such things asvoltage/current gain, transconductance, transresistance, Rin, and Rout.

The labeling convention used by the book for mixed LS and SS sources is as follows:

vI(t)LS + SS

= VILS

+ vi(t)SS

(1)

where VI is a constant in time. The full, real world circuit can be formed by incorporating all ofthe SS sources into the LS model.

The SS models for both NMOSFETs and PMOSFETs in saturation are shown in Figure 1. Thesmall signal transconductances are found via a Taylor Series approximation of Id:

ids IDSVGS

gm

vgs +IDSVBS

gmb

vbs +IDSVDS gd =

1ro

vds

isd ISDVSG

gm

vsg +ISDVSB

gmb

vsb +ISDVSD gd =

1ro

vsd

(2)

The above definitions for gm, gmb, and ro are valid for all three regions of operation: saturation,triode, and cutoff. In saturation, for given bias condtions, ID = IDS = ISD and Vdsat = Vdsatn =

1

• Description Variable Example

I,R

,V

eloci

ty,D

opin

g

Ohms Law V = IR 1 kMass-Action Law np = n2i 10

20 1/cm3

Drift Velocity vdn =

{nE = n VL E Esatvsatn E Esat

106 cm/s

Drift Current Density Jd = Jdn + Jdp = q (nvn + pvp) 1 A/cm2

Drift Current I = JdA A = widththickness 100 AResistivity = 1q(nn+pp) 100 m cmConductivity = 1 10 S/cmResistance R = LW

t 1 k

Sheet Resistance Rsh =t 5 k/

NM

OSFET

Cutoff Ids = 0 VGS < VTn 0 ATriode Ids = WL kn

[VGS VTn VDS2

]VDS 100 A

VGS > VTn, VDS VGS VTnSaturation Ids = 12

WL kn [VGS VTn]

2 (1 + nVDS) 1 mAVGS > VTn, VDS VGS VTn

Backgate Effect VTn = VT0n + n(2p VBS

2p

)1.5 V

VBS < 0, p < 0, VTn > VT0n

PM

OSFET

Cutoff Isd = 0 VSG < VTp 0 ATriode Isd = WL kn

[VSG + VTp VSD2

]VSD 50 A

VSG > VTp, VSD VSG + VTpSaturation Isd = 12

WL kn [VSG + VTp]

2 (1 + nVSD) 0.5 mAVSG > VTp, VSD VSG + VTp

Backgate Effect VTp = VT0p p(

2n VSB

2n)

1.5 VVSB < 0, n > 0,VTp > VT0p

Mis

c.

Vdsatn , VGS VTn 0.5 VVdsatp , VSG + VTp 0.5 V

Channel Modulation n = 0n L0L 0 = 0.01, L0 = 1m 0.01 1/V mChannel Modulation n = 0n L0L 0 = 0.01, L0 = 1m 0.01 1/V m

Table 1: Table summarizing materials covered up to Midterm #1.

2

• (a) NMOS

(b) PMOS

Figure 1: Full small signal models for the n-channel and p-channel MOSFETs. Ignore the capacitorsfor Midterm #2 (i.e., for Midterm #2, replace the capacitors in the figure above with open circuits).These are figures 4.24 and 4.26 from Howe and Sodini, respectively.

Vdsatp, the small signal transconductances are:

gm 2IDVdsat

2IDknW

L

gmb gm

2VBS 2p

ro =1gd 1

ID

(3)

Note the following:

The equations in (3) are good for both NMOS and PMOS.

The equations in (3) are good for transistors in saturation only. The equations are differentfor the triode region, though the models depicted in Figure 1 are correct for both saturationand triode regions.

3

• Changing ID will change both gm and ro. Increasing W and L by the same factor will changeonly ro. Hence, gm and ro can be changed independently of one another.

If the bulk of the transistor is attached to the source, VBS = VSB = 0 = gmb = 0. If thebulk terminal is not explicitly shown, assume that it is attached to the lowest potential if itis a NMOS, and the highest potential if it is a PMOS.

3 Single Transistor Amplifiers

There are three single transistor amplifiers:

1. Common Source (CS). The source terminal is attached to a constant voltage. It is a goodtransconductance amplifier.

2. Common Gate (CG). The gate terminal is attached to a constant voltage. It is a goodcurrent buffer (output stage for a current amplifier).

3. Common Gate (CD). The drain terminal is attached to a constant voltage. It is a goodvoltage buffer (output stage for a voltage amplifier).

The configuration of each amplifier is depicted in Figure 2. Remember the following:

The input is never at the drain.

The input is at the gate, unless the gate is a SS ground (CG). In this case, the input is atthe source.

The output is never at the gate.

The output is at the drain, unless the drain is a SS ground (CD). In this case, the output isat the source.

3.1 Gain, Rin, and Rout

With amplifiers, we are concerned with the controlled source gain (e.g., Av for a voltage amplifier,Gm for a transconductance amplifier), Rin, and Rout. To determine the controlled source gain, wefirst remove the source and load resistances, RS and RL. Next, we bias the circuit. Finally, wehook up a SS voltage or current source at the input and mearsure the output current or voltage,as illustrated in Figure 3. Mathematically, this is equivalent to:

Av =VOUTVIN

voutvin

Voltage Gain

Ai =IOUTIIN

ioutiin

Current Gain

Gm =IOUTVIN

ioutvin

Transconductance

Rm =VOUTIIN

voutiin

Transresistance

(4)

4

• Figure 2: Single transistor amplifier configurations. This is a figure from the backside cover ofHowe and Sodini.

5

• Figure 3: Method to calculate two-port SS models. For any circuit, to find the equivalent two-portcontrolled source gain (Av, Ai, Gm, and Rm), Rin, or Rout, replace the dark gray boxes in thisfigure with the biased circuit of interest. As directed in the figure, attach the test voltage/currentsource and, if applicable, the load or source resistance (RL and RS). Then, measure the outputcurrent/voltage or test current/voltage indicated in the figure. Use (4) and (5) to calculate thecontrolled source gain, Rin, or Rout. This is figure 8.3 from Howe and Sodini.

6

• Figure 4: The controlled source gain, Rin, and Rout of the three single transistor amplifiers. Thevalues presented are approximations. This is a figure from the backside cover of Howe and Sodini.

Notice that we have used the books labeling convention (1). The values of Av, Ai, Gm, and Rmare most readily obtained via hand analysis of the SS model.

To find Rin, we hook up the load resistance (RL) and bias the circuit. Then, we attach a SStest source (voltage or current) at the input, and measure the current or voltage accross the inputsource. Rout is found in a similar manner. We hook up the source resistance (RS) and bias thecircuit. Then, we attach a SS test source (voltage or current) at the output, and measure thecurrent or voltage accross the output source. Mathematically:

Rin =VINIIN

viniin

Rout =VOUTIOUT

voutiout

(5)

The controlled source gain, Rin, and Rout of the three single transistor amplifiers is recordedin Figure 4. Note that these values are approximations. When in doubt, always perform a SSanalysis.

Also note that these values correspond to 2-port models that take the forms depicted in Figure 5.The 2-port models are all equivalent. That is, using Thevenin and Norton equivalents (Figure 6),any 2-port can be converted into any other 2-port model.

7

• Figure 5: The four possible 2-port models. This is a figure from the backside cover of Howe andSodini.

8

• VT Vo

Req

+

+

Io

VoReq

+

Io

VTReq

IN =

IN Vo

Req

+

+

Io

VoReq

+

Io

INReqVT =

(a) Thevenin to Norton

VT Vo

Req

+

+

Io

VoReq

+

Io

VTReq

IN =

IN Vo

Req

+

+

Io

VoReq

+

Io

INReqVT =

(b) Norton to Thevenin

Figure 6: Procedure for transforming between Thevenin and Norton equivalent circuits.

4 Current Mirrors

A current mirror is a very convenient way of generating a specific current in a circuit. Most singletransistor amplifiers are biased with current sources obtained, in some way or another, from acurrent mirror. An example current mirror is pictured in Figure 7. For the mirror pictured:

VREF = VTn +

IREF(WL

)1

kn2

(6)

IOUT =

(WL

)2(

WL

)1

IREF (7)

Notice that the current mirror structure can also provide a very good voltage reference: VREF .Further, note that for an effective mirror we usually require L1 = L2. An even better mirror is onein which the controlled transistors (like M2 in Figure 7) are all of the same size.1 By shortin

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