MEM1763/1742

SYSTEM IDENTIFICATION AND ESTIMATION

ASSIGNMENT 2

DESIGN PSEUDO RANDOM BINARY SEQUENCE (PRBS) OF 15 STAGES SHIFT REGISTER USING SIMULINK AND HARDWARE

Prepared for:

Lecturer: Assoc. Prof. Dr. Mohd Fua’ad Rahmat

Prepared by:

Name : Nurul Syahirah Binti Khalid

Matrix : ME101156

Name : Masmaria Binti Abd Majid

Matrix : ME081600

The objective of this report is:

1. To design of pseudo random binary sequence (PRBS) of 15 stages shift register using

Simulink and hardware construction.

2. To verify the PRBS output, using hardware construction.

Pseudo Random Binary Sequence (PRBS) generator with a given MLS Using Math Lab

MLS, N=2n -1 = 32767 where n= 15. The orientation of bit on shift register are tabulate in Appendix 1 for only until 40 clock.

Figure 1 : PRBS

SR1

Xor

Output

SR2 SR3 SR4 SR5 SR6 SR7 SR8 SR9 SR10 SR11 SR12 SR13 SR14 SR15

PART A: PRBS using SIMULINK

PRBS signal also simulate in Simulink. In Simulink it constructed based on PRBS equation,

N=2n-1. In our case , n is equal to 15.Therefore,we need to used 15 flip flop in order to make

a shift register. To built shift register we used D flip flop but in Simulink, the limitation of

using D flip flop is it cannot set the initial condition of the flip flop. Therefore JK flip flop are

used to function as a D flip flop to make it as a shift register. Means the JK flip flop are

designed to be a subsystem of D flip flop. In order to make JK flip flop to function as D flip

flop, the input of K are complement of input J. The subsystems of the D flip flop as shown in

Figure 3. The construction of PRBS using subsystem of JK flip flop are shown in Figure

2 .We use output of Q15 as our PRBS output and the input of our shift register is a feedback

from the output Q1 XOR with the ouput of Q15.The results after simulation are shown in

Figure 4

.

Figure 2: PRBS using SIMULINK

Figure 3 : Subsytem of D flip flop

Figure 4: Output of Q15 and Q1 XOR Q15

PART B: Circuit construction using TINA software.

Circuit for PRBS are design using TINA software. The hardware description consists of voltage

regulator, timer, operational amplifier and 8 bit shift register . Voltage regulator (LM7805C) used to

regulate voltage from 9V to 5V to source the circuits and timer NE555 function as a CLK to shift

register. In our case, we use 8-bit serial in shift register (SN74164) . It will shift the output to the next

flip flop to the right. Our input is a feedback from the output of Q1 XOR with output of Q15. The

operational amplifier (LM741) are used to amplifier the signal from the output of the shift register.

PRBS of the signal are measure using oscilloscope, in our case we choose output of Q15 as our PRBS

signal. After simulation the result of PRBS as shown in Figure 6, while circuit construction are shown

in Figure 5.

V1

IN

GN

DOUT

U1

CLR

CLK

A

B

QA

QB

QC

QD

QE

QF

QG

QH

9

8

1

2

3

4

5

6

10

11

12

13

U2

CLR

CLK

A

B

QA

QB

QC

QD

QE

QF

QG

QH

9

8

1

2

3

4

5

6

10

11

12

13

U3

U4

R1

THRES

CONT

TRIG

RESET OUT

DISC

VC

CG

ND

U5

C1 10n

P1 1M

C1 100n

C3 10u

R4 3

6k

R5 1

5K LE

D1

V2

P2

-

+ +

U6

Ch1+ - Ch2+ -

OSC2

R2

Figure 5 : TINA Simulation for PRBS

Figure 6 : Output of PRBS after simulation of TINA

From the results that obtain by using the TINA software, we can say that the waveform is the

same with the waveform by using SIMULINK and same with the theoretical. After that, the

hardware for the circuit is constructing so that the real circuit can be test by using

oscilloscope. Figure 7 show the circuit that constructed. After that, we test the output (PRBS)

by using ociloscopes. Figure 8 show the several output that we get from the circuit( purple

line for clock and green line for PRBS output)

Figure 7: Circuit for PRBS.

Figure 8: Several Waveform for clock and PRBS taken for different value.

Conclusion :

The output of PRBS between Simulink ,TINA software and hardware are the same.We also

construct the PRBS results also in truth table as shown in Appendix 1. In our case, because of

big value of PRBS we just construct the truth table until 40 clock only in order to verify our

simulation result.

CLK SR1 SR2 SR3 SR4 SR5 SR6 SR7 SR8 SR9 SR10 SR11 SR12 SR13 SR14 SR15 1xor51 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 02 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 13 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 04 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 15 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 06 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 17 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 08 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 19 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 010 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 111 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 012 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 113 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 014 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 115 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 016 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 017 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 118 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 119 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 020 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 021 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 122 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 123 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 024 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 025 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 126 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 127 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 028 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 029 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

APPENDIX 1

30 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 131 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 132 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 033 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 134 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 135 1 1 0 1 1 1 0 0 1 1 0 0 1 1 0 136 1 1 1 0 1 1 1 0 0 1 1 0 0 1 1 037 0 1 1 1 0 1 1 1 0 0 1 1 0 0 1 138 1 0 1 1 1 0 1 1 1 0 0 1 1 0 0 139 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 140 1 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0