Review Sheet for Midterm #2

Brian Bircumshawbrianb@eecs.berkeley.edu

1 Miterm #1 Review

See Table 1 on the following page for a list of the most important equations you should know fromMidterm #1.

2 Large Signal (LS) & Small Signal (SS) Concepts

Most real world circuits are broken up into both a large signal (LS) and a small signal (SS) model.LS models are used to determine the biasing conditions. They include common circuit elements(e.g., transistors, diodes, R, L, C, etc.), as well as constant voltage and current sources. From theLS model, a SS model can be created. This is done by transforming all circuit elements to their SSequivalents (e.g., transistors become voltage controlled current sources; R’s remain the same; L’soften become open circuits; C’s often become shorts). Constant voltage sources beomce SS groundswhile constant current sources become SS open circuits. If the sources are imperfect, the sources’resistance must be taken into account. The SS model is actually a linearized model (Taylor Seriesapproximation) of the circuit, linearized about the bias point (also known as the operating point).The SS model is extremely useful in analyzing complex circuits and determining such things asvoltage/current gain, transconductance, transresistance, Rin, and Rout.

The labeling convention used by the book for mixed LS and SS sources is as follows:

vI(t)︸︷︷︸LS + SS

= VI︸︷︷︸LS

+ vi(t)︸︷︷︸SS

(1)

where VI is a constant in time. The full, real world circuit can be formed by incorporating all ofthe SS sources into the LS model.

The SS models for both NMOSFETs and PMOSFETs in saturation are shown in Figure 1. Thesmall signal transconductances are found via a Taylor Series approximation of Id:

ids ≈∂IDS

∂VGS︸ ︷︷ ︸gm

vgs +∂IDS

∂VBS︸ ︷︷ ︸gmb

vbs +∂IDS

∂VDS︸ ︷︷ ︸gd = 1

ro

vds

isd ≈∂ISD

∂VSG︸ ︷︷ ︸gm

vsg +∂ISD

∂VSB︸ ︷︷ ︸gmb

vsb +∂ISD

∂VSD︸ ︷︷ ︸gd = 1

ro

vsd

(2)

The above definitions for gm, gmb, and ro are valid for all three regions of operation: saturation,triode, and cutoff. In saturation, for given bias condtions, ID = IDS = ISD and Vdsat = Vdsatn =

1

Description Variable Example

I,R

,V

eloci

ty,D

opin

g

Ohm’s Law V = IR 1 kΩMass-Action Law np = n2

i 1020 1/cm3

Drift Velocity vdn =

µnE = µn

VL E ≤ Esat

vsatn E ≥ Esat

106 cm/s

Drift Current Density Jd = Jdn + Jdp = q (nvn + pvp) 1 A/cm2

Drift Current I = JdA A = width×thickness 100 µAResistivity ρ = 1

q(nµn+pµp) 100 mΩ− cm

Conductivity σ = 1ρ 10 S/cm

Resistance R = LW

ρt 1 kΩ

Sheet Resistance Rsh = ρt 5 kΩ/

NM

OSFET

Cutoff Ids = 0 VGS < VTn 0 A

Triode Ids = WL kn

[VGS − VTn − VDS

2

]VDS 100 µA

VGS > VTn, VDS ≤ VGS − VTn

Saturation Ids = 12

WL kn [VGS − VTn]2 (1 + λnVDS) 1 mA

VGS > VTn, VDS ≥ VGS − VTn

Backgate Effect VTn = VT0n + γn

(√−2φp − VBS −

√−2φp

)1.5 V

VBS < 0, φp < 0, VTn > VT0n

PM

OSFET

Cutoff Isd = 0 VSG < −VTp 0 A

Triode Isd = WL kn

[VSG + VTp − VSD

2

]VSD 50 µA

VSG > −VTp, VSD ≤ VSG + VTp

Saturation Isd = 12

WL kn [VSG + VTp]

2 (1 + λnVSD) 0.5 mAVSG > −VTp, VSD ≥ VSG + VTp

Backgate Effect VTp = VT0p − γp

(√2φn − VSB −

√2φn

)1.5 V

VSB < 0, φn > 0,−VTp > −VT0p

Mis

c.

Vdsatn , VGS − VTn 0.5 V

Vdsatp , VSG + VTp 0.5 V

Channel Modulation λn = λ0nL0L λ0 = 0.01, L0 = 1µm 0.01 1/V µm

Channel Modulation λn = λ0nL0L λ0 = 0.01, L0 = 1µm 0.01 1/V µm

Table 1: Table summarizing materials covered up to Midterm #1.

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(a) NMOS

(b) PMOS

Figure 1: Full small signal models for the n-channel and p-channel MOSFETs. Ignore the capacitorsfor Midterm #2 (i.e., for Midterm #2, replace the capacitors in the figure above with open circuits).These are figures 4.24 and 4.26 from Howe and Sodini, respectively.

Vdsatp, the small signal transconductances are:

gm ≈2ID

Vdsat≈

√2IDkn

W

L

gmb ≈gmγ

2√−VBS − 2φp

ro =1gd≈ 1

λID

(3)

Note the following:

• The equations in (3) are good for both NMOS and PMOS.

• The equations in (3) are good for transistors in saturation only. The equations are differentfor the triode region, though the models depicted in Figure 1 are correct for both saturationand triode regions.

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• Changing ID will change both gm and ro. Increasing W and L by the same factor will changeonly ro. Hence, gm and ro can be changed independently of one another.

• If the bulk of the transistor is attached to the source, VBS = VSB = 0 =⇒ gmb = 0. If thebulk terminal is not explicitly shown, assume that it is attached to the lowest potential if itis a NMOS, and the highest potential if it is a PMOS.

3 Single Transistor Amplifiers

There are three single transistor amplifiers:

1. Common Source (CS). The source terminal is attached to a constant voltage. It is a goodtransconductance amplifier.

2. Common Gate (CG). The gate terminal is attached to a constant voltage. It is a goodcurrent buffer (output stage for a current amplifier).

3. Common Gate (CD). The drain terminal is attached to a constant voltage. It is a goodvoltage buffer (output stage for a voltage amplifier).

The configuration of each amplifier is depicted in Figure 2. Remember the following:

• The input is never at the drain.

• The input is at the gate, unless the gate is a SS ground (CG). In this case, the input is atthe source.

• The output is never at the gate.

• The output is at the drain, unless the drain is a SS ground (CD). In this case, the output isat the source.

3.1 Gain, Rin, and Rout

With amplifiers, we are concerned with the controlled source gain (e.g., Av for a voltage amplifier,Gm for a transconductance amplifier), Rin, and Rout. To determine the controlled source gain, wefirst remove the source and load resistances, RS and RL. Next, we bias the circuit. Finally, wehook up a SS voltage or current source at the input and mearsure the output current or voltage,as illustrated in Figure 3. Mathematically, this is equivalent to:

Av =∂VOUT

∂VIN≈ vout

vinVoltage Gain

Ai =∂IOUT

∂IIN≈ iout

iinCurrent Gain

Gm =∂IOUT

∂VIN≈ iout

vinTransconductance

Rm =∂VOUT

∂IIN≈ vout

iinTransresistance

(4)

4

Figure 2: Single transistor amplifier configurations. This is a figure from the backside cover ofHowe and Sodini.

5

Figure 3: Method to calculate two-port SS models. For any circuit, to find the equivalent two-portcontrolled source gain (Av, Ai, Gm, and Rm), Rin, or Rout, replace the dark gray boxes in thisfigure with the biased circuit of interest. As directed in the figure, attach the test voltage/currentsource and, if applicable, the load or source resistance (RL and RS). Then, measure the outputcurrent/voltage or test current/voltage indicated in the figure. Use (4) and (5) to calculate thecontrolled source gain, Rin, or Rout. This is figure 8.3 from Howe and Sodini.

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Figure 4: The controlled source gain, Rin, and Rout of the three single transistor amplifiers. Thevalues presented are approximations. This is a figure from the backside cover of Howe and Sodini.

Notice that we have used the book’s labeling convention (1). The values of Av, Ai, Gm, and Rm

are most readily obtained via hand analysis of the SS model.To find Rin, we hook up the load resistance (RL) and bias the circuit. Then, we attach a SS

test source (voltage or current) at the input, and measure the current or voltage accross the inputsource. Rout is found in a similar manner. We hook up the source resistance (RS) and bias thecircuit. Then, we attach a SS test source (voltage or current) at the output, and measure thecurrent or voltage accross the output source. Mathematically:

Rin =∂VIN

∂IIN≈ vin

iin

Rout =∂VOUT

∂IOUT≈ vout

iout

(5)

The controlled source gain, Rin, and Rout of the three single transistor amplifiers is recordedin Figure 4. Note that these values are approximations. When in doubt, always perform a SSanalysis.

Also note that these values correspond to 2-port models that take the forms depicted in Figure 5.The 2-port models are all equivalent. That is, using Thevenin and Norton equivalents (Figure 6),any 2-port can be converted into any other 2-port model.

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Figure 5: The four possible 2-port models. This is a figure from the backside cover of Howe andSodini.

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VT Vo

Req

–+

–

+

Io

VoReq

–

+

Io

VT

ReqIN =

IN Vo

Req

–+

–

+

Io

VoReq

–

+

Io

INReqVT =

(a) Thevenin to Norton

VT Vo

Req

–+

–

+

Io

VoReq

–

+

Io

VT

ReqIN =

IN Vo

Req

–+

–

+

Io

VoReq

–

+

Io

INReqVT =

(b) Norton to Thevenin

Figure 6: Procedure for transforming between Thevenin and Norton equivalent circuits.

4 Current Mirrors

A current mirror is a very convenient way of generating a specific current in a circuit. Most singletransistor amplifiers are biased with current sources obtained, in some way or another, from acurrent mirror. An example current mirror is pictured in Figure 7. For the mirror pictured:

VREF = VTn +

√IREF(WL

)1

kn2

(6)

IOUT =

(WL

)2(

WL

)1

IREF (7)

Notice that the current mirror structure can also provide a very good voltage reference: VREF .Further, note that for an effective mirror we usually require L1 = L2. An even better mirror is onein which the controlled transistors (like M2 in Figure 7) are all of the same size.1 By shorting thedrains of the controlled transistors together, it is possible to get any integer multiple of IREF .

1NOTE: For the exam, it is not required that you know/understand the following footnoted material. Thisinformation is provided for your enlightenment as a circuit designer.

When transistors have the same W/L, and are situated relatively close to one another physically, the transistorsare said to be “well matched.” The ratios of (W/L)’s between well matched transistors will remain constant despitevariations in fabrication.

Due to variations in fabrication and operation, fabricated transistors never have the exact same dimensions asdesigned. Typically, the dimensions of all transistors in a particular area of a chip vary by the same amount. Forexample, if the fabricated dimensions of M1 in Figure 7 are actually W fab

1 = α(W design1 −2εa) and Lfab

1 = β(Ldesign1 −

2εb), then the fabricated dimensions of M2 will vary similarly: W fab2 = α(W design

2 −2εa) and Lfab2 = β(Ldesign

2 −2εb).If our transistors are well matched, then Ldesign

1 = Ldesign2 and W design

1 = W design2 . In this case:

WL

fab

2WL

fab

1

=

WL

design

2WL

design

1

(8)

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Figure 7: Sample current mirror. This is figure 9.27 from Howe and Sodini.

The SS output resistance of the current mirror, roc, looking into the drain of M2, is:

roc = ro2 ≈1

λ2IOUT(9)

5 Voltage Swing

As transistors have scaled down and voltage supplies have dropped, voltage swing has become ofgreater and greater concern. The following steps can help you determine the voltage swing in acircuit.

• Output Swing

1. Examine the LS model.

2. Require all transistors to be in the saturation (high-gain) region.

3. Adjust VOUT above the bias point until a transistor enters the triode or cutoff regions,or until the corresponding VIN goes above its maximum value (often VDD) or below itsminimum value (often VSS).

4. The VOUT determined in the previous step is VOUT,max.

5. Again, examine the LS model and require all transistors to be in the saturation (high-gain) region.

6. Adjust VOUT below the bias point until a transistor enters the triode or cutoff regions,or until the corresponding VIN goes above its maximum value (often VDD) or below itsminimum value (often VSS).

7. The VOUT determined in the previous step is VOUT,min.

8. The output swing is: VOUT,min < VOUT < VOUT,max.

• Input Swing

1. Examine the LS model.

Therefore, the ratio IOUT /IREF will be as designed.

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2. Require all transistors to be in the saturation (high-gain) region.

3. Adjust VIN above the bias point until a transistor enters the triode or cutoff regions, oruntil the corresponding VOUT goes above its maximum value (often VDD) or below itsminimum value (often VSS).

4. The VIN determined in the previous step is VIN,max.

5. Again, examine the LS model and require all transistors to be in the saturation (high-gain) region.

6. Adjust VIN below the bias point until a transistor enters the triode or cutoff regions, oruntil the corresponding VOUT goes above its maximum value (often VDD) or below itsminimum value (often VSS).

7. The VIN determined in the previous step is VIN,min.

8. The output swing is: VIN,min < VIN < VIN,max.

6 Solving Circuit Problems

When dealing with any analog circuits problem we are usually concerned with two things: (1) meet-ing the required specifications, and (2) biasing the circuit properly. Based on the given situation,one of the three general approaches presented in Table 2 on the next page can be used to solve theproblem.

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Situation Goals Approach

GivenCircuit andBias

Find Specs1. Use LS model and bias conditions to determine bias

voltages and currents. Determine W/L of each transis-tor. Assume MOSFETs are in saturation.

2. Check to make sure MOSFETs are in saturation. Ifnot, something may be wrong and you should checkyour work.

3. Determine small signal parameters: gm, ro, and gmb.

4. Determine specs: voltage gain, current gain, Rin, Rout,etc.

GivenCircuit andSpecs

Find Bias1. Use SS model to solve for given specs. Use these equa-

tions to determine bias currents and voltages. AssumeMOSFETs are in saturation.

2. Check to make sure MOSFETs are in saturation. Ifnot, something may be wrong and you should checkyour work.

3. If asked, determine input and output swings, and/orpower consumption.

Given Specs(no Circuit)

CreateDesign 1. Postulate circuit needed.

2. Determine specs from SS model of postulated circuit,assuming MOSFETs are in saturation.

3. Determine required bias conditions based on SS para-meters. If needed, determine input and output swings,and/or power consumption.

4. Check to see if your circuit meets all the specs. If youdo not meet the specs, return to step 1.

5. Check to make sure MOSFETs are in saturation. Ifnot, something may be wrong and you should checkyour work.

Table 2: General circuit problem solving approaches for different situations.

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