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Resonant Boost Converter for Distributed Maximum Power

Point Tracking in Grid-Connected Photovoltaic Systems

by

Gregor Simeonov

A thesis submitted in conformity with the requirementsfor the degree of Masters of Applied Science

Graduate Department of Electrical and Computer Engineering

University of Toronto

Copyright c© 2010 by Gregor Simeonov

Abstract

Resonant Boost Converter for Distributed Maximum Power Point Tracking in

Grid-Connected Photovoltaic Systems

Gregor Simeonov

Masters of Applied Science

Graduate Department of Electrical and Computer Engineering

University of Toronto

2010

This thesis introduces a new photovoltaic (PV) system architecture employing low volt-

age parallel-connected PV panels interfaced to a high voltage regulated DC bus of a

three-phase grid-tied inverter. The concept provides several improvements over existing

technologies in terms of cost, safety, reliability, and modularity. A novel resonant mode

DC-DC boost converter topology is proposed to enable the PV modules to deliver power

to the fixed DC bus. The topology offers high step-up capabilities and a nearly constant

efficiency over a wide operating range. A reduced sensor maximum power point tracking

(MPPT) controller is developed for the converter to maximize energy harvesting of the

PV panels. The reduced sensor algorithm can be generally applied to the class of con-

verters employing pulse frequency modulation control. A ZigBee wireless communication

system is implemented to provide advanced control, monitoring and protection features.

A testbench for a low cost 500 W smart microconverter is designed and implemented,

demonstrating the viability of the system architecture.

ii

Acknowledgements

First and foremost I would like to thank my loving parents Alex and Zdenka for their

support, my brother Andrej for his long-lasting friendship, and my girlfriend Linh for

sticking with me through thick and thin over the last six years.

I would like to extend my gratitude to my supervisor Dr. Peter Lehn for his wis-

dom, patience, and for giving me the opportunity to explore my practical and academic

interests with this work.

I wish to acknowledge and give thanks for the financial support from Hydro One

in the form of the H.W. Price Research Fellowship, and Hatch Limited for the Hatch

Sustainable Energy Research scholarship.

Finally I would like to reflect on my years at the University of Toronto; a journey of

learning, maturing, discovering, achieving, and building friendships and memories that

will last a lifetime.

iii

Contents

1 Introduction 1

1.1 Grid-Connected PV Systems . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Module-Integrated Converters . . . . . . . . . . . . . . . . . . . . 2

1.1.2 Micro-Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1.3 Low Voltage Inverter . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Grid-connected System Description . . . . . . . . . . . . . . . . . . . . . 5

1.2.1 Microconverter Requirements . . . . . . . . . . . . . . . . . . . . 7

1.2.2 Parallel vs. Series Connected Panels . . . . . . . . . . . . . . . . 8

1.3 Overview of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Resonant Boost Converter Analysis 13

2.1 Overview of Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.1 Hard Switched Converters . . . . . . . . . . . . . . . . . . . . . . 13

2.1.2 Resonant Mode Converters . . . . . . . . . . . . . . . . . . . . . . 14

2.2 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.1 Power Stage Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2.2 Power Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2.3 Peak Current and Voltage Analysis . . . . . . . . . . . . . . . . . 22

2.2.4 Voltage and Current Conversion Ratio . . . . . . . . . . . . . . . 24

2.3 Switching Loss and Efficiency Considerations . . . . . . . . . . . . . . . . 24

iv

2.3.1 Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3 Photovoltaic System Design and Implementation 30

3.1 Power Stage Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.1.1 Resonant Frequency, Inductor and Capacitor . . . . . . . . . . . . 31

3.1.2 Semiconductor Devices . . . . . . . . . . . . . . . . . . . . . . . . 33

3.1.3 Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.1.4 Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.1.5 Lossless Snubber . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.1.6 Digital Controller and Gate Drivers . . . . . . . . . . . . . . . . . 37

3.1.7 PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2 PV Emulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.2.1 PV Emulator Implementation . . . . . . . . . . . . . . . . . . . . 40

3.2.2 PV Cell Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.3 Inverter Emulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4 Maximum Power Point Tracking Control System 45

4.1 MPPT Control Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.2 Controller Model and MPPT Algorithm . . . . . . . . . . . . . . . . . . 47

4.3 Converter Control System . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.4 Considerations on Control System Improvements . . . . . . . . . . . . . 52

5 Communication System 54

5.1 Communication System Requirements . . . . . . . . . . . . . . . . . . . . 54

5.1.1 ZigBee Wireless Networks . . . . . . . . . . . . . . . . . . . . . . 56

5.2 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3 PV Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.3.1 Software Description . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.4 Server Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . 62

v

5.5 Future Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6 Experimental Results 67

6.1 Converter Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.1.1 Nominal Operating Conditions . . . . . . . . . . . . . . . . . . . 68

6.1.2 Hold State and Soft Switching Operation . . . . . . . . . . . . . . 69

6.1.3 Input Filter Validation . . . . . . . . . . . . . . . . . . . . . . . . 72

6.2 Converter Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.2.1 Weighted Efficiency Results . . . . . . . . . . . . . . . . . . . . . 74

6.3 MPPT Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.3.1 PV Emulator Parameters . . . . . . . . . . . . . . . . . . . . . . . 78

6.3.2 MPPT Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

7 Conclusion 81

Bibliography 84

A Converter PCB Schematics 87

B Converter PCB Bill of Materials 91

C Communication Module PCB Schematics 93

D Communication Module PCB Bill of Materials 95

E Converter Microcontroller Source Code 97

F PV Emulator Microcontroller Source Code 103

vi

List of Tables

3.1 Resonant boost converter parameters. . . . . . . . . . . . . . . . . . . . . 39

5.1 XBee API commands supported by the communication module. . . . . . 61

6.1 Expected and measured parameters at the nominal operating point. . . . 68

6.2 Recorded efficiency with hold state control mode. . . . . . . . . . . . . . 75

6.3 Weighted efficiency results. . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.4 Emulated PV panel parameters. . . . . . . . . . . . . . . . . . . . . . . . 78

B.1 Converter PCB bill of materials. . . . . . . . . . . . . . . . . . . . . . . . 92

D.1 Communication module PCB bill of materials. . . . . . . . . . . . . . . . 96

vii

List of Figures

1.1 Module integrated converters. . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Micro-inverter module technology. . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Low voltage inverter technology with parallel panel collection. . . . . . . 5

1.4 Proposed system featuring distributed MPPT using DC-DC boost con-

verters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.5 I-V characteristic curves of two panels at different irradiance levels. . . . 8

1.6 P-I curve of panel A and B in series. . . . . . . . . . . . . . . . . . . . . 9

1.7 P-V curve of panel A and B in parallel. . . . . . . . . . . . . . . . . . . . 10

2.1 Frequency response of a series resonant LC circuit. . . . . . . . . . . . . 15

2.2 Proposed resonant boost converter topology. . . . . . . . . . . . . . . . . 16

2.3 Operating states of the resonant boost converter. . . . . . . . . . . . . . 19

2.4 Theoretical waveforms of the resonant boost converter. . . . . . . . . . . 20

2.5 Input current waveform demonstrating approximation of ton. . . . . . . . 22

2.6 Converter waveforms highlighting soft switching elements. . . . . . . . . 26

2.7 Converter with Sr removed, provided control by S1 and S2. . . . . . . . . 27

2.8 Waveforms of converter with classical frequency control. . . . . . . . . . . 28

2.9 Waveforms of converter operating with pulse skip modulation. . . . . . . 29

3.1 Block diagram of PV system components. . . . . . . . . . . . . . . . . . 31

3.2 Resonant boost converter power stage. . . . . . . . . . . . . . . . . . . . 31

viii

3.3 Input capacitor voltage ripple. . . . . . . . . . . . . . . . . . . . . . . . . 34

3.4 Output capacitor circuit and voltage ripple waveform. . . . . . . . . . . . 35

3.5 Parasitic oscillations during the hold state leading to breakdown of Sr. . 37

3.6 Interrupt switch snubber diode implementation. . . . . . . . . . . . . . . 37

3.7 Converter PCB showing A) S1, S2, B) Lr, C) Sr, D) Cin, E) Ds, F) Do, G)

gate drivers, H) communication header, and I) dsPIC33FJ microcontroller. 39

3.8 PV emulator power and control circuit architecture. . . . . . . . . . . . . 41

3.9 PV cell electrical model. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.10 Schematic of high voltage supply used to emulate DC bus of a grid-tied

inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.11 Image of DC supply showing variac and parallel RC load. . . . . . . . . . 44

4.1 P-V characteristic of panel for the P&O algorithm. . . . . . . . . . . . . 46

4.2 Power function vs. switching frequency curve of resonant boost converter. 48

4.3 Reduced sensor hill-climbing MPPT algorithm flow chart. . . . . . . . . . 50

4.4 Block diagram of MPPT control system. . . . . . . . . . . . . . . . . . . 51

5.1 a) Typical ZigBee network and a b) dropped router node. . . . . . . . . . 57

5.2 ZigBee network with only router nodes ensures reliable communication. . 57

5.3 Digi International XBee ZB ZigBee module with wire antenna. . . . . . . 58

5.4 Wireless communication system architecture for distributed microconverters. 59

5.5 Communication module PCB containing XBee modem. . . . . . . . . . . 60

5.6 Control flow of reading XBee API frame. . . . . . . . . . . . . . . . . . . 62

5.7 Control flow of writing XBee API frame. . . . . . . . . . . . . . . . . . . 63

5.8 Network Setup window used to configure coordinator and logging system. 64

5.9 Network Status window used to list and monitor active ZigBee nodes. . . 65

5.10 Monitor Converter tab provides direct access to microconverter parameters. 65

6.1 Resonant tank voltage and current waveforms at rated power. . . . . . . 69

ix

6.2 Measured resonant inductor current and voltage waveforms at fs = 27 kHz. 70

6.3 Measured waveforms of a) FET S1 and b) FET S2 with a hold state. . . 71

6.4 Measured waveforms of the interrupt switch Sr . . . . . . . . . . . . . . . 72

6.5 Measured waveforms of the output diode Do . . . . . . . . . . . . . . . . 73

6.6 Input voltage ripple at a) fs = 40.7 kHz and b) fs = 2.04 kHz. . . . . . 73

6.7 Converter efficiency versus input power. . . . . . . . . . . . . . . . . . . . 76

6.8 Measured (points) and theoretical (curve) I-V characteristics under two

shading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.9 Measured (points) and theoretical (curve) P-V characteristics highlighting

maximum power points. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.10 Waveforms showing converter tracking MPP of two emulated PV profiles. 80

7.1 Cost distribution of microconverter components. . . . . . . . . . . . . . . 83

A.1 Resonant boost converter power stage schematic. . . . . . . . . . . . . . 88

A.2 Gate drivers circuit schematic. . . . . . . . . . . . . . . . . . . . . . . . . 89

A.3 Microcontroller and analog sensors schematic. . . . . . . . . . . . . . . . 90

C.1 Communication module PCB schematic. . . . . . . . . . . . . . . . . . . 94

x

Chapter 1

Introduction

Renewable energy production has been steadily increasing as international goals to re-

duce dependence on fossil fuels have been on the agenda for nations worldwide. Solar

photovoltaic (PV) power systems are becoming a prevalent renewable energy option with

the cost of PV cells decreasing and their solar conversion efficiency increasing. Yearly

growth rates over the last five years were on average more than 40% [1], with a world-

wide production of 7.3 GW in 2009 [2], making photovoltaics one of the fastest growing

industries. The largest PV markets are in Europe, accounting for 77% of the world de-

mand in 2009 [2]. However, recent provincial government programs such as the Feed-In

Tariff program in Ontario, enabled by the Green Energy and Economy Act 2009 [3], have

created a growth opportunity for PV technology in Canada. This thesis will focus on the

development of a novel power electronics interface applicable to a modular grid-connected

photovoltaic system.

1.1 Grid-Connected PV Systems

The first generation of grid-connected PV systems consisted of connecting an array of

PV panels to a central inverter interfaced to the utility grid. Since photovoltaic cells

produce direct current (DC) at very low voltage, solar PV panels would have to be

1

Chapter 1. Introduction 2

wired in series, called strings, to attain a high DC voltage level that is then converted

to AC by an inverter. The power production of the system could then be increased by

connecting multiple strings in parallel. While the configuration is simple, the total energy

harvesting capabilities of the system is poor due to centralized maximum power point

tracking (MPPT) operation of the entire PV array. Since the PV array is susceptible to

varying power production conditions including shading, panel mismatch and degradation

factors, the bus voltage and string currents regulated by the inverter are always sub-

optimal for maximum power production per panel. Recent emerging solutions have been

to subdivide the array to perform MPPT tasks on a per-string or per-panel basis using

a power electronics interface, increasing the energy harvesting of the PV system. This

effectively reduces the number of solar panels required to generate the same amount of

power at the grid.

Many system topologies have been proposed to provide distributed MPPT. However

the delicate balance between energy harvesting gains and total system cost has not been

justified in most cases. On a practical level, the main challenge with a distributed

MPPT converter (microconverter) solution is still the requirement to interface the low-

voltage PV panel to a high voltage DC level for the inverter, meanwhile maintaining high

electrical efficiency. Several new PV system topologies have emerged on the market to

perform this task. The following is a review of their viability in a commercial rooftop or

utility scale PV system.

1.1.1 Module-Integrated Converters

In order to address problems associated with series strings under partial shading, module

integrated converter (MIC) solutions have been introduced, Figure 1.1. These power

optimizing converters interface a PV panel to a series string. By connecting the converters

in series, a high DC voltage VBUS is achieved on the inverter bus, meanwhile providing

MPPT on a per-panel basis. National Semiconductor’s SolarMagic Power Optimizer is an


example of a MIC available on the market, rated for 40 VDC , 350 W panels at the input,

and compatible with 600 VDC and 1000 VDC output bus voltages [4]. Using a three mode

buck-boost converter (buck, boost, and pass-through), a maximum efficiency of 99.5% is

advertised. While the MIC is appealing because it can be mounted with the PV panel,

the topology requires a buck-boost converter and a complicated tri-mode control scheme

to achieve MPPT under all operation conditions [5]. Moreover, the cost/watt of a MIC

system may not be justifiable for a larger scale commerical rooftop system. While the

MIC has more of an application in residential rooftop, inability to ground the PV panels

poses a safety hazard due to high voltages floating across the PV panels and therefore

may not meet certain codes.

PV

MPPT

PV

MPPT

PV

MPPT

Inverter

AC ControlMains 1 or 3 ACφ φ

BUSV

+

−

stringI

Figure 1.1: Module integrated converters.

1.1.2 Micro-Inverters

A micro-inverter integrates the MPP tracker and inverter into a single module, Figure

1.2. It removes panel mismatch losses by performing MPPT and interface to the grid on

a per panel basis. Most micro-inverters consist of a two stage power electronic interface, a

DC-DC converter steps up the low input voltage to a high voltage DC bus, and a DC-AC


inverter stage delivers power to the grid [6]. A commercially available micro-inverter is

offered by Enphase, designed for a panel voltage of 31 - 50 VDC and maximum power

of 240W [7] at a weighted efficiency of 95.5%. Micro-inverter systems benefit from their

modularity, capable of plug-and-play installation by users without much knowledge of

electrical systems. However, they pertain more to residential rooftop installations as the

high cost of power electronics for each micro-inverter would lead to a large cost/watt

in larger scale PV systems. Collecting power on the low-voltage AC interface requires

high current cabling, further increasing the cost of the system. In addition, electrolytic

capacitors are typically required in parallel to the PV panel or on the DC link bus for

decoupling the single-phase power ripple, significantly reducing the lifetime of the device

and increasing maintenance costs.

PV

PV

PV

Mains 1 ACφ

MPPT

MPPT

MPPT

Figure 1.2: Micro-inverter module technology.

1.1.3 Low Voltage Inverter

Another technology that has recently appeared on the market is a low voltage PV inverter

from Sustainable Energy Technologies. The Sunergy [8] PV inverter, like the micro-

inverter, is a two stage converter with a DC-DC boost stage to step-up the low PV

panel voltage and perform MPPT, followed by a single phase DC-AC inverter stage, as


shown in Figure 1.3. However, it significantly reduces the cost/watt of the system by

wiring PV panels in parallel to achieve power production up to 6kW per inverter at a

conversion efficiency of 95.2%. The energy harvesting benefits of using a parallel panel

instead of a series panel architecture is higher energy harvesting, as explained in section

1.2.2. The main drawback to this topology is again the use of electrolytic capacitors for

power decoupling of the single phase power ripple, limiting the lifetime of the converter.

PVV

+

−

PVI

PV PV

MPPT

Inverter

Mains 1φAC Control

PV

Figure 1.3: Low voltage inverter technology with parallel panel collection.

1.2 Grid-connected System Description

This thesis proposes a novel DC-DC microconverter concept applicable to modular, low-

voltage, parallel panel PV systems connected to a three phase grid-tied central inverter.

The system topology, shown in Figure 1.4, combines the cost reduction benefits of larger

central converter solutions, the high energy harvesting benefits of microconverter tech-

nology, and long converter lifetime provided by the elimination of elecrolytics in the

system.

The topology has several advantages over the aforementioned systems. First, the

parallel panel configuration has a higher energy yield than an equivalent series connected

system, as demonstrated in 1.2.2. The topology is simple and modular, allowing power

production to be easily scaled by adding or removing modules connected to the common

DC bus. The modular design eliminates a single point of failure that could potentially


Inverter

AC Control Mains 3φ

PVV

+

−

PVI

MPPT

PV PV

DC/DC Boost

MPPT

PV PV

MPPT

PV PV

BUSV

+

−

BUSI

= 800 V100 V

ac480 V

Figure 1.4: Proposed system featuring distributed MPPT using DC-DC boost converters.

bring down the whole system, a common occurrence in central inverter configurations

where a failed panel requires the system to go offline for repair. The three phase grid

interface also eliminates the need for large capacitors on the DC link, meaning film

capacitors can be used in place of electrolytics, increasing the lifetime of the system. In

addition, the high voltage DC bus reduces cabling costs compared to competing topologies

by collecting power from the panels at lower current. Finally, the grounded low voltage

panels provide increased safety during installation and maintenance, adhering to all North

American codes. For example, the National Electrical Code (NEC) 690 demands that

the PV modules must be system grounded and monitored for ground faults when the

maximum output voltage of module is over 50 volts [9].

The implementation of the described system relies on a power electronic interface to

step-up low voltage (80 - 120 V) produced by the panels to the high voltage DC bus

(800 V). The input voltage range corresponds to the voltages produced by thin film solar


panel technology, and the output voltage is the DC bus of a 480 V three-phase grid-tied

inverter using 1200 V switches. The requirement for a large step-up, high efficiency, DC-

DC power converter created a research opportunity to develop a smart microconverter

design for PV applications.

1.2.1 Microconverter Requirements

Assuming that a classical three phase grid-tied inverter can be used as the DC-AC inter-

face, the requirements for a smart DC-DC microconverter were defined for application in

the proposed PV system.

1. Large voltage step-up: The converter must be capable of high voltage gains (8 -

10) for amplifying the low voltage (80 - 120 V) of the PV panels to the high voltage

DC bus (800 V).

2. High efficiency: The converter must have a high electrical efficiency (95%) over

a wide operating range. Solar PV system efficiency standards emphasize efficiency

at operation as low as 5 - 20% of the nominal power.

3. High reliability: The microconverter must use film capacitor technology.

4. Low cost: This requirement is driven by a low component count for the microcon-

verter power stage and control circuit.

5. MPPT Controller: Analog sensing circuits and a digital controller are required

to perform maximum power point tracking.

6. Communication: A low bit-rate communication system is required for monitoring

and control of the distributed microconverters. A user driven central data collector

should have the ability to monitor power production and issue shut down or start

up commands.


1.2.2 Parallel vs. Series Connected Panels

This section will describe the superior performance of parallel connected versus series

connected solar PV panels. Under varying temperature and solar radiation (irradiance),

PV cells generate varying power Ppv = VpvIpv proportional to the area under their I-V

characteristic curve. Non-uniform irradiance conditions can be due to partial shading or

soiling of the PV panel. Figure 1.5 shown an example of I-V curves for two PV cells, one

at full irradiance (1000W/m2) and one experiencing partial shading resulting in exposure

to a quarter (250 W/m2) of the maximum irradiance. Note that the maximum power

point (MPP) is defined as the operating point on the I-V curve where the maximum

power is produced, PMPP = VMPP IMPP .

PV Current, I

(A)

pv

PV Voltage, V (V)pv

0 10 20 30 40 50 60 70 800

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

2Panel A - 1000 Wm2Panel B - 250 W

m

MPP A

MPP B

MPPA

V

MPPB

V

MPPAI

MPPBI

Figure 1.5: I-V characteristic curves of two panels at different irradiance levels.

In series strings, PV cells share the same current, posing several problems in partial

shading conditions. Figure 1.5 indicates that a change in irradiance produces a large

change in the MPP current IMPP and a small change in the MPP voltage VMPP . Figure

1.6 shows the characteristic power curve of the two PV cells connected in series. At

low current, shaded panel B will drive panel A, resulting in low net power production.


However, operating at a current above the short-circuit current of panel B, ISCB, will

cause the panel’s bypass diode to conduct. This condition results in no power contribution

from panel B, and the net power in the string will be equal to the power produced by

panel A. Moreover, maximum power point trackers may incorrectly identify the optimal

operating point due to multiple peaks in the power profile, requiring more elaborate

algorithms to circumvent this problem.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.50

50

100

150

200

250

300

PV Pow

er, P

(W)

pv

PV Current, I (A)pv


mPanel A+B (series)

SCB

I

Figure 1.6: P-I curve of panel A and B in series.

Parallel connected panels share the same voltage. As Figure 1.5 shows, the MPP

voltages of the non-uniformly shaded panels are close in range, therefore an operating

condition providing close to maximum power contribution from both panels is achievable.

Figure 1.7 indicates that the peak power in parallel connected panels is higher than that

of series panels, where the increased energy yield can be in the range of 5 - 15% [8].

Moreover, multiple peaks in the power profile are eliminated, simplifying the design of

the MPPT algorithm.

In conditions of varying irradiance levels, parallel-connected panels provide superior

energy harvesting over series-connected panels. Classical PV systems were limited by the


PV Power, P

(W)

pv

PV Voltage, V (V)pv

0 10 20 30 40 50 60 70 800

50

100

150

200

250

300


mPanel A B (parallel)

Figure 1.7: P-V curve of panel A and B in parallel.

fact that panels had to be connected in series to get practically usable voltage levels. By

developing new power electronic technologies to eliminate this voltage gap, the benefits

of parallel wired PV panels can be utilized.

1.3 Overview of Thesis

The parallel-panel PV system chosen in this study introduces the main problem of in-

terfacing the low-voltage PV panels to a high voltage DC bus for a three-phase grid-tied

inverter, meanwhile maintaining high electrical efficiency, high reliability, and low cost.

This thesis presents the solution to this problem with the development and implementa-

tion of a smart DC-DC step-up microconverter.

Chapter 2 begins with a review of several hard-switched DC-DC step-up converter

topologies that were studied, and why they were found inadequate for our application. A

novel resonant-mode boost converter topology is then introduced, featuring high voltage

conversion ratios and high efficiency due to the benefits of soft switching. The theoret-

ical operation of the converter is discussed, provided by the converter state equations


and switching waveforms. These equations are then manipulated to develop the design

formulas needed for the practical implementation of the converter.

In Chapter 3 the implementation details of the resonant boost converter prototype

and testbench PV system are discussed. The system contains three main components,

namely a photovoltaic emulator at the input, the resonant converter power stage, and a

high voltage supply at the output to emulate a grid-tied inverter DC bus. The focus in

this section is on the design process of the resonant converter. This includes the selection

of resonant circuit elements, semiconductor switches, input filter, and a snubber circuit.

A printed circuit board containing the converter power stage and a digital microcontroller

is then designed to provide a platform for experimental testing.

Chapter 4 discusses the development of a voltage-sensor based MPPT controller for

the resonant converter. By using a relationship between the converter switching frequency

and the PV panel voltage to calculate power, the requirement for an external current

sensor is eliminated. A classical hill-climbing algorithm using power feedback is then

described, followed by an explanation on how the control system is executed by the

microcontroller.

In Chapter 5, a wireless communication system is designed using a ZigBee interface

to provide control, monitoring and protection features for the distributed microconverter

PV system. The chapter begins with a discussion on which communication technologies

were considered, and why a low cost wireless network was preferred. The architecture of

the communication is the described, followed by the implementation details of a commu-

nication module used to interface the converter to the ZigBee network. A PC interface

was also designed to provide central control and data collection of the PV plant.

Chapter 6 provides the experimental results of the designed system. The analytical

model of the converter developed in Chapter 2 is validated with measured waveforms

and parameters. The open-loop weighted efficiency of the converter is then evaluated,

with notes on how to optimize the converter design even further. Finally, the closed-loop


system is tested with the PV emulator to validate the reduced-sensor MPPT algorithm.

Overall, the results indicate that the low voltage, parallel-panel PV architecture is prac-

tically viable with the smart microconverter technology that was designed.

Chapter 2

Resonant Boost Converter Analysis

In this chapter a novel resonant DC-DC boost converter is proposed for application in

distributed microconverter solar photovoltaic systems. First a review is given to provide

a comparison of the proposed converter with classical boost topologies, followed by a brief

discussion of how the topology was derived. The theoretical operation of the converter is

then described, provided by converter state equations, component waveforms, and design

equations. Finally a discussion is provided on the soft switching benefits and efficiency

advantages of the converter.

2.1 Overview of Technology

2.1.1 Hard Switched Converters

The primary difficulty with the conventional boost converter is the hard switching of

inductive currents which cause stress on the main switch and output diode. As the duty

ratio increases, the switching and copper losses dramatically reduce efficiency of the con-

verter at gains typically larger than 4 [10]. To achieve higher step-up at better efficiency,

a high frequency transformer can be used in a forward or flyback converter configura-

tion. These converters have been especially applied in single-phase grid-connected PV

13

Chapter 2. Resonant Boost Converter Analysis 14

systems [6]. However, the flyback converter suffers from the effects of voltage stress on

the main switch and consequently snubber losses. Both topologies also require special

design considerations of high frequency transformers, leading to increased complexity.

Another class of converters that was considered use switched-capacitor circuits [11] to

achieve a high voltage gain. However, the number of switched capacitors required is di-

rectly proportional to the desired voltage gain. Thus high gains yield a large component

count, increased losses and increased complexity.

2.1.2 Resonant Mode Converters

To reduce the losses associated with hard switching, a converter operating in resonant

mode was desired. By using an LC tank to create oscillatory voltage and current wave-

forms, resonant converters can achieve soft switching characteristics such as zero-voltage

switching (ZVS) and/or zero-current switching (ZCS) of the switches. These character-

istics in turn provide significant switching loss reduction in most semiconductor power

devices.

The proposed converter was derived from a recent class of transformerless step-up

resonant DC-DC converters developed by Dr. Dragan Jovcic [13] that utilize a four-

switch bridge around an LC circuit to achieve high step-up and soft switching. The

converter was appealing for its capability of providing high voltage gains independent

of switch duty ratios, meanwhile having a low component count and a relatively simple

topology. Dr. Jovcic’s converter was intended for megawatt size applications, so the use

of reverse blocking thyristors and a switching frequency in the low kilohertz range resulted

in efficiencies in the 95% range. However, scaling the converter down to a lower wattage

PV microconverter application indicated that the switching frequency would have to be

increased to tens of kilohertz in order to achieve reasonable power density. Consequently,

after replacing the thyristor switches with insulated-gate bipolar transistors (IGBT) and

a series diode combination to achieve higher switching frequency, PSPICE simulations


indicated poor converter efficiency due to switch conduction losses. A modified resonant

boost topology that eliminates the need for reverse blocking switches was investigated.

Similar to the converter of Dr. Jovcic, the studied converter exploits the voltage gain of

a series LC tank circuit to produce a transformerless step-up converter.

2.2 Theory of operation

The fundamental method by which the proposed converter achieves a high voltage gain

is by exploiting the gain characteristics of an excited series LC tank at its resonant

frequency ωr =1√

LrCr, shown in Figure 2.1.

iV( )ω

rLjω

r

1

Cjω oV ( )ω

ωω

o

i

V ( )

V( )

rω ω

+

−

Figure 2.1: Frequency response of a series resonant LC circuit.

The proposed converter topology, Figure 2.2, is a transformerless DC-DC resonant

step-up converter with a common ground. A half bridge input switch is used to excite

the series resonant LrCr circuit and a rectifier to clamp the tank capacitor voltage at

the desired output level, enabling power transfer from a low voltage input source to a

high voltage output circuit. An interrupt switch is introduced in series with the resonant

tank to provide variable frequency control via a near lossless hold state. An energy

pulse is delivered to the load with a magnitude dependent on the input voltage, output

voltage and resonant tank parameters. This pulse is transmitted during a fixed interval

(constant “on” time), thus by using the interrupt switch to create a variable length hold

state (variable “off” time), the average power delivered can be controlled. The common

ground feature is important in PV applications where it may be necessary to ground the


PV panel to meet safety requirements.

S

S

rL

rC

rS

oD

iV

oC

oV

Lri

oi

Crv

Sri

Sv

rD

oR

Si

Si

Dov

Srv

+

−

Sv

+

−

+

−

+

−

+ −

+

−

Figure 2.2: Proposed resonant boost converter topology.

2.2.1 Power Stage Analysis

In this section the steady state equations of the converter in Figure 2.2 are derived.

Before proceeding with the analysis, several assumptions are made:

1. All semiconductor and passive components are ideal and lossless.

2. The capacitor Co is sufficiently large to assume a fixed DC output voltage Vo.

3. The converter is operating with a gain greater than one, Vo > Vi.

The converter switching states and waveforms are depicted in Figure 2.3 and Figure 2.4

respectively. The circuit has four states, where switches S1 and Sr are gated complement

to switch S2. The time-domain state equations were derived using the aid of Laplace

transforms.

State 1 [0, t1]: The initial inductor current iLr(0) = 0 and capacitor voltage coming

out of the hold state is vCr(0) = −Vo. The switches S1 and Sr are gated on, and a

step input Viu(t) is applied to the resonant tank. The step input causes iLr and vCr


to build sinusoidally at the resonant frequency described by the following equations.

ωr =1√LrCr

(2.1)

vCr(t) = Vi − (Vo + Vi)cos(ωrt) (2.2)

iLr(t) =(Vi + Vo)sin(ωrt)

Zr

where Zr =

√

Lr

Cr

(2.3)

State 2 [t1, t2]: When Cr is charged to the output voltage vCr(t1) = Vo , the output

diode Do becomes forward biased. Assuming the forward voltage drop of Do is neg-

ligible, vCr is clamped to Vo and the switch Sr naturally stops conducting current.

The stored energy in the resonant inductor Lr is then delivered to the output as a

triangular current pulse. The time t2 indicates the duration that the switch S1 is

gated “on”, drawing power from the input source. This period is constant during

steady-state, and is defined as the constant “on” time ton.

vCr(t) = Vo (2.4)

iLr(t) =Vi − Vo

Lr

t + iLr(t1) = io(t) (2.5)

State 3 [t2, t3]: At t2 the resonant inductor current discharges to zero. At this instant

S2 is gated “on” while S1 and Sr are turned “off”, and Do becomes reverse biased.

The tank current iLr now oscillates in the negative direction, discharging Cr via

the freewheeling diode Dr described by the state equations below. This state resets

the resonant capacitor voltage back to −Vo before entering the hold state.

vCr(t) = Vocos(ωrt) (2.6)


iLr(t) = −Vosin(ωrt)

Zr

(2.7)

State 4 [t3, Ts]: As the negative half cycle of iLr oscillates to zero, the freewheeling

diode Dr turns off and becomes reverse biased. Switch S2 is still gated on, however

no current flows in the resonant tank and the converter enters a hold state. In

effect, the resonant tank switch Sr blocks the high voltage stored in the tank capac-

itor. The switching period Ts controls the length of the hold state Ts − t3, thus the

average power delivered is controlled by varying the switching frequency fs = 1Ts.

Evaluating equations (2.6) and (2.7) at t = t3 indicate the capacitor voltage during

the hold state is indeed −Vo and satisfies the initial condition of State 1.

iLr(t3) = −Vosin(ωrt3)

Zr

= 0 ⇒ t3 =π

ωr

vCr(t3) = vCr(π/ωr) = Vocos(π) = −Vo

2.2.2 Power Equation

The converter waveforms demonstrate that energy transfer occurs only during two states

of the converter. In State 1 the low voltage input source transfers energy into the

resonant circuit, while in State 2 a current pulse is delivered to the high voltage output

circuit. To derive a steady-state model of the converter, the energy transfer in these two

states was analyzed. The input energy drawn in one switching cycle is given by:

Ei = Vi

∫ t1

t0

iS1(t)dt+ Vi

∫ t2

t1

io(t)dt (2.8)

In State 1, the resonant capacitor has the same current as the input. Substituting the

input current with the resonant capacitor current during State 1 and evaluating the left


0 1State 1 [t , t ]

rL

rC

rS

iV

S

rL

rC o

DiV

oV

S

rL

rC

rD

rS

S

rL

rC

oC

oR

1 2State 2 [t , t ]

2 3State 3 [t , t ] 3State 4 [t , T ]s

oV

+

−

oV

Figure 2.3: Operating states of the resonant boost converter.


Sv

Sv

Srv

Crv

Lri

oi

Dov

Si

iV

iV

oV-

Lpki

- oV

t t t sT

Si

r

αω

oV

oV

Sri t

ont

Figure 2.4: Theoretical waveforms of the resonant boost converter.


term in (2.8) we obtain:

iS1(t) = iCr(t) = Cr

∂vCr

∂tt0 ≤ t ≤ t1 (2.9)

Ei = Vi

∫ Vo

−Vo

∂vCr + Vi

∫ t2

t1

io(t)dt

= 2CrViVo + ViIoTs (2.10)

Based on assumption 1, the output energy can be equated to the input energy over one

switching period.

Eo = Vo

∫ t2

t1

io(t)dt = VoIoTs (2.11)

Ei = 2CrViVo + ViIoTs = VoIoTs (2.12)

Solving for Io in (2.12) and multiplying by the output voltage results in the converter

power equation:

Po = Pi = VoIo =2CrViV

2o

Vo − Vi

fs (2.13)

Equation (2.13) indicates that the tank capacitor Cr and switching frequency fs deter-

mine the power transferring capabilities of the converter. The maximum power transfer

occurs when the switching frequency is set to operate the tank current iLr at the border

of discontinuous conduction mode. From the waveforms in Figure 2.4, this condition is

satisfied when the switching period Ts = t3. The period t3 is the sum of the constant “on”

time and half the period of the resonant cycle. Therefore the maximum power transfer

occurs at:

Pi,max =2CrViV

2o

Vo − Vi

· 1t3

t3 = ton +π

ωr

(2.14)

The parameter ton can be calculated by evaluating the state equations (2.3) and (2.5)

at the initial and final conditions. However, these equations rely on the knowledge of


parameters Lr and Cr which must be determined during the design of the converter. In

section 3.1.1 the maximum power equation of the converter is used as the primary design

formula for determining Cr and Lr. Therefore, the exact value of ton cannot be calculated

a priori.

To simplify the design of the converter, the maximum power can be calculated by

approximating ton to be equal to half the resonant period, πωr. For large step-up ratios,

Vo ≫ Vi, the shape of the input current iS1 is approximately sinusoidal with a frequency

near the resonant frequency ωr. Figure 2.5 shows the actual input current iS1, and a

sinusoidal pulse i′S1 with frequency ωr.

Si

ont

sT

′Si

t

πωr

t

Figure 2.5: Input current waveform demonstrating approximation of ton.

By setting ton ≈ πωr, the maximum power of the converter can then be approximated

as:

Pi,max ≈ 2CrViV2o

Vo − Vi

· ωr

2π(2.15)

2.2.3 Peak Current and Voltage Analysis

The peak inductor current is an important parameter for rating the switches S1, S2,

Sr, and the resonant inductor Lr. Equation (2.2) is evaluated at the boundary between


State 1 and State 2 to determine the conduction angle α = ωrt1

vCr(α) = Vi − (Vo + Vi)cos(α) = Vo

cos(α) =Vi − Vo

Vo + Vi

α = cos−1

(

Vi − Vo

Vo + Vi

)

(2.16)

Based on assumption 3, the converter is operating in boost mode, thus the conduction

angle must satisfy:

π

2< α < π for Vo > Vi (2.17)

Using the conduction angle and (2.3), the peak inductor current equation is then:

iLpk =(Vi + Vo)

Zr

(2.18)

Figure 2.4 indicates that the peak voltage across the resonant capacitor Cr occurs

during State 2 and State 4, during which the magnitude of the capacitor voltage is

equal to the output voltage. The forward blocking voltage of the interrupt switch Sr

should also be rated for this value, since the peak capacitor voltage vCpk is applied across

the switch during the hold state.

vCpk = V o (2.19)

In addition, the output diode Do must be capable of reverse blocking twice the magnitude

of the output voltage.


2.2.4 Voltage and Current Conversion Ratio

If a parallel RC load is used, the converter voltage conversion ratio can be determined

from (2.13).

Po =V 2o

Ro

=2CrViV

2o

Vo − Vi

fs

⇒ Vo

Vi

= 1 + 2CrRofs (2.20)

Similarly, using (2.20) and assumption 1, the current conversion ratio was determined.

Vo

Vi

=IiIo

⇒ IoIi

= (1 + 2CrRofs)−1 (2.21)

The converter conversion equations are provided for completeness. Note that the conver-

sion ratios are a function of the load, due to the discontinuous conduction mode (DCM)

operation of the converter. In our system the output voltage is assumed to be fixed, so

the power equation (2.13) is used instead of (2.20) and (2.21) during the design process.

2.3 Switching Loss and Efficiency Considerations

The proposed topology benefits from several soft switching features at both the input and

output stages of the converter. Practical semiconductor switches exhibit non-ideal voltage

and current trajectories due to non-zero turn-on and turn-off periods. This effect results

in switching losses, and can severely impact converter efficiency and performance. By

commutating the switches during either (or both) zero current (ZC) or zero voltage (ZV)

conditions, this switching loss can be significantly reduced. In addition, P-N junction

diodes suffer from the reverse recovery loss phenomena, where current flows in the reverse

direction for a finite time (reverse recovery time trr) during turn-off as the injected


minority carries in the junction are swept out and recombined. During this transient the

diode begins to reverse block voltage while the reverse current is still flowing, and the

device absorbs a significant amount of energy. By reducing the amount of voltage the

diode must block during trr, the reverse recovery losses can be minimized.

The oscillatory nature of the resonant currents and voltages in the proposed converter

are used to create ZCS and ZVS conditions. Figure 2.6 highlights the soft switching

features of the converter. The input bridge MOSFETs S1 and S2 are gated at the

zero-current crossings of the resonant tank current, leading to reduced switching losses.

Meanwhile, the output diode Do has a ZV turn-on and ZV during turn-off, reducing

losses associated with reverse recovery. The freewheeling diode Dr features ZC and ZV

turn-on. The interrupt IGBT Sr turns on at ZC and turns off at ZC/ZV, since the

tail current recombines with the tank inductor current during State 2. Overall, soft

switching features of the resonant boost converter are imperative for achieving stringent

efficiency requirements for PV applications.

The advantage of using a hold state for variable power transfer is apparent in the

expected constant efficiency of the converter over a wide operating range. Before entering

the lossless hold state, the converter draws and delivers a fixed energy pulse at the

resonant frequency. Therefore the energy lost due to conduction losses, semiconductor

switching losses and inductor core losses are all constant regardless of the length of the

switching period Ts. The total total energy loss can then be lumped into a single term

Eloss, and the average power loss in the converter can be expressed as follows:

Ploss = Elossfs (2.22)

Recall from (2.13) that the power drawn by the converter is directly proportional to

the switching frequency. Examining the equation below indicates the efficiency of the

converter is expected to be constant regardless of the amount of power transferred, as-


Sv

Sv

Srv

oi

Dov

Si

t t t sT

Si

ZV turn-off

ZC turn-off

ZC turn-off

ZV turn-on

ZC turn-on

ZC turn-on

t

Sri t

rS ZC turn-on

rD ZV,ZC turn-on

Figure 2.6: Converter waveforms highlighting soft switching elements.


suming that the input and output voltages are constant. This is an obvious advantage in

comparison with classical hard-switched converters, where conduction energy losses vary

with the duty cycle and hence are not constant over the operating range of the converter.

η =Pi − Ploss

Pi

=

2CrViV2o

Vo−Vifs − Elossfs

2CrViV 2o

Vo−Vifs

=

2CrViV2o

Vo−Vi−Eloss

2CrViV 2o

Vo−Vi

(2.23)

2.3.1 Control Modes

Several different control schemes to operate the resonant converter were considered. At

full power, the inductor current iLr is continuous and the hold state time Ts − t3 is

zero. In effect the interrupt switch Sr and diode Dr conduct during the full switching

period Ts, generating significant conduction losses without any gains in functionality.

The efficiency of the converter could be improved by eliminating the interrupt switch

element, Figure 2.7, and using the duty cycle of the half bridge switches S1 and S2 to

control the converter.

S

S

rL

rC

oD

iV

oC

oV

Lri o

i

Crv

Sv

oR

Si

Si

+

−

Sv

+

−

+

−

+

−

Figure 2.7: Converter with Sr removed, provided control by S1 and S2.


Two alternative control modes employing switches S1 and S2 were investigated. In

the first mode, classical frequency control is used by gating S1 and S2 at 50% duty cycle

near the resonant frequency of the tank, ωr = 2πfr. By varying the switching frequency

above (or below) the resonant frequency, the peak tank current iLpk and output power

can be controlled. Maximum power transfer occurs when the switching frequency is

tuned to match the resonant frequency, fs = fr, and the current waveforms iS1 and

iS2 are sinusoidal. The converter waveforms at full power are the same as the proposed

converter operating with a hold state time of zero. Figure 2.8 demonstrates the converter

waveforms when the bridge is switched above the resonant frequency, fs > fr. When

operating at lower power, the efficiency of the converter is expected to reduce dramatically

since the currents in switches S1 and S2 are no longer sinusoidal and generate significant

switching losses.

Sv

Sv

iV

iV

sT

Si

Si

Lri

Crv

oi

sT

t

s rf >f

Lpki

oV

Figure 2.8: Waveforms of converter with classical frequency control.


The second mode uses pulse skip modulation (PSM) to vary the switching period Ts,

effectively controlling the average power transfer in the converter. The gating of S1 and

S2 is similar to that of the hold state control mode, except that the length of the switching

period Ts must be an integer multiple of the resonant period Tr, as shown in Figure 2.9.

Instead of entering a lossless hold state, the tank current iLr oscillates freely during the

variable length period Ts. The benefit of PSM over the the aforementioned frequency

control method is that soft switching of S1 and S2 is preserved over the entire operating

range of the converter. While the peak power efficiency is expected to be higher, the

freewheeling tank current generates significant conduction and inductor core losses for

low duty ratios, making PSM operation unfavourable at low power compared to the hold

state control mode. The two alternative control modes are evaluated experimentally in

Chapter 6, indicating that the hold state method is advantageous at low power and yields

a higher weighted efficiency of the converter.

Sv

Sv

iV

Si

Si

Lri

Crv

oi

iV

sT =

rnT

t

oV

=n

rT

Figure 2.9: Waveforms of converter operating with pulse skip modulation.

Chapter 3

Photovoltaic System Design and

Implementation

In this chapter, the design and implementation of the PV system testbench is described.

The system has three main components, namely the PV emulator, the resonant boost

converter power stage, and the inverter DC bus emulator, as shown in Figure 3.1.

First the resonant boost converter design methodology is discussed. This includes the

selection of key components in the power stage based on the design equations developed

in Chapter 2. The selection of an input capacitor to meet PV panel ripple voltage specifi-

cations is described, followed by the implementation of a lossless snubber circuit required

for the practical application of the resonant tank interrupt switch. A printed circuit

board (PCB) containing the power stage and digital controller for the boost converter is

also described.

At the input, a programmable PV emulator was designed and implemented to test

the maximum power point tracking controller of the resonant converter. The chapter

concludes with the design of a high voltage DC source at the output to emulate a grid-

tied inverter DC bus.

30

Chapter 3. Photovoltaic System Design and Implementation 31

PVi

PVv+

−

PV

Emulator

DC-DC

oV

+

−

oi

Inverter

EmulatorPower

Stagepvi

pvv

Figure 3.1: Block diagram of PV system components.

3.1 Power Stage Design

The resonant boost converter power stage was designed to process 500 watts of power

with a nominal input voltage of 100 V , average input current of 5 A, and an output

voltage of 800 V corresponding to the DC bus voltage required for a three-phase grid-

tied inverter. The power stage components, shown in Figure 3.2 were selected to meet

these requirements.

S

S

rL

rC

rS

oD

oV

Lri

rD

Si

inC

iV

+

−

oi

Figure 3.2: Resonant boost converter power stage.

3.1.1 Resonant Frequency, Inductor and Capacitor

The resonant boost converter is a frequency controlled device, therefore setting the max-

imum switching frequency of the converter inherently sets the resonant frequency of the


LrCr tank. A nominal switching frequency of 40 kHz was selected based on considera-

tions for the inductor size and switching frequency limitations of the IGBT. Setting the

nominal switching frequency to equal the resonant frequency, fs,nom = ωr

2π, the maximum

power equation (2.15) was then used to determine the size of Cr.

Pnom ≈ 2CrViV2o

Vo − Vi

fs,nom

⇒ Cr =Pnom(Vo − Vi)

2ViV 2o fs,nom

= 68nF (3.1)

The resonant frequency and the calculated Cr were then used determine the value of the

resonant inductor Lr:

ωr = 2πfs,nom =1√LrCr

⇒ Lr =1

(2πfs,nom)2Cr

= 233µH (3.2)

Using equation (2.18), the peak resonant tank current was determined.

iLpk =(Vi + Vo)

Zr

= 15.38Apk (3.3)

Sourcing a suitable resonant capacitor was difficult due to the high frequency and

high voltage/current requirements. Film capacitors designed for high voltage snubber

applications appeared to have parameters compatible with our application. The resonant

capacitor chosen was a 68 nF power film capacitor from Cornell Dubilier, featuring 8

mΩ ESR, 630 V rms voltage and 16.6 Apk current carrying capabilities at frequencies up

to 100 kHz. Since the operating frequency of the converter is 40kHz and below, the

current stress on the resonant capacitor is well below rated.

The sourcing of a resonant inductor proved to be an even more difficult task. In

conventional DC-DC converters the inductor is rated based on maximum DC currents


and tolerable ripple current. However, due to high frequency AC currents, resonant

inductor design requires special attention to core losses and copper winding parasitics

such as the skin effect [14]. A custom inductor was ordered from E Craftsman for our

application, having an inductance of 230 µH , a current rating of 15 Apk at 60 kHz, and

a target power loss (core plus copper) of 15 watts. Unfortunately the ordered inductor

did not perform as well as expected, so a 224 µH inductor was built in the lab using a

Ferroxcube ferrite core for excellent high frequency performance, and 13 AWG litz wire

to reduce copper losses associated with skin effect.

3.1.2 Semiconductor Devices

The main criteria for selecting the semiconductor switches was low conduction loss to

meet the high efficiency requirements for PV applications. Low-cost International Rec-

tifier MOSFETs were selected for the input switches S1 and S2, having a breakdown

voltage of 200 V , continuous drain current of 26 A and on resistance of 21 mΩ. The

body diodes of the MOSFETs are required to carry the rated current in case of non-ideal

switching conditions and commutation of the inductor current.

The interrupt switch Sr is a 1200 V , 30 A IGBT from International Rectifier, featuring

high switching speeds and low conduction losses. The external freewheeling diode Dr is

a 1200 V , 20 A rectifier from Vishay, optimized for short recovery time and low forward

voltage drop.

The output diode Do must be rated for twice the output voltage, 2Vo = 1600 V .

Moreover, the average rectified current of the device has to be overrated to account

for large peak currents during turn-on. Two low-cost 1000 V , 8 A diodes from ON

Semiconductor were connected in series to give an effective blocking voltage of 2000 V

and a total forward voltage drop of 3 V . Since the series diodes block zero voltage during

turn-off, reverse recovery losses were expected to be minimal.


3.1.3 Input Capacitor

A first order input filter was designed to reduce the voltage ripple at the PV panel

terminals to 2% of the nominal maximum power point voltage VMPP = 100 V . Figure

3.3 shows the PV panel voltage in steady-state, where vi is the input voltage of the

converter, Cin is the input capacitor, and Ipv is the DC panel current. Recall that the

converter draws energy from the input during a constant period ton, approximately equal

to half the resonant period 2πωr. During the following states, Cin is charged linearly by the

PV panel current for a duration equal to the switching period Ts minus ton.

tont

iv

sT

i∆v

pv

in

I

C

Figure 3.3: Input capacitor voltage ripple.

The equation describing the relationship between the voltage ripple ∆vi and the

capacitance Cin can be expressed as:

Cin =Ipv(Ts − ton)

2∆vi(3.4)

The largest voltage ripple occurs at the lowest switching frequency. Given that the

converter is designed to provide MPP tracking down to 5% of the rated power (25 W ),

the lowest switching frequency is therefore 5% of the nominal fs (2 kHz). Assuming

that the MPP voltage of the panel is still around the nominal value of 100 V , the panel

current Ipv at 5% was calculated to be 0.25 A. Using equation (3.4), the input capacitor


was designed to reduce the voltage ripple below 4 Vpk−pk.

Cin ≥0.25A ·

(

12kHz

− 12

140kHz

)

4Vpk−pk

= 30.47µF (3.5)

A 39 µF , 100 V capacitor with an ESR of 2 mΩ was selected from AVX Corporation’s

line of film capacitors for input DC filtering.

3.1.4 Output Capacitor

An output capacitor, shown in Figure 3.4, is required to filter the high frequency switching

current at the output of the converter. While the output dynamics of the converter were

not analyzed in this project due to the constant voltage source assumption of the DC

bus emulator, the design process for an output capacitor is included in this section for

completeness.

tov

sT

o∆v

oi

oI

oC

oi

+

−

ov

∆t

t

t

Figure 3.4: Output capacitor circuit and voltage ripple waveform.

In steady-state, an energy pulse is delivered to the output stage of the converter over

a constant period, equal to the period of State 2, ∆t2 = t2 − t1. The period ∆t2 can be


determined by evaluating the state equation (2.5) at t2.

iLr(t2) =Vi − Vo

Lr

∆t2 + iLr(t1) = 0

⇒ ∆t2 = −Vi − Vo

Lr

iLr(t1) (3.6)

The initial current in (3.6) is calculated by evaluating the inductor current equation (2.3)

in State 1 at the conduction angle α. From (2.3) we have:

iLr(t1) = iLr(α) =(Vi + Vo)sin(α)

Zr

where α = cos−1

(

Vi − Vo

Vo + Vi

)

(3.7)

The output capacitor Co depends on the desired voltage ripple ∆vo, the length of the

switching period Ts, ∆t2, and the loading current Io.

Co ≥Io (Ts −∆t2)

2∆vi(3.8)

Similarly to the input capacitor, the output voltage ripple is greatest at the lowest oper-

ating frequency of the converter. Co should therefore be calculated with Io and Ts values

corresponding to the converter operating point at the lightest load.

3.1.5 Lossless Snubber

During the initial implementation of the converter, we found that parasitic capacitances

Cp from the freewheeling diode Dr and interrupt switch Sr were causing high frequency

current oscillations during the hold state, as shown in Figure 3.5. This current ripple

induced high voltage oscillations across the IGBT, causing voltage breakdown of the

switch and ultimately failure of the hold state control mode.

To mitigate this problem a lossless snubber was introduced in the circuit to clamp

the voltage at the IGBT during the hold state, avoiding over-voltage breakdown of the

switch. A snubber diode, Ds shown in Figure 3.6, rated for a reverse blocking voltage


S

rLrC

rSpCrD

ip

Srv

+

−

Srv

pi

Lri

Lpki

t

t

tsT

oV

t

Figure 3.5: Parasitic oscillations during the hold state leading to breakdown of Sr.

larger than Vo (800 V ) was used, clamping the IGBT voltage directly to the output

supply voltage during the hold state.

S

S

rL

rC

rS

oD

oV

rD

inC

iV

+

−S

D

Snubber

Figure 3.6: Interrupt switch snubber diode implementation.

3.1.6 Digital Controller and Gate Drivers

A programmable microcontroller from the Microchip dsPIC33FJ [16] series was selected

to perform the converter control and communication tasks. The 40 MIPS digital signal

controller is a powerful but cost-effective 16-bit microcontroller featuring several ADC

ports and an advanced PWM module capable of variable frequency control. Microchip’s

MPLAB integrated development environment (IDE) with a free C compiler was used for


software development. In addition, a PICKit2 in-circuit serial programmer and debugger

provided a simple and efficient debugging process. The C code for the microcontroller

main program is provided in Appendix E. The implementation details of the MPPT con-

trol and communication systems are discussed in Chapter 4 and Chapter 5, respectively.

A digital PWM module of the dsPIC33FJ is responsible for generating the gating

signals for the switches S1, S2 and Sr. As mentioned previously, switch S1 is gated

complementary to S2, but in phase with Sr. Two gate driver chips were required to drive

the three switches. A standard low-side FET driver was used to drive the IGBT Sr as

the emitter terminal is referenced to ground. The half bridge circuit uses a high/low side

driver employing a bootstrap circuit to drive the high side MOSFET S1. The switching

nature of the converter indicates that the high-side switch will never have a duty cycle

of more than 50%, which occurs at the maximum switching frequency. Consequently, no

additional percautions needed to be taken to ensure the bootstrap capacitor circuit is

charged over the entire operating range of the converter. An external 3.3 V supply was

used to power the microcontroller, and a 10 V supply for powering the gate drivers. A

final design would include on-board supplies to power the logic and gate drivers.

3.1.7 PCB Design

A printed circuit board was designed to integrate the resonant boost converter power

stage, microcontroller and gate drivers circuits into one platform. A compact design was

used for the prototype, shown in Figure 3.7, to increase power density of the circuit as

well as to minimize trace lengths and associated parasitics. A schematic of the PCB

is provided in Appendix A, and a bill of materials in Appendix B. The resonant boost

converter parameters were recalculated based on the actual values of the sourced Lr and

Cr, and a summary of the power stage parameters is provided in Table 3.1.


Converter Parameter Value

Rated Power (Pnom) 506 WNominal input voltage (Vi) 100 VNominal output voltage (Vo) 800 VNominal switching frequency (fs,nom) 40.7 kHzResonant capacitor (Cr) 68 nF/630 Vrms

Resonant inductor (Lr) 224 µH/16 Apk

Input capacitor (Cin) 39 µF/100 VMOSFET (S1, S2) 200 V /26 AIGBT Sr 1200 V/30 AFreewheeling diode Dr 1200 V /20 AOutput diode Do 2 series 1000 V /8 ASnubber diode Ds 1000 V /8 A

Table 3.1: Resonant boost converter parameters.

A

B

C

D

F

G

I

E

H

Figure 3.7: Converter PCB showing A) S1, S2, B) Lr, C) Sr, D) Cin, E) Ds, F) Do, G)gate drivers, H) communication header, and I) dsPIC33FJ microcontroller.


3.2 PV Emulator Design

The input of the PV system testbench consists of a PV emulator switch-mode power

supply that has a programmable output current and voltage profile to emulate the I-V

characteristics of a PV panel. The PV emulator was a low cost solution to test and

validate the MPPT controller developed in Chapter 4.

Several PV simulator technologies were reviewed to get an understanding of potential

power stage and control elements to be implemented. In [17], a buck-boost converter

is operated with current control when the panel voltage Vpv < VMPP , and with voltage

control when Vpv > VMPP . While this dual control mode provides superior stability,

the converter and controller design were too complicated for the purpose of this project.

In [18], a DC-DC chopper using voltage regulation simulates a PV characteristic by

measuring the load resistance and then calculating the desired voltage reference. A

similar concept was used for the PV emulator implementation, although the design was

further simplified using a more embedded architecture.

3.2.1 PV Emulator Implementation

The PV emulator is a DC-DC one-quadrant chopper using inductor current-mode control.

The converter circuit, shown in Figure 3.8, is switched at a frequency of 100 kHz and

has a large 20 A, 5 mH inductor operated in continuous conduction mode (CCM). CCM

operation is ensured given the large inductor size, and assuming that the converter will

not be operated under very light loads. The input MOSFET Q is rated for 200 V /17 A,

while the freewheeling Silicon Carbide diode D is rated for 10 A and has negligible reverse

recovery losses. A 150 V DC supply is used to power the circuit, thus the converter is

theoretically capable of outputting to a voltage range of 0 to 150 VDC.

The I-V curve generator and converter controller are implemented entirely on a Mi-

crochip dsPIC33FJ microcontroller. Up to two PV profiles can be programmed in the


DC150 V

5 mHQ

D

iPV

PVv

+

−

ADC

LUT

[ ]PVv n

pvi

pvv

[ ]PVi n

[ ]refi n+

−Σ

[ ]e nK

DPWM

[ ]d n

dsPIC33F Digital Controller

Figure 3.8: PV emulator power and control circuit architecture.

microcontroller provided that the I-V characteristics have a maximum short circuit circuit

Isc = 6.37 A and an open circuit voltage Voc = 123 V . When the microcontroller is pow-

ered on, two I-V curve look-up-tables (LUT) are generated based on user-programmed

PV panel parameters and the PV model described in the following section.

Every sampling interval, the microcontroller senses the output panel voltage vpv and

generates a current reference iref from the I-V curve LUT. A proportional digital current

controller is then responsible for regulating the output current ipv to follow iref . This

control mode works well in the constant current region of an I-V curve, where a PV

panel behaves like a constant current source. It was found that in some cases the current

controller would become unstable as the operating point on the I-V curve approaches the

open-circuit voltage. In the future, this could be mitigated by implementing a voltage

controller in the region to the right of the maximum power point vpv > VMPP . Although

conversion efficiency was not a priority in the PV emulator design, a peak efficiency of

98.5% was recorded at 50% duty cycle with a 500 W load. The PV emulator worked

sufficiently well, and provided a low cost platform for testing the MPPT control system.


3.2.2 PV Cell Model

sR 0=

shR → ∞ pv

V

+

−

pvI

Figure 3.9: PV cell electrical model.

The PV emulator generates the I-V curves using an algorithm sourced from [15],

based on the PV circuit model depicted in Figure 3.9. Assuming an ideal cell, the series

resistance Rs and shunt resistance Rsh are neglected in the I-V curve calculations. Given

the sensed panel voltage Vpv, the panel current is then calculated as follows:

Ipv = Isc

[

1− C1

(

eVpv

C2Voc − 1

)]

(3.9)

Where

C1 =

(

1− Imp

Isc

)

· e−Vmp

C2Voc (3.10)

and

C2 =

Vmp

Voc− 1

ln(

1− Imp

Isc

) (3.11)

The parameters Voc, Isc, Vmp, and Imp are user-inputted parameters that define the PV

panel open circuit voltage, short circuit current, maximum power voltage, and maximum

power current, respectively. The PV cell’s dependence on temperature and irradiance

level was also added to the model, provided by the additional inputs of the panel cur-

rent temperature coefficient α, and voltage temperature coefficient β. The algorithm

describing the complete model can be found in the PV emulator source code, Appendix

F.


3.3 Inverter Emulator Design

To emulate a DC bus regulated by a three-phase grid-tied voltage-source converter, a

high voltage DC supply was designed and built in the lab that functioned as the load of

the resonant boost converter. The 800 V variable DC power supply was implemented

using a 110 Vrms AC line input, followed by a variable autotransformer (variac) to step

up the voltage to 575 Vrms, and a full bridge rectifier followed by a DC filter. The circuit,

shown in Figure 3.10, has a 1.1 kΩ passive load and is capable of supplying 580 W of

power at 800 VDC . A 3.2 mF capacitor bank is used to provide power decoupling and

filtering of the 60 Hz rectified sinusoidal voltage. The 120 Hz voltage ripple on the bus

is 3 Vpk−pk at maximum power, sufficiently small to assume a stiff DC voltage.

Full BridgeRectifier

DCC

oV

+

−

oi

1 : 1

rms110 : 575 V DC1000 V

30Ω

3.2 mF

4.3 kVA av10 A

oR

1.1 kΩ

ac110 V

Variac

DC+800 V

Figure 3.10: Schematic of high voltage supply used to emulate DC bus of a grid-tiedinverter.

The resonant boost converter outputs to the same load as the high voltage DC supply.

The variac, pictured in Figure 3.11, is then used to adjust the desired bus voltage.


Figure 3.11: Image of DC supply showing variac and parallel RC load.

Chapter 4

Maximum Power Point Tracking

Control System

In this chapter a novel reduced sensor maximum power point tracking (MPPT) controller

is developed for the resonant boost converter. A brief discussion on MPPT algorithms is

first provided, leading to the motivation for the proposed algorithm. The theory for the

reduced sensor algorithm is then derived, followed by a description of the control system

implementation.

4.1 MPPT Control Strategy

Under varying irradiance and cell temperature levels, the maximum power point (MPP)

and corresponding operate voltage of a PV cell continuously changes. Consequently, au-

tonomous tracking of the MPP is essential to any PV power system to provide maximum

energy harvesting at all times. In the proposed PV system, maximum energy harvesting

of the PV plant is provided by sub-dividing the plant into smaller, parallel-connected

PV arrays, and providing local MPPT of each array via the resonant boost converter

interface. Many MPPT algorithms have been proposed, varying in complexity, accuracy,

convergence speed and cost. A good summary of offline and online MPPT methods is

45

Chapter 4. Maximum Power Point Tracking Control System 46

provided in [19].

The most widely applied algorithms are the hill-climbing and perturb and observe

(P&O) methods. Both methods involve the perturbation of either the duty ratio (hill-

climbing) or the input voltage reference (P&O) of the power converter and measuring

the change in power due to the perturbation. Figure 4.1 shows the P-V characteristic

of a PV panel and how the P&O algorithm adjust the operating point on the curve. A

voltage increment ∆V (decrement) to the left of the maximum power point voltage VMPP

results in an increase (decrease) in the power produced by the PV panel. Therefore if the

algorithm determines that the perturbation has resulted in a positive (negative) change

in power ∆P , the following perturbation is maintained (reversed), until the maximum

power point PMPP has been reached.

PPV

VPV

MPP

V

MPPP

V+V

∆

V-V

∆V

P

P+ P∆

P- P∆

Figure 4.1: P-V characteristic of panel for the P&O algorithm.

Hill-climbing and P&O methods rely on power feedback, requiring both a voltage and

a current sensor to measure the DC power generated by the PV panel. By eliminating the

DC current sensor element, the system cost can be significantly reduced and reliability

increased. A voltage-sensing based MPPT algorithm was proposed in [20]. By defining


an objective function P ∗pv ∝ Vpvf(D), where D is the duty cycle of a buck or boost

converter, the MPP can be identified since the maxima of Ppv and P ∗pv coincide. Since

the duty cycle D is an internal control parameter, only a low-cost input voltage sensor

is required to implement the controller. The principle of relating the PV power to a

function dependent on converter control parameters was applied in the development of

the MPPT controller for the resonant boost converter.

4.2 Controller Model and MPPT Algorithm

The proposed MPPT algorithm relates the power generated by the PV panel to a function

of the converter input voltage Vi and the switching frequency fs. Since fs is a control

parameter set internally by the microcontroller, the MPP tracking system effectively

requires only one external sensor to operate.

The DC power generated by a PV source is given by:

Ppv = VpvIpv (4.1)

From energy conservation, the average input power of the resonant boost converter can

be equated to the PV power.

Ppv = Pi =2CrViV

2o

Vo − Vi

fs (4.2)

Where Vi = Vpv is the voltage at the input of the converter and therefore the PV panel

terminal voltage. If the DC bus voltage is regulated, the output voltage Vo is assumed

to be constant. Under dynamic conditions, the power equation (4.2) then becomes a

function of the panel voltage and the switching frequency.

Ppv = f(vpv)f(fs) (4.3)


By defining the power function Pm that is directly proportional to Ppv, the MPP can

be dynamically tracked by maximizing the vpv and fs relationship using a MPPT power

feedback algorithm of choice.

Pm =Ppv

2CrV 2o

=vpv

Vo − vpvfs (4.4)

Note that equation (4.3) describes a general relationship between panel power and con-

verter switching frequency, while (4.4) explicitly applies to the resonant boost converter.

The reduced sensor MPPT methodology described above can be extended to the class of

pulse frequency modulation (PFM) mode converters, as long as the converter power can

be expressed as a function of the switching period.

Figure 4.2 shows the Pm-fs relationship of the resonant boost converter supplied by

a PV panel. The graph indicates a characteristic similar to the P-V curve shown in

Figure 4.1, meaning classical hill-climbing techniques can be applied to track the MPP.

Moreover, the maxima occurs when the slope of the curve is zero ∂Pm

∂fs= 0, a condition

that the algorithm can utilize to identify when the MPP has been reached.

mNormalized P

Switching Frequency, f (kHz)s

0 5 10 15 20 25 30 35 40 450

0.2

0.4

0.6

0.8

1

1.2

∂ = ∂ MPP 0m

s

P

f

Figure 4.2: Power function vs. switching frequency curve of resonant boost converter.


The hill-climbing algorithm developed aims to maximize equation (4.4) by perturbing

the converter switching frequency by a fixed step size ∆F to locate the MPP. This process

is summarized by the flow chart in Figure 4.3. Each sampling interval n, the PV panel

voltage vpv and the switching frequency fs are read. The power function Pm is then

calculated and compared with the previous value. If the previous step has resulted in an

increase in Pm, the same perturbation is applied in the following interval. However, if

the previous step has resulted in a decrease in Pm, the step direction is reversed. Finally,

if Pm is equal to the previous value, the converter is operating at the MPP and therefore

no perturbation should be applied.

4.3 Converter Control System

The MPPT control system is implemented using various peripherals of the dsPIC33FJ

digital microcontroller. A block diagram of the system is shown in Figure 4.4. The only

components external to the microcontroller are the switch gate drivers and the voltage

sensor conditioning circuit.

The advanced high-speed PWM module PWM1 on board the dsPIC33FJ is used

to generate complementary logic-level gating signals via the PWM1H and PWM1L

output pins. A key feature of the PWM1 module is its capability of variable frequency

operation by adjusting the PWM and duty cycle periods via the PTPER and MDC

special function registers. The variable length hold state used to control the resonant

boost converter is achieved by dynamically changing the value of PTPER in software. As

previously discussed, the “on” time ton of the high side switch S1 and interrupt switch Sr

is constant for nominal operating conditions. Consequently the MDC register contains a

fixed value reflecting the period ton.

Panel voltage sensing is achieved by using a voltage divider circuit followed by a low-

pass filter capacitor to reduce switching noise feeding the microcontroller. The 10-bit


Interrupt

Measure: [ ]pvV n

Read : [ ]sf n

[ ][ ] [ ]

[ ]

pvm s

o pv

V nP n f n

V V n= ⋅

−

= −[ ] [ 1]m mP n P n

−[ ] [ 1]m mP n P n>

∆ = 0F∆ = −∆F F∆ = ∆F F

+ = + ∆[ 1] [ ]s sf n f n F

− =[ 1] [ ]m mP n P n

yes

no

yes

no

Return

Figure 4.3: Reduced sensor hill-climbing MPPT algorithm flow chart.


sensV [ ]pvV n

[ ]sf n

[ 1]sf n +MPPTf Limiters

minF

maxF

PWM1 Module

PWM1H PWM1LPTPER

Controller

dsPIC33FJ Digital Controller

SrSS

PVV

[ 1]sT n +1x

ADC0

Figure 4.4: Block diagram of MPPT control system.

ADC0 digital-to-analog converter module digitizes the sensed voltage Vsens and generates

an interrupt in phase with the PWM1 switching period when a conversion is complete.

Additional noise filtering is provided by averaging and bit shifting several measured values

before being sent to the MPP tracker for computation.

The ADC0 Interrupt Service Routine provides an interrupt-driven control flow

for the MPP tracker. The program initializes the PWM1 module to operate at the

nominal switching frequency of the converter (fs,nom = 40.7 kHz). Using 16-bit fixed

point computations, the power function Pm is calculated, where Vpv[n] is the sensed

voltage, fs[n] is calculated from the PWM period register PTPER, and the constant

Vo is set to the DC bus voltage (800 V ). A fixed frequency step ∆F is then applied

to the converter via the PTPER register, and the new period is automatically latched

to the output pins PWM1H and PWM1L by the microcontroller. To avoid overflow of

the PTPER register and operation above the resonant frequency, a frequency limiter is

implemented before the value of PTPER is updated. The MPP tracker then enters the

control loop described by the algorithm in Figure 4.3.


4.4 Considerations on Control System Improvements

While hill-climbing is attractive for its simplicity, it suffers from several inherent draw-

backs. The most predominant issues include oscillations about the MPP during steady

state, and the tendency for the algorithm to drift away from the MPP under rapidly

changing atmospheric conditions. Solutions to these problems have been addressed in

literature, most involving modifications to the hill-climbing algorithm to improve the

steady state and transient responses. Although these issues were not mitigated in this

project, several solutions were studied and found applicable to the designed MPPT con-

trol system.

A bottleneck of hill-climbing is the heuristic tuning of the perturbation step size

parameter. The step size sets the tradeoff between the steady-state and the dynamic

performance of the MPP tracker. A small step size reduces steady state oscillations, but

slows down the dynamic response of the system. Meanwhile, a large step size improves

convergence speed, but results in large oscillations about the MPP leading to lower

efficiency of the system. This problem has been addressed with the implementation

of adaptive hill-climbing methods that use variable step sizes [21]. The adaptive hill-

climbing algorithm dynamically reduces the step size as the operating point approaches

the MPP, maintaining good transient performance and reducing steady state oscillations.

Additional modifications to the algorithm have provided solutions to minimize the

susceptibility of the MPPT to drift in rapidly changing atmospheric conditions. The

reason for this phenomenon is that the MPPT controller cannot distinguish whether

a change in power is the result of the perturbation, or a a variation in the irradiance.

Incremental conductance methods are primarily used to mitigate this problem, and could

potentially be adapted to the resonant converter control model described above. In [22],

a classical hill-climbing algorithm is used in conjunction with a three point weighted

comparison to measure the power level at three different intervals before deciding on the

direction of the perturbation step.


Although the MPPT controller implemented for this project uses a fixed step size

and is expected to suffer from the aforementioned drawbacks, various solutions were

investigated and found applicable without the need to re-design the architecture of the

control system.

Chapter 5

Communication System

The shift from centralized to distributed MPPT technology has introduced the possibility

of providing advanced PV plant safety and diagnostic features by integrating a low-cost,

low bit-rate communication network with the distributed DC-DC microconverters. This

chapter focuses on the design and implementation of a modular ZigBee wireless commu-

nication system used to interface the resonant boost converter to a central PC control

and monitoring program. A brief survey of possible communication system options is

given, followed by the motivation for using a wireless ZigBee solution. The architecture

of the proposed communication system is described, followed by the implementation de-

tails of a microconverter communication module, as well as a Windows based graphical

user interface used for managing and collecting data from the network. While the top

level functions are minimal, the implemented communication system provides a good

framework for expanding the features to meet the requirements of a full scale distributed

MPPT PV system.

5.1 Communication System Requirements

The three main considerations for selecting a communication system were cost, modu-

larity, and complexity. The desired physical and networking layers of the system were

54

Chapter 5. Communication System 55

investigated first. Several wired solution were considered, including RS-485 and the Dig-

ital Addressable Lighting Interface (DALI) used for communication in lighting control

systems. While both protocols use a minimal number of wires for the interface, three

wires for RS-485 and two wires for DALI, the cost and complexity of adding additional

wiring to a large scale commercial rooftop or utility PV system could not be justified.

Moreover, modularity may become an issue when expanding the size and communication

distance of the network, requiring signal repeaters or other hardware to ensure reliable

communication.

Power-line communication (PLC) was considered as a potentially viable option be-

cause it eliminates the need for additional wires by coupling the communication signals

to the high voltage DC bus cables. PLC is used in distributed MPPT technologies avail-

able on the market, including the Enphase microinverter [7] that transmits power data

over the single phase AC bus in residential applications. Reference [23] also describes

the integration of PLC with module integrated converters. Several PLC transceiver

ICs are available on the market, including the STMicroelectronics ST7538Q and Maxim

MAX2990. Initially, these were attractive solutions as they provide all the signal pro-

cessing overhead for the PLC interface, eliminating the need to design a complex analog

transceiver circuit. However, both chips required a fairly large external component count

to implement the power line coupling circuit, making PLC comparable to wireless in

terms of cost. In addition, signal integrity was a concern due to the expected noisy DC

bus.

A wireless solution for the communication system became advantageous to overcome

the issues of modularity and installation complexity. A low cost, low data rate and low

power, wireless digital communication system was sought after. A broad family of low

power digital radios were found that use a physical layer based on the IEEE 802.15.4 wire-

less standard for low bit-rate wireless networks. Several companies provide proprietary

network protocol stacks in addition to the radio modules, enabling simple integration


of wireless communication into existing systems. Examples include Microchip’s MiWi

protocol and Texas Instrument’s SimpliciTI stack. The industry standardized ZigBee

protocol [24] was found most appealing due to the availability of many compatible prod-

ucts on the market, supported by a variety of vendors. The ZigBee plug-and-play mesh

networking features made it the preferred solution for designing a simple and modular

communication system for a distributed microconverter PV system.

5.1.1 ZigBee Wireless Networks

This section will briefly discuss the basic operating principles of a ZigBee personal area

network (PAN). ZigBee applications operate on the 2.4 GHz ISM band, conforming to

IEEE 802.15.4 specifications, at a data rate of 250 kbps (kilo-bits per second). The media

access control (MAC) and network layers are included in the stack, so data transmission

between neighbouring devices as well as message routing over multiple devices (“multi-

hops”) are supported. Reference [24] provides a comprehensive description of the ZigBee

protocol and stack layers.

There are three possible device types in a ZigBee network: coordinator (C), router

(R) and end device (E). A ZigBee network requires a coordinator to start and man-

age the ZigBee network, while the number of routers and end devices is defined by the

number of desired nodes in the network, the physical distance between them, and power

consumption considerations. Once a personal area network (PAN) is established by the

coordinator, routers and end devices are capable of joining and transmitting/receiving

data to/from any node within the network. However, routers have the additional capa-

bility of routing a message from a transmitting node that is out of range of the receiving

node. Due to the additional features, routers usually consume more power than end

devices.

Figure 5.1a shows a typical ZigBee network including the coordinator, routers and

end devices. The end device on the left depends on a router to communicate to the


C R

E

E R R

EE

E

C R

E

E R R

EE

E

a) b)

Figure 5.1: a) Typical ZigBee network and a b) dropped router node.

coordinator and other nodes in the network. If the router drops out of the network, the

end device has no means of accessing the PAN set up by the coordinator and will also

leave the network, Figure 5.1b.

R C RR R

R

RR

R

Figure 5.2: ZigBee network with only router nodes ensures reliable communication.

With a communication system powered by PV panel modules, nodes may be drop-

ping on and off the network due to varying atmospheric conditions. The reliability of the

ZigBee network can be improved by configuring each node in the network to be a router.

Consequently, when an intermediate node drops from the network, an alternate route

will be formed by the remaining nodes such that they have access to the PAN, as demon-

strated in Figure 5.2. ZigBee’s self-healing, mesh network and multi-hop operation are

powerful features that provide the modularity and reliability required for a distributed

microconverter communication system.


5.2 System Architecture

The implemented communication system uses a wireless ZigBee and several wired commu-

nication protocols to allow control and monitoring of individual microconverters (nodes)

by a a host PC (server). To reduce the cost of the communication system, a commu-

nication module PCB was designed to interface the ZigBee network to multiple DC-DC

microconverters using a single ZigBee modem. For the prototype system only a single

converter was tested, therefore the following discussion will focus on the operation of a

single converter per communication module.

The ZigBee modem used for our system is Digi International’s XBee ZB module [25],

pictured in Figure 5.3, an embedded device that implements the 2.4 GHz RF modem,

antenna, and the entire ZigBee protocol stack. Access to the XBee module is provided by

an application programming interface (API) implemented over a simple universal asyn-

chronous receiver/transmitter (UART) logic-level serial interface. By eliminating the

need to program and implement the ZigBee stack, the XBee module was an ideal choice

for rapid development of the communication system. The device features a communica-

tion range of 120 metres in an open environment, is FCC and CE approved, and draws

about 100 mW of power during continuous operation.

Figure 5.3: Digi International XBee ZB ZigBee module with wire antenna.

The proposed architecture of the communication system is shown in Figure 5.4. Each

communication module contains a XBee modem configured as a ZigBee router device. A


microcontroller is used to control the data flow between the XBee modem and the DC-DC

converter MPPT controller via a three-wire inter-integrated circuit (I2C) serial interface.

The ZigBee network coordinator is mains powered and would be packaged with the central

inverter. The PC interface consists of a ZigBee to RS-232 gateway, and a graphical user

interface (GUI) was designed to provide access and management of the wireless network.

Several basic control and monitoring features were implemented, including monitoring of

microconverter input power production, gating control, and emergency plant shut down.

An important feature left for future implementation is fault and failure detection at the

microconverter level. This feature would allow the PV plant operator to diagnose and

isolate faults in the PV system, for example a PV panel short to ground, enabling rapid

system maintenance.

φMains 3 AC

BUSV

+

−

BUSI

MPPT

PV PV

2I C

µC

Comm. Module

XBee(R)

PVV

+

−

PVI

MPPT

PV PV

Microconverter

2I C

µC

Comm. Module

XBee(R)

XBee

(C)

AC Control

ZigBee

Gateway

Inverter

PC Server

RS-232

Figure 5.4: Wireless communication system architecture for distributed microconverters.

5.3 PV Communication Module

The PV communication module, Figure 5.5, is an embedded system containing a Mi-

crochip dsPIC33FJ microcontroller, XBee ZigBee module, and a IDC cable connector


for interfacing the I2C serial line to the converter. The microcontroller software, pro-

grammed in C, controls the data flow between the converter MPPT controller and the

ZigBee network. The PCB schematic and bill of materials of the communication module

can be found in Appendix C and Appendix D, respectively.

Figure 5.5: Communication module PCB containing XBee modem.

Assuming that the ZigBee coordinator has initialized the network, the XBee module

locates the coordinator on a pre-specified PAN ID upon power-up. The PAN ID is

programmed onto the XBee device using Digi International’s X-CTU software. Once

joined, the ZigBee node is assigned a dynamic 16-bit network address. This address

is stored and tracked by the PC server software, and is used for direct addressing of

active nodes in the network. The address of the coordinator is static (0x0000), thus

the communication module always transmits to a fixed address and presently does not

require any additional housekeeping of network addresses.

Two transmission types are available, unicast and broadcast. Unicast transmissions

use direct addressing between ZigBee nodes and comprise the majority of messages sent

between the PC server and the microconverters, for example to monitor the input voltage

and current sensors of the converter. Broadcast transmissions are used when a message

needs to be received by all nodes in the network. In the implemented system, a broadcast

transmission is used only when a plant shut down command is administered by the server.


5.3.1 Software Description

The dsPIC33FJ microcontroller uses the XBee API over the UART peripheral to packe-

tize and transmit data in the ZigBee network. The program is structured around reading

and writing API frames that ultimately contain data to be exchanged with the DC-DC

converter over the I2C bus. While the XBee API supports a handful of commands, only

the ZigBee Receive Packet and Transmit Request commands were implemented. The

supported API command ID’s are shown in Table 5.1, and complete details of the API

can be found in the XBee Manual [25].

API Frame Name UART Data Direction cmdID

ZigBee Receive Packet XBee to dsPIC33FJ 0x90ZigBee Transmit Request dsPIC33FJ to Xbee 0x10

Table 5.1: XBee API commands supported by the communication module.

The control flow of an API read is shown in Figure 5.6. The UART receive (RX)

and transmit (TX) functions are both interrupt driven. Incoming data from the XBee

is stored in a receive buffer. The main loop of the program continuously reads this

buffer and tries to parse a valid API frame. When a ZigBee Receive Packet is parsed,

the data payload contains the message sent from the server, including the requested

microconverter I2C address and a command register. This data is then passed to an I2C

state machine and is transmitted to the converter at the specified address. The current

implementation supports two commands, a gating control command, and a request data

command.

An API write function is called when data has been received over the I2C from the

converter and is ready to be sent to the server. The main program loop waits for a

transmit request flag to be set by the I2C state machine, after which a ZigBee Transmit

Request API frame is assembled and transferred to the UART TX buffer, as shown in

Figure 5.7. When the TX buffer is filled, the UART TX interrupt service routine is called

and the data is transferred to the XBee module to be sent over the ZigBee network. This


Read UART

RX Buffer

Main Loop

API Message

Found?

No

Yes

cmdID = 0x90?Remove Frame from

UART RX Buffer

No

Process Frame

and Call I2C SM

Yes

Figure 5.6: Control flow of reading XBee API frame.

data contains the requested data by the server, for example converter gating status and

sensor values.

The current implementation of the communication module has a simplified command

data structure to provide control and monitoring of the resonant boost converter over

the ZigBee network. While the top level features are minimal, the designed platform is

easily expandable to provide additional commands required in a practical PV system.

5.4 Server Graphical User Interface

The PC interface of the communication system consists of a XBee coordinator module

connected to a Microsoft Windows based PC via a RS-232 COM port. A GUI was

developed using Visual Basic 6.0 to provide a user-controlled interface for forming and

managing the ZigBee network, as well as issuing commands and logging retrieved data

from the microconverter. Communication with the XBee coordinator is implemented

using the XBee API, similarly to the dsPIC33FJ program on the communication mod-


Main Loop

I2C

Transmit Request

= True?

No

Assemble API Frame

cmdID = 0x10

Yes

Send Frame to

UART TX Buffer

Figure 5.7: Control flow of writing XBee API frame.

ule. Therefore, this section will focus more on the features of the GUI, and not on the

implementation details.

The GUI contains four tabulated windows providing various functions. The Net-

work Setup window, pictured in Figure 5.8, is used to manage the XBee coordinator

parameters, initialize the ZigBee network, and configure the data logging system. Upon

powering and connecting the XBee module to the PC, the Scan Network command

button initializes and scans available nodes in the network through the ZigBee coordina-

tor. The Log Settings frame is used to configure the destination of the log file, as well

to adjust the period (in seconds) the program uses to automatically requests data from

the microconverters. When the logging system is enabled, the GUI requests converter

gating status, input voltage, and input current sensor data from all the ZigBee nodes in

the network, and stores the retrieved data in a comma separated value (CSV) file.

The Network Status window, Figure 5.9, provides a real time display of the active

ZigBee nodes in the network. The GUI uses an internal data structure to keep track

of the status each node in the network. This information includes the XBee node serial

number, network address, and node identifier. In the event that a node drops out of the

network, for example if a communication module needs to power down due to shading,


Figure 5.8: Network Setup window used to configure coordinator and logging system.

the GUI will flag the device as unavailable, and will remove it from the data logger.

Using the unique serial number of each XBee module, the GUI can dynamically track

which nodes have been newly discovered, or which ones have re-joined the network.

Selecting the Monitor Converter tab provides a method of manually reading and

writing to a specific microconverter. Figure 5.10 demonstrates a user selecting to turn

“gating on” of converter 0 at ZigBee node 1. The ZigBee node number corresponds

to the node identifier in the Network Status window. In the bottom field, the user

can also send a data request command to immediately display sensor values of the se-

lected converter. The sensor values are then used to calculate the input power of the

microconverter.

The final window features an Emergency Shut Down command that sends a broad-

cast message to the ZigBee network, issuing a command to disable gating of all the con-

verters in the system. This is the first of potentially many advanced maintenance and

safety features made possible by a PV communication system.


Figure 5.9: Network Status window used to list and monitor active ZigBee nodes.

Figure 5.10: Monitor Converter tab provides direct access to microconverter parameters.


5.5 Future Development

The designed communication module and PC GUI demonstrate the basic functionality

of the proposed wireless communication system. The implemented system provides the

framework for installing and managing a large-scale communication network containing

hundreds of PV microconverter modules. Several basic functions like converter gating

control and sensor reading have been implemented, demonstrating that more functions

can easily be added in the future. For example, the addition of microconverter out-

put voltage and current measurements can provide detailed information of the system

efficiency in real time.

Using a standardized protocol like ZigBee also adds the flexibility of using off-the-

shelf modems and gateways to customize access to the network. For example, using a

ZigBee to cellular or ethernet gateway for the coordinator can provide remote or web-

based monitoring of the PV system. Such features provide added value and marketability

for a system level PV solution.

Several ZigBee network design details have yet to be addressed. Since only one

node was used in the prototype system, the dynamic performance of the ZigBee network

containing hundreds of nodes has yet to be analyzed. Due to the lack of an open field

test site, the practical range of the XBee modems has yet to be tested. Moreover,

multi-hop messaging and routing features will have to be implemented to ensure reliable

communication in a larger PV installation. Finally, the ZigBee stack provides several

layers of data security and encryption that can be eventually be included.

Chapter 6

Experimental Results

This chapter presents the experimental results of the system designed in Chapter 3, in-

cluding the performance of the resonant boost converter as well the MPPT controller

developed in Chapter 4. The switching waveforms of the resonant boost converter are

analyzed and compared to the theoretical model of the converter described in Chapter

2. Efficiency measurements were taken of the converter operating at various power lev-

els, demonstrating the large step-up, high efficiency capabilities of the topology. The

emulated PV system was tested with the reduced sensor MPPT controller to validate

the MPPT model. The results indicate the applicability of the proposed resonant boost

converter and controller in the distributed MPPT PV system described in Chapter 1.

6.1 Converter Model Validation

In this section experimental results are provided to validate the theoretical analysis and

design procedure of the resonant boost converter as discussed in Chapter 2 and Chapter

3 respectively.

67

Chapter 6. Experimental Results 68

6.1.1 Nominal Operating Conditions

The converter circuit was first tested under nominal operating conditions given the pa-

rameters provided in Table 3.1. A 100 V DC voltage supply was used at the input and

the output supply voltage was set to 800 Vdc. The maximum power of the converter was

determined by tuning the “on” time ton of switches S1 and Sr via the MDC register to

achieve zero current turn-on and turn-off, then adjusting the switching frequency fs to a

point where a maximum average input current was observed. The peak inductor current

and capacitor voltage were also recorded, and the measured parameters are compared to

the expected values in Table 6.1.

Pnom (W ) Vi (V ) Vo (V ) fs,nom (kHz) iLpk (A) vCpk (V )

Expected 506 100 800 40.7 15.7 800Measured 486 100 800 40.7 15.5 804

Table 6.1: Expected and measured parameters at the nominal operating point.

Figure 6.1 shows the capacitor voltage and inductor current waveforms at the rated

power. At the maximum switching frequency of 40.7 kHz, the inductor current is con-

tinuous and no hold state is apparent. The peak inductor current was found to be near

the theoretical value, confirming that equation (2.18) accurately describes peak currents

required to rate the MOSFETs, IGBT, and resonant tank components in the circuit.

The recorded peak capacitor voltage was slightly above the ideal value of 800 V due to

voltage drop of the output diodes Do in the forward biased region.

The maximum power of the converter was recorded to be lower than the theoretical

value by 4%. The discrepency between the theoretical nominal power and the actual

measured power are a result of the conduction losses and switching losses damping the

gain of the resonant circuit. In addition, the theoretical value was calculated using an

approximation for the value of ton, resulting in a small margin of error. These results

indicates that the boost converter has practical finite gain, which can be quantified in

the future with a detailed loss model of the converter. Nevertheless, the measured power


Crv

[500 V/div]

Lri

[10 A/div]

time [5 s/div]µ

804 V

15.5 A

Figure 6.1: Resonant tank voltage and current waveforms at rated power.

was within range of the theoretical value, indicating that the design equation (2.15) is a

valid tool for rating the converter power.

6.1.2 Hold State and Soft Switching Operation

Variable frequency operation of the converter was analyzed by reducing the switching

frequency from the nominal value. Arbitrarily setting fs to 27 kHz via the PWM period

register PTPER, the soft switching, hold state, and snubber diode performance of the

converter were then analyzed.

In Figure 6.2 the inductor current iLr and capacitor voltage vCr show that the hold

state current is zero and that the stored capacitor voltage value around -800 V , as

expected. The constant capacitor voltage and inductor current indicate that the hold

state is near lossless. Conduction losses in the resonant tank circuit are evidently minimal,

as larger losses would cause the capacitor voltage to discharge rapidly during the hold

state.

Figure 6.3 shows the switching waveforms of the MOSFETs S1 and S2. The high

side MOSFET S1 is switched on at zero-current (ZC) since the current in the resonant


Crv

[500 V/div]

Lri

[10 A/div]

time [10 s/div]µ

Figure 6.2: Measured resonant inductor current and voltage waveforms at fs = 27 kHz.

tank is zero coming out of the hold state. The resonant tank current is commutated such

that S1 is gated “off” at ZC and the low side FET S2 is gated “on” at ZC. The hold

state naturally turns S2 off at ZC, thus very efficient switching is achieved in the FET

bridge. Some of the soft switching features rely on careful tuning of the ton parameter,

as described in the previous section. A feature to automatically tune ton can be added to

the converter control system in the future. This would involve a sensor in the tank circuit

to detect the zero current crossing of the inductor current, and using that information

to set the exact value of ton.

The waveforms of the interrupt switch Sr and anti-parallel diode Dr branch are shown

in Figure 6.4. Coming out of the hold state, the IGBT Sr is gated on at ZC and conducts

the positive half cycle of the resonant capacitor current. The freewheeling diode Dr

naturally turns on at ZC and ZV as the negative half cycle of the tank current resonates.

The hold state begins when the current through Dr goes to zero, after which the snubber

diode Ds conducts, clamping the voltage across Sr to Vo (800 V ). Some high frequency

oscillations are apparent in vSr, but the snubber limits these oscillations, preventing

voltage breakdown of the Sr in the forward blocking mode.

The output diode Do waveform is provided in Figure 6.5. Under nominal conditions,


Sv[50 V/div]

Si[10 A/div]

time [10 s/div]µ

Sv

[50 V/div]

Si

[10 A/div]

time [10 s/div]µ

a)

b)

ont

sTZC turn-on

ZC turn-off

ZC turn-on

ZC turn-off

Figure 6.3: Measured waveforms of a) FET S1 and b) FET S2 with a hold state.


Srv

[500 V/div]

Sri

[10 A/div]

time [10 s/div]µ

ZC turn-on

Figure 6.4: Measured waveforms of the interrupt switch Sr

the output diodes must reverse block a total 1.6 kV , equal to twice the output voltage.

However, the lab voltage probes could tolerate a differential voltage of 1 kV , therefore

the output voltage had to be decreased to 500 V for this measurement. Nevertheless, the

voltage and current waveforms indicate the soft switching operation of Do. The diode

voltage sinusoidally decreases to zero before turning on, achieving ZV switching. As the

output current reaches zero, the diode experience a soft turn-off as the reverse blocking

voltage gradually builds from zero. This effectively minimized the reverse recovery losses

in Do.

6.1.3 Input Filter Validation

The input voltage ripple at the nominal MPP voltage was measured to verify the input

filter design equation developed in section 3.1.3. The input capacitor Cin was designed to

reduce the input voltage ripple to 4 Vpk−pk in the worst case scenario where the converter

operates at 5% of the rated power and frequency. The test was conducted by connecting a

series resistance between the DC voltage supply and the input of the resonant converter,

effectively decoupling the output filter of the DC supply from the input filter of the


Dov

[500 V/div]

oi

[1 A/div]

time [10 s/div]µ

ZV turn-on ZV turn-off

Figure 6.5: Measured waveforms of the output diode Do

resonant boost converter. This provided an accurate method of testing the performance

of the input filter if a PV panel was used in place of the input DC supply.

Figure 6.6 shows AC coupled measurements of the input voltage vi with the converter

operating at the nominal frequency of 40.7 kHz, and at the 5% rated power frequency

of 2.04 kHz. As expected, the voltage ripple is larger at lower frequency, but well within

the 4 Vpk−pk design requirement.

i∆v

[1 V/div]

time [10 s/div]µ

i∆v

[1 V/div]

time [200 s/div]µ

a)

b)

pk-pk1.58 V

pk-pk2.85 V

Figure 6.6: Input voltage ripple at a) fs = 40.7 kHz and b) fs = 2.04 kHz.


6.2 Converter Efficiency

High electrical efficiency is a top priority when it comes to PV system design. In dis-

tributed MPPT systems, the efficiency of the microconverter interface must be very high

to achieve substantial energy harvesting gains over classical panel arrays that do not

use additional power electronics. Based on technology available on the market [6], effi-

ciency in the mid to high 90’s percentile is required for microconverter technology to be

competitive.

The target efficiency of the resonant boost converter was 95%. Unfortunately this

criteria was not met, and a discussion on how it can be improved is given at the end

of the section. Nevertheless, experimental results indicate that the converter exhibits

a nearly flat efficiency over a wide operating range. This feature is imperative for PV

systems installed in temperate climates where PV panels generate wide power ranges due

to varying atmospheric conditions.

6.2.1 Weighted Efficiency Results

The weighted efficiency of the resonant boost converter was measured in accordance

with the California Energy Commission (CEC) performance test protocol [26] used to

evaluate grid-connected PV inverters. Two sets of weighting factors were used, one set

corresponding to a climate that experiences overall high irradiance (CEC efficiency) and

another corresponding to a temperate climate with lower irradiance levels (EU efficiency).

Operating at the nominal input and output voltage levels, the efficiency of the con-

verter, given by equation (6.1), was measured at different percentages of the rated input

power. Table 6.2 shows the recorded efficiency values of the converter power controlled

by the variable length hold state method. It was also of interest to evaluate and compare

the efficiency of the converter using classical frequency and pulse skip modulation control

modes. For those measurements the interrupt switch Sr was bridged and the converter


control was implemented using switches S1 and S2 as described in section 2.3.1.

η =Po

Pi

(6.1)

Power Level (%) Vi (V ) Vo (V ) fs (kHz) Pi (W ) Po (W ) η (%)

100 100 800 40.7 486 431.2 88.775 100.2 800 32.3 364.6 329.6 90.450 100.4 800 21.46 243.6 216 88.730 100.5 801 12.9 146.1 129.762 88.820 100.5 800 8.66 98.3 86.4 87.910 100 801 4.27 48.4 42.453 87.75 100.1 801 2.13 24.3 20.826 85.6

Table 6.2: Recorded efficiency with hold state control mode.

The CEC efficiency and EU weighted efficiency equations are given below, where ηk

is the efficiency at the k percent power level as described in Table 6.2.

ηCEC = 0.04η10 + 0.05η20 + 0.12η30 + 0.21η50 + 0.53η75 + 0.05η100 (6.2)

ηEU = 0.03η5 + 0.06η10 + 0.13η20 + 0.10η30 + 0.48η50 + 0.20η100 (6.3)

Figure 6.7 shows a comparison of the converter efficiency versus the input power for

the three control modes. At maximum power, the converter waveforms are identical

for the three modes. Consequently, the peak efficiency is higher with frequency control

and pulse skip modulation since the conduction losses associated with Sr and Dr are

eliminated. Note that the measurements acquired with pulse skipping are discontinuous

to highlight the fact that the converter operating points are very discrete in this mode of

control. The weighted efficiency results of the converter are provided in Table 6.3. The

results clearly indicate that the hold state control method provides superior performance

over a wider operating range.


0 50 100 150 200 250 300 350 400 450 5000

10

20

30

40

50

60

70

80

90

100Efficiency, (%)

η

iInput Power, P (W)

Frequency control

Pulse skip modulation

Hold state

Figure 6.7: Converter efficiency versus input power.

Control Method CEC Efficiency, ηCEC EU Efficiency, ηEU

Hold state 89.53% 88.45%Pulse skip modulation 85.81% 81.9%Frequency control 75.59% 68.99%

Table 6.3: Weighted efficiency results.


With hold state control, the weighted efficiency is close to the peak efficiency, demon-

strating that the converter performance is insusceptible to conditions of varying power

production from the PV panels. Nevertheless, improvements to the converter design are

required to achieve the 95% efficiency goal. We have several ideas on how to improve

converter efficiency for future work. One factor that will lead to better performance is

to improve the design of the high frequency inductor Lr. Moving from the purchased E

Craftsman inductor mentioned in Chapter 3 to a custom inductor made in the lab re-

sulted in efficiency improvements on the order of three to four percent. We would expect

an additional improvement of one to two percent by moving to thicker copper gauge and

larger core size. Also, by lumping the series output diodes into a single device would

lower the forward biased voltage and reduce the Do conduction losses.

Furthermore, modifying the converter topology by adopting a full bridge instead of

half bridge circuit to drive the resonant tank would significantly improve the converter

efficiency. In the half bridge topology, the negative half cycle of the tank current is free-

wheeling and does not contribute to the net power delivered by the converter. Using a

full bridge switch would result in power drawn from the input during the entire resonant

period, effectively doubling the maximum power of the converter but maintaining com-

parable losses in the resonant circuit as the half bridge topology. Silicon carbide diodes

may be required in the output rectifier stage to maintain low losses.

6.3 MPPT Performance

The PV emulator was used as the input stage to the resonant boost converter to verify

the operation of the MPPT control system. Two I-V profiles were programmed in the

emulator, providing a method to analyze the transient and steady state behaviour of the

MPP tracker.


6.3.1 PV Emulator Parameters

The PV panel specifications chosen to test the PV emulator are shown in Table 6.4. With

a peak power voltage of 90 V and peak power current of 4.5 A, the selected PV profile

is capable of supplying 405 watts.

Parameter Value Units

Rated Power (Pmp) 405 WMaximum Power Voltage (Vmp) 90 VMaximum Power Current (Imp) 4.5 AOpen Circuit Voltage (Voc) 120 VShort Circuit Current (Isc) 4.77 AVoltage Temperature Coefficient (β) -0.172 V/KCurrent Temperature Coefficient (α) 0.88 mA/KReference Temperature (Tr) 25 C

Table 6.4: Emulated PV panel parameters.

Two irradiance levels were selected for the testbench, and the measured I-V and P-V

characteristics are compared with the theoretical curves shown Figure 6.8 and Figure 6.9

respectively. The measured results indicate I-V curves sufficiently close to the theoretical

values, although some offset is evident in the constant current portion of the curves.

6.3.2 MPPT Results

The MPPT controller test was performed by initializing the PV emulator on the 800

W/m2 operating curve, then applying a step change in irradiance to 500 W/m2. In prac-

tice, a PV panel would experience a gradual change in irradiance due to cloud movement

or over the course of a day, but the test provided a convenient method of analyzing

the converter’s response to large disturbances of input power. Using a fixed step size of

∆F = 500 Hz for the MPPT controller, the converter input voltage vpv and power ppv

over time are shown in Figure 6.10.

Following the turn-on transients, the waveforms demonstrate that the MPPT con-

troller is capable of tracking the correct peak power of the PV emulator according to the


0 20 40 60 80 100 120 1400

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

PV Current, i

(A)

PV

PV Voltage, v (V)PV

2800 , 25W Cm

°

2500 , 25W Cm

°

Figure 6.8: Measured (points) and theoretical (curve) I-V characteristics under two shad-ing conditions.

0 20 40 60 80 100 120 1400

50

100

150

200

250

300

350

400

X: 93.2Y: 339.2

X: 88.7Y: 201.7

PV Power, p

(W)

PV

PVPV Voltage, v (V)

2800 , 25W Cm

°

2500 , 25W Cm

°

Figure 6.9: Measured (points) and theoretical (curve) P-V characteristics highlightingmaximum power points.


pvv

time [2 s/div]

[20 V/div]

pvp [120 W/div]

93 V87 V

336 W

201 W

2W800m 2

W500m

Figure 6.10: Waveforms showing converter tracking MPP of two emulated PV profiles.

expected values documented in Figure 6.9. At 800 W/m2, the MPPT controller reaches

steady state and oscillates about the MPP voltage of 93 V , which matches closely with

the expected value of 93.2 V .

As the step change from 800 W/m2 to 500 W/m2 is applied, the operating point

of the converter shifts and the input voltage drops. The MPPT controller responds to

the change by hill-climbing to the MPP of the new I-V characteristic. In this case, the

magnitude of the steady state oscillations are larger due to the fact that the fixed 500

Hz step size incurs a larger gain in power at the lower irradiance level. Recall that the

power drawn by the converter is directly proportional to the frequency. This issue can

be mitigated by adopting an adaptive hill-climbing algorithm that dynamically adjusts

the step size to achieve better steady-state and transient performance.

Overall, the ability of the MPPT controller to correctly track the MPP of the two I-V

curves validates the model and algorithm developed in Chapter 4. While the steady-state

performance of the controller was sub-optimal due to the fixed step size, modifications

to the algorithm discussed in section 4.4 can be applied in future work.

Chapter 7

Conclusion

Grid-connected photovoltaic power systems today are moving from central inverter topolo-

gies to distributed MPPT strategies. By dividing the PV panel array and localizing peak

power tracking on a sub-array or per-panel level, the energy harvesting of the plant can

be significantly improved, requiring fewer solar panels to effectively generate the same

amount of power at the grid. Many distributed MPPT systems have been proposed, some

of which have been reviewed in Chapter 1. However many concepts suffer from high cost

and/or low reliability when it comes to commercial or utility scale installations.

This thesis proposed a new PV system architecture that provides improved energy

harvesting versus cost by connecting the low-voltage panels in parallel to increase power

production and to reduce susceptibility to partial shading. The panels are then interfaced

to a high voltage DC bus to minimize cabling costs. A three-phase inverter is employed

to avoid 120 Hz ripple power on the DC link. This eliminates the need for unreliable

electrolytic DC link capacitors. A DC-DC switch-mode converter capable of high step-up

conversion ratios at high efficiency was required to practically achieve this architecture.

This created a research opportunity to investigate the viability of the system by devel-

oping a microconverter interface featuring a DC-DC step-up topology, MPPT controller,

and embedded communication.

81

Chapter 7. Conclusion 82

A testbench PV system was designed and implemented. The focus of the system was

on a prototype for a 500 W microconverter employing a novel resonant boost converter

topology capable of achieving large voltage gains by resonating a series LC circuit at its

natural frequency. By interrupting the resonant current and introducing a lossless hold

state, the converter operates over a wide power range with a near constant efficiency.

To emulate the high voltage DC bus interface, a 4.3 kW , 800 V DC power supply was

designed, providing regulation of the bus voltage level with a variac. In addition, a

programmable photovoltaic emulator capable of supplying 780 W at efficiencies up to

98.5% was introduced to test the MPPT controller of the microconverter. The low cost

PV emulator proved to be an effective testing tool and is readily available in the lab for

future use.

A peak power tracker using minimal sensing components was developed for the res-

onant converter. The maximum power point was tracked by exploiting the relationship

between input voltage and converter switching frequency. This effectively reduced the

cost and increased the reliability of the control system by eliminating the need for a DC

current sensor to perform MPPT. The methodology used to derive the reduced sensor

algorithm can be generally applied to a broad class of converters that use pulse fre-

quency modulation control. A wireless communication system using the standardized

ZigBee protocol was implemented, providing advanced control, monitoring, and protec-

tion features to the PV system. A flexible framework was created to allow addressing

of multiple converters per communication module, distributing the cost per watt of the

communication system.

The designed system provided promising results in asserting the viability of the

parallel-panel PV architecture. For a system using ten 500 W converters per communica-

tion board, an estimated cost of 87.16 $kW

was determined for the smart microconverter

technology including the power stage, MPPT controller and embedded communications,

Figure 7.1. Compared with a benchmark price of 6106 $kW

for a 50 kW commercial system

Chapter 7. Conclusion 83

[27], the microconverter technology is a low cost solution for providing distributed MPPT

to achieve higher energy yield and return from the PV system. The parallel architecture

improves on the modularity and ease of installation over competing series-string systems.

In addition, high reliability was achieved by eliminating electrolytics from the design,

and the safety benefits of low-voltage panel connections are further complimented by the

central communication system. With a weighted efficiency of around 89%, further work

must be done on the converter design to meet the 95% goal. We believe this milestone

could be met with a better magnetics design, a modification of the converter to a full

bridge topology, and possibly introducing the use of silicon carbide in the output rectifier

stage.

Figure 7.1: Cost distribution of microconverter components.

Bibliography

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[13] D. Jovcic and B.T. Ooi, “High-Power, Resonant DC/DC Converter for Integration

of Renewable Sources,” IEEE Bucharest Power Tech Conference, July 2, 2009.

[14] L. H. Dixon, “Eddy Current Losses in Transformer Windings and Circuit Wiring,”

Unitrode/TI Magnetics Design Hand-book, TI Literature No. SLUP132, Topic R4,

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[15] M. Buresch, Photovoltaic Energy Systems: Design and Installation. Toronto:

McGraw-Hill, 1983.

[16] “dsPIC33FJ06GS202 Data Sheet: High Performance 16-bit Digital Signal Con-

trollers,” Microchip Datasheet, http://www.microchip.com, July 20, 2010.

[17] S. Poshtkouhi, J. Varley, R. Popuri, and O. Trescases, “Analysis of Distributed Peak

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Appendix A

Converter PCB Schematics

The circuit schematics of the resonant boost converter prototype PCB are provided here.

Many components in the circuit are used for debugging purposes, and would not be

included in a final design. Figure A.1 contains the converter power stage, Figure A.2

provides the gate driving circuit, and Figure A.3 contains the microcontroller and analog

sensing circuits. The PCB was designed using Altium’s DXP 2004 CAD platform. The

bill of materials of the main converter components are provided in Appendix B.

87

Appendix

A.

ConverterPCB

Schematics

88

Vin1

Gnd2

CN4

VIN_CON

316uH

L1Inductor

Vout1

Gnd2

CN3

VOUT_CON

11

22

TP12Bridge

TP6

Vin+

Vosens

Visens_in

Isens_in

Visens

Isens

12 2.2u 875V

C25Cap

12 39u 100V

C26Cap

1

23

Q3IGBT-N

11

22

TP11Bridge

Q1IRFS4615

68nF

C11Cap

11

22

TP10

Bridge

11

22

TP8

BridgeFET_HI

FET_LO

VBRIDGE

Vosens_inVosens

IGBT_LO

TP15

Vc-

TP16

Gnd

PGND

10mH

FB1

Inductor

PGND

2

1

3

Q2IRFS4615

11

22

TP9

Bridge

TP7

Vo

31

D4Diode

IP+

1IP

+2

IP+

3IP

+4

IP-

5IP

-6

IP-

7IP

-8

GN

D9

VZ

CR

10

FIL

TE

R11

VIO

UT

12

FA

UL

T13

VC

C14

VO

C15

FA

UL

T_

EN

16

Cu

rren

t S

enso

r

IS1CurrentSensor

+3V3

12

10nC12

12

0.8nC13

Isens

0.1uC18

Visens

12

10uC14

3 1D2

Diode

3 1D1

Diode

3 1D3

Diode

Figu

reA.1:

Reson

antboost

converter

pow

erstage

schem

atic.

Appendix

A.

ConverterPCB

Schematics

89

IGBT Driver

+10V

+10V

NC1

INA2

GND3

INB4

!OUTB5

VDD6

!OUTA7

NC8

U3

TC427

0.1u

C23

+10V

0.1u

C24

IN_HI1

IN_LO2

GND3

DR_LO4

VCC5

BRG6

DR_HI7

VBOOT8

U2

NCP518110

R22

FET_HI

FET_LO

+10V

VBRIDGE

1kR191kR21

1 2D5

Diode

5.1R18

FET_HI_DRVFET_LO_DRV

IGBT_LO1kR24

Bridge Driver

TP17

Qhi

TP18

Qlo

12

10uC15

12

10uC17

Vin1

Gnd2

Gnd3

CN2

TER_3

+10V

12 10u

C16

+10V

10

R20

10

R23

0.1uC19

0.1uC20

PGND

PGNDPGND

PGND

PGND

PGND

Figu

reA.2:

Gate

drivers

circuitsch

ematic.

Appendix

A.

ConverterPCB

Schematics

90

+3V3

+3V3

12 10u

C4

+3V3

0.1uC8

0.1uC9

S5

SW-PB

+3V3

10kR13

Reset

30k

R1

820

R7

Visens_in

1nC1

Cap

2.7M

R2

Vosens_in Isens_in

Isens_MCUVosens_MCUVisens_MCU

Sensing Circuits

S2SW-PB

+3V3

10kR4

S1SW-PB

+3V3

10kR3

RB8

MCU I/Os

Vin1

Gnd2

Gnd3

CN1

TER_3

+3V3

+3V3

12 10u

C5

1 2

10u

C3

TP3

Vis

TP4

Vos

TP5

Is

FET_HI_DRVFET_LO_DRV

Visens_MCUVosens_MCUIsens_MCU

PGED2PGEC2

MCLR

Debugger/Programmer

VPP1

VDD2

GND3

PDAT4

PCLK5

NC6

JP2

PIC_PROG

MCLR

0.1uC10

+3V3

PGED2PGEC2

1 23 45 67 89 10

JP1

Header 5X2

Communication Connector

+3V3

10kR14

10kR15

10kR16

10kR17

S3SW-PB

+3V3

10kR5

300

R11

DS3

300

R12

DS4

RB8

RB9RB10

RB11

MCLR!1

AN0/CMP1A2

AN1/CMP1B3

AN2/CMP2A4

AN3/CMP2B5

AN4/RB96

AN5/RB107

Vss8

CLKIN9

CLKO10

PGED2/RB311

PGEC2/EXTref12

Vdd13

RB814

RB15/RP1515

RB5/RP516

RB6/RP617

RB7/RP718

Vss19

Vcap20

RB1121

RB1222

PWM2H/RB1323

PWM2L/RB1424

PWM1H25

PWM1L26

AVss27

AVdd28

U1

DSPIC33FJ06GS202

RB9 RB10 RB11

TP2

RB11

10k

R81nC2

Cap

Figu

reA.3:

Micro

controller

andan

alogsen

sorssch

ematic.

Appendix B

Converter PCB Bill of Materials

The bill of materials for the resonant boost converter PCB prototype is provided here.

Note that only the main components of the power stage and microcontroller circuit are

provided, with designators corresponding to the PCB schematic provided in Appendix A.

Some components were either used for debugging or prototyping purposes, and would not

be in a final design, hence were omitted from the bill of materials. Some elements such

as an on-board power supply for the gate drivers and microcontroller were not included

in the prototype design, and will have to be added in the future.

The high frequency inductor L1 was built in the lab using 34 turns (2 layers) of 13

AWG litz wire (650 strands of 40 AWG) on a Ferroxcube 3C95 core.

91

Appendix

B.

ConverterPCB

BillofMaterials

92

Designator Description Part Quantity Unit Price (CAD)

Power Stage ComponentsQ1,Q2 MOSFET N-CH 200 V, 26 A, 21 mΩ IRFI4227PBF 2 1.50Q3 IGBT Ultra Fast 1200 V, 30 A IRG4PH40KPBF 1 2.65

D1,D2,D3 Diode Ultra Fast 1000 V, 8 A MUR8100EG 3 0.54D4 Diode Fast Rec. 1200 V, 20 A 20ETF12 1 2.53L1 Inductor HF 221 µH, 16 A N/A 1 15.00 (est.)C11 Capacitor PolyFilm 68 nF, 630 VAC 940C20S68K-F 1 1.82C26 Capacitor Film 39 µF, 100 V FFB34E0396K 1 8.04U2 MOSFET Driver HI/LO 600 V NCP5181PG 1 1.56U3 MOSFET Driver LO 1.5 A TC427CPA 1 0.97D5 Bootstrap Diode 400 V, 1 A US1G-13-F 1 0.08

R20,R22,R23 Gate Resistor 10 Ω, 1/2 W, 5% ERJ-14YJ100U 3 0.023Control System Components

U1 dsPIC Microcontroller 3V3, 40 MIPS DSPIC33FJ06GS202 1 3.23R7 Resistor 820 Ω, 1/2 W, 1% LTR18EZPF8200 1 0.041R1 Resistor 30 kΩ, 1/2 W, 1% CRCW121030K0FKEA 1 0.057C1 Capacitor Ceramic, 1 nF, 50 V C0805C102K5RACTU 1 0.0073JP1 10 Pin Vertical Header 5103308-1 1 0.43

C3,C4,C5,C15 Capacitor Ceramic, 10 µF, 16 V C3216X7R1C106M 4 0.063C8,C9,C19,C20,C23,C24 Capacitor Ceramic, 0.1 µF, 50 V C0805C104K5RACTU 6 0.009Total (power stage): 37.34Total (control system): 4.07Grand Total: 41.41

Table B.1: Converter PCB bill of materials.

Appendix C

Communication Module PCB

Schematics

The schematics of the communication module are provided here. This is a prototype

PCB. Additional components are required for a final design, including an on-board +3.3V

power supply for powering the logic.

93

Appendix

C.

Communication

ModulePCB

Schematics

94

VCC1

DOUT2

DIN3

DO84

!RES5

RSSI6

PWM17

NC8

!DTR9

GND10

DIO411

!CTS12

ON/!SLEEP13

VREF14

ASSOC15

!RTS16

DIO317

DIO218

DIO119

Commission20

U1

Xbee ZB

+3V3

+3V3

12 10u

C2

+3V3

0.1u

C5

0.1u

C6

S2

SW-PB

+3V3

10kR3

Reset

Vin1

Gnd2

Gnd3

CN1

TER_3

+3V3

+3V3

12 10u

C3

1 210uC1

PGED2

PGEC2

MCLR

Debugger/Programmer

VPP1

VDD2

GND3

PDAT4

PCLK5

NC6

JP2

PIC_PROG

MCLR

0.1u

C4

+3V3

PGED2

PGEC2

+3V3

10k

R8

10k

R9

UART_RX

UART_TXUART_RTSUART_CTS

+3V3

0.1u

C7

+3V3

UART_RX

UART_TX

UART_CTS

UART_RTS

+3V3

10kR4

10kR5

10kR6

10kR7

MCLR

S1 SW-PB

+3V3

10kR1

300R2

DS1

1 23 45 67 8

9 10

JP1

Header 5X2

S4

SW-PB

+3V3

10kR11

S3

SW-PB

+3V3

10kR10

RA0

MCU I/Os

S5

SW-PB

+3V3

10kR12

300

R13

DS2

300

R14

DS3

RA1 RA2 RA3

RA0RA1

RA2

RA3

TP6SCL

TP5SDA

TP1

URX

TP2

UTX

TP3 UCTS

TP4URTS

0.1u

C8

I2C Communication Connector

Decoupling Capacitors Xbee ZNET Zigbee Module

MCLR!1

RA02

RA13

RA24

RP0/RB05

RP9/RB96

RP10/RB107

Vss8

RP1/RB19

RP2/RB210

PGED2/RB311

PGEC2/EXTref12

Vdd13

RP8/RB814

RB15/RP1515

RB5/RP516

RB6/SCL17

RB7/SDA18

Vss19

Vcap20

RP11/RB1121

RP12/RB1222

RP13/RB1323

RP14/RB1424

RA425

RA326

AVss27

AVdd28

U2

DSPIC33FJ06

SDA

SCL

SDASCL

Figu

reC.1:

Com

munication

module

PCB

schem

atic.

Appendix D

Communication Module PCB Bill of

Materials

Ths bill of materials for the communication module is provided here. The unit price

reflects the cost of the comopnent in quantities of 10 000 or less. Note that the cost does

not reflect a final design, but just the prototype system. Components used for debugging

and programming were omitted from the bill of materials.

95

Appendix

D.

Communication

ModulePCB

BillofMaterials

96

Designator Description Part Quantity Unit Price (CAD)

Communication Module ComponentsU1 XBee ZB low power ZigBee module with wire antenna XB24-Z7WIT-004 1 17.83U2 dsPIC Microcontroller 3V3, 40 MIPS DSPIC33FJ06GS202 1 3.23JP1 10 Pin Vertical Header 5103308-1 1 0.43

R3,R8,R9 Resistor 10kΩ, 1/8 W, 5% MCR10EZPJ103 3 0.003C1,C2 Capacitor Ceramic, 10 µF, 16 V C3216X7R1C106M 3 0.063

C5,C6,C7,C8 Capacitor Ceramic, 0.1 µF, 50 V C0805C104K5RACTU 4 0.009Grand Total: 21.72

Table D.1: Communication module PCB bill of materials.

Appendix E

Converter Microcontroller Source

Code

Software development was done using the Microchip MPLAB IDE with an academic

license for the C30 C compiler. The Microchip PICKit 2 was used for in-circuit program-

ming and debugging of the microcontroller.

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗Pro j ect : Resonant Boost Converter MPPT and Communication Cont r o l l e r∗∗FileName : CONVERTER main. c∗Proces sor : Microchip dsPIC33FJ06GS202∗Author : Gregor Simeonov∗Company : Univer s i ty o f Toronto − Energy Systems Group∗Date : 08/20/2010∗∗Notes : A Maximum Power Point Tracking (MPPT) c o n t r o l l e r f o r a resonant boost conver ter∗ with va r i ab l e f r equency con t r o l us ing a h i l l c l imbing MPPT algor i thm with a∗ f i x ed s tep s i z e . Nominal sw i tch ing f r equency o f the conver ter i s 40 . 7kHz ,∗ sw i tches are gated in a complementary f a sh i on us ing the PWM1 module∗ o f the m i c r o c on t r o l l e r ( port outputs PWM1L and PWM1H) .∗∗ An app l i c a t i on l aye r communication p r o to co l i s used to send ADC r e g i s t e r contents∗ and r e c e i v e s t a r t / stop gat ing /MPPT commands f o r the conver ter . This i s implemented∗ us ing the I2C module o f the m i c r o c on t r o l l e r with a hard−coded I2C bus addres s∗ o f the dev i ce de f i ned in the code . The conver ter i s an I2C s l ave dev i ce .∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/#inc l ude ” p33 f j 06gs202 . h” // i n c l ude conta ins s t r u c t s f o r a s s i gn i ng i nd i v i d u a l b i t s

//Def ine I /O b i t p o s i t i o n s#de f i n e LO DRV (0 x0008 )#de f i n e HI DRV (0 x0010 )#de f i n e LED ON (0 x0800 )#de f i n e BIT0 (0 x0001 )#de f i n e BIT1 (0 x0002 )#de f i n e BIT2 (0 x0004 )#de f i n e BIT3 (0 x0008 )#de f i n e BIT4 (0 x0010 )#de f i n e BIT5 (0 x0020 )#de f i n e BIT6 (0 x0040 )#de f i n e BIT7 (0 x0080 )

97

Appendix E. Converter Microcontroller Source Code 98

#de f i n e BIT8 (0 x0100 )#de f i n e BIT9 (0 x0200 )#de f i n e BIT10 (0 x0400 )#de f i n e BIT11 (0 x0800 )#de f i n e BIT12 (0 x1000 )#de f i n e BIT13 (0 x2000 )#de f i n e BIT14 (0 x4000 )#de f i n e BIT15 (0 x8000 )

//MPPT Cont r o l l e r cons tants and va r i a b l e s#de f i n e Ts MIN 2890#de f i n e Ts MAX 60000#de f i n e AVGNUM 256#de f i n e DELTA F 500#de f i n e VOUT 6606 //800V∗(2ˆ10)/124 = 6767 , s c a l e s with 10−b i t Vin sensor

i n t initMPPT ;uns igned i n t ADC Vin , ADC Iin , ADCcount ;uns igned i n t Vavg , Iavg ;uns igned long Vacc , Iacc ;uns igned long Pmk, Pmk 1 , Fk ,Vk,Tk ;i n t s tep = 0 ;

//I2C Communication constants , va r i ab l e s , and s t r u c t#de f i n e CONVADDRESS 0x0008#de f i n e I2CTX SIZE 5#de f i n e I2XRX SIZE 1s t r uc t UDP

uns igned char Status ;uns igned char Vin [ 2 ] ;uns igned char I i n [ 2 ] ;

uns igned char I2CTXBuffer [ 5 ] ;uns igned i n t I2CTXIndex ;

;s t r u c t UDP Converter ;

i n t main ( void )

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ In t e r na l O s c i l l a t o r Conf i gurat i on∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗///Fosc= Fin∗M/(N1∗N2) , Fcy=Fosc /2 , Fin = 7.37 Mhz//Fosc= 7.37∗(43)/(2∗2)=80Mhz f o r Fosc , Fcy = 40Mhz

PLLFBD=43; // M = PLLFBD + 2CLKDIVbits .PLLPOST=0; // N1 = 2CLKDIVbits .PLLPRE=0; // N2 = 2

builtin write OSCCONH (0 x01 ) ; // New Os c i l l a t o r FRC w/ PLLbuiltin write OSCCONL (0 x01 ) ; // Enable Switch

whi le (OSCCONbits.COSC != 0b001 ) ; // Wait f o r new Os c i l l a t o r to become FRC w/ PLLwhi le (OSCCONbits.LOCK != 1 ) ; // Wait f o r P l l to Lock

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ I /O Port Conf i gurat i on∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/ADPCFG = 0xFFF8 ; // Set AN0 and AN1, AN2 as analog input

TRISA = 0x0000 ; //PORT A − s e t analog p ins as inputsTRISA |= BIT0 + BIT1 + BIT2 ;

TRISB = 0x0000 ; //PORTB − s e t push buttons as inputsTRISB |= BIT8 + BIT9 + BIT10 ;

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ PWM and ADC Clock Conf i gurat i on∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗///PWM and ADC Clock = ( (FRC ∗ 16) / APSTSCLR ) = (7 . 37 ∗ 16) / 1 = ˜ 120MHzACLKCONbits .FRCSEL = 1 ; //FRC prov ides input f o r Aux i l i a ry PLL ( x16 )ACLKCONbits .SELACLK = 1 ; // Auxi l i a ry O s c i l l a t o r prov ides c l ock sour ce f o r PWM & ADCACLKCONbits .APSTSCLR = 7 ; //Divide Aux i l i a ry c l ock by 1ACLKCONbits .ENAPLL = 1 ; //Enable Aux i l i a ry PLL


whi le (ACLKCONbits .APLLCK != 1 ) ; //Wait f o r Aux i l i a ry PLL to LockPWMCON1bits.CAM = 0 ; //Edge−Aligned ModePWMCON1bits.MDCS = 1 ; //Duty cyc l e sour ce = Master Duty Cycle r e g i s t e r

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ PWM Module Conf i gurat i on∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/PTCON2bits .PCLKDIV = 3 ; //Clock Pr e s ca l e r = 8

PTPER = 2890; //PWM Per iod PTPER = P des i r ed /( p r e s c a l e r ∗1.04 e−9)// P des i r ed = 1/Fs = 40 .7 kHz

MDC = PTPER/2; //FIXED ON TIME at 50% Duty o f MAX Fs

IOCON1bits .PENH = 0 ; //PWM1H i s c on t r o l l e d by PWM moduleIOCON1bits .PENL = 0 ; //PWM1L i s c on t r o l l e d by PWM moduleIOCON1bits .PMOD = 0 ; // S e l e c t Complementary Output PWM mode

DTR1 = 0 ; //No Deadtime = (65 ns / 1 . 04 ns ) where 65ns i s d e s i r ed deadtimeALTDTR1 = 0 ; //No ALTDeadtime = (65 ns / 1 . 04 ns ) where 65ns i s d e s i r ed deadtimePHASE1 = 0 ; //No phase s h i f t

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ADC Module Conf i gurat i on∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/ADCONbits .FORM = 0; // In t eg e r data formatADCONbits . EIE = 0 ; //Early In t e r r up t d i s ab l edADCONbits .ORDER = 0 ; //Convert odd channel f i r s tADCONbits .SEQSAMP = 0 ; // S e l e c t s imultaneous samplingADCONbits .ADCS = 0 ; //ADC clock = FADC/6 = 120MHz / 6 = 20MHz

IFS6b i t s .ADCP0IF = 0 ; //Clear ADC Pair 0 i n t e r r up t f l a gIPC27bits .ADCP0IP = 5 ; // Set ADC Pair 0 i n t e r r up t p r i o r i t yIEC6bits .ADCP0IE = 1 ; //Enable the ADC Pair 0 i n t e r r up t

ADSTATbits .P0RDY = 0 ; //Clear Pai r 0 data ready b i tADCPC0bits . IRQEN0 = 1 ; //Enable ADC Inte r r up t pa i r 0ADCPC0bits .TRGSRC0 = 4 ; //ADC Pair 0 t r i g g e r e d by PWM1 Tr igger

TRGCON1bits .DTM=0; //SINGLE t r i g g e r modeTRIG1bits .TRGCMP=0; //Primary t r i g compare value

TRGCON1bits .TRGDIV = 0xF ; // Tr i gger generated every 15 th PWM cyc l eTRGCON1bits .TRGSTRT = 63; //Enable Tr i gger generated a f t e r 63 PWM cyc l e sTRIG1 = 1445; // Tr i gger compare value , compare at MDC/2 = 1445 o f the PTPER

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ I2C Module Conf i gurat i on∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/I2C1BRG = 0x188 ; //100 kHz operat i on at 40 MIPs

IPC4 = 0x0006 ; //I2C Slave In t e r r up t p r i o r i t y l e v e l 6IEC1bits . SI2C1IE = 1 ; //Enable s l av e i n t e r r up tIFS1b i t s . SI2C1IF = 0 ; //Clear s l av e i n t e r r up t f l a g

I2C1CONbits .STREN = 1 ; //Enable c l ock s t r e t c h i n gI2C1CONbits .A10M = 0 ; //7 b i t addres s ing used f o r s l av eI2C1CONbits .GCEN = 1 ; //Enable g ene r a l c a l l s f o r emergency shut down f ea tu r eI2C1ADD = CONVADDRESS; //Address o f s l av e dev i ce

I2C1CONbits . I2CEN = 1 ; //Enable I2C module , s e t port I /Os f o r module

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ Main Program Loop∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/Converter . Status = 0x00 ;

//Monitors communication r e g i s t e r to enable / d i s a b l e MPPT/ gat ingwhi le (1)

//MPPT/ gat ing d i s ab l ed in conver ter s t a tu s r e g i s t e ri f ( ( Converter . Status&0x01)==0)

//MPPT o f f , re− i n i t i a l i z e MPPT parametersVacc = 0 ;Iacc = 0 ;ADCcount = 0 ;


initMPPT = 0 ;PTPER = Ts MIN ; // Set PWM to maximum fr equency

IOCON1bits .PENH = 0 ; //PWM1H i s c on t r o l l e d by PORTAIOCON1bits .PENL = 0 ; //PWM1L i s c on t r o l l e d by PORTAPTCONbits .PTEN = 1 ; // Di sab l e PWMADCONbits .ADON = 0 ; // Di sab l e ADC module /MPPT

PORTA &= ˜LO DRV & ˜HI DRV; //Turn o f f sw i tchesPORTB &= ˜LED ON; //Turn o f f s t a tu s LED

//MPPT/ gat ing enabled in conver ter s t a tu s r e g i s t e re l s e

IOCON1bits .PENH = 1 ; //PWM1H i s c on t r o l l e d by PWM moduleIOCON1bits .PENL = 1 ; //PWM1L i s c on t r o l l e d by PWM modulePTCONbits .PTEN = 1 ; //Enable PWMADCONbits .ADON = 1 ; //Enable ADC module/MPPTPORTB |= LED ON; //Turn on s ta tu s LED

//Update conver ter s t a tu s and sensor va lues f o r communicationConverter . I2CTXBuffer [ 0 ] = Converter . Status ;Converter . I2CTXBuffer [ 1 ] = Vavg>>8;Converter . I2CTXBuffer [ 2 ] = Vavg&0x00FF ;Converter . I2CTXBuffer [ 3 ] = Iavg>>8;Converter . I2CTXBuffer [ 4 ] = Iavg&0x00FF ;

r e turn 1 ;

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ADC Inte r r up t Se r v i c e Routine and MPPT Cont r o l l e r Algorithm∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/void a t t r i b u t e ( ( i n t e r r u p t , no auto psv ) ) ADCP0Interrupt ( )

IFS6b i t s .ADCP0IF=0;

ADC Vin = ADCBUF0; //10− b i t ADC Vin sensor readADC Iin = ADCBUF1; //10− b i t ADC I i n sensor read

Vacc += ( long ) ADC Vin ; //Vin accumulator f o r averag ingIacc += ( long ) ADC Iin ; // I i n accumulator f o r averag ingADCcount++;

i f (ADCcount==AVGNUM)

// Cal cu l ate average value o f Vin and I i nVavg = ( i n t ) Vacc/AVGNUM;Iavg = ( i n t ) Iacc /AVGNUM;

Vacc = 0 ;Iacc = 0 ;ADCcount = 0 ;

i f ( initMPPT == 0)

Vk = ( long ) Vavg ;Fk = ( long ) 120192308/PTPER;//Fk = 1/ t r /PTPER = 1/(8∗1 . 04 e−9)/PTPERPmk = Vk∗Fk/(VOUT−Vk) ; // Cal cu l ate power f unc t i on PmPmk 1 = Pmk;

s tep = −DELTA F; //Assign i n i t i a l per turbat i on d i r e c t i o ninitMPPT = 1 ; //MPPT i n i t i a l i z a t i o n complete

e l s e

Vk = ( long ) Vavg ;Fk = ( long ) 120192308/PTPER;Pmk = Vk∗Fk/(VOUT−Vk) ; // Cal cu l ate power f unc t i on Pmk

//MPPT Hi l l−c l imbing Algorithmi f (Pmk>Pmk 1)

// I f pr ev i ous s tep was 0 , apply new stepi f ( s tep==0)


s tep = −DELTA F;//Else , keep same per turbat i on d i r e c t i o ne l s e

s tep = step ;

e l s e i f (Pmk<Pmk 1)

// I f pr ev i ous s tep was 0 , apply new stepi f ( s tep==0)

s tep = DELTA F;//Else , r ev e r s e per turbat i on d i r e c t i o ne l s e

s tep = −s tep ;

e l s e

s tep = 0 ;//Update old value o f PmPmk 1 = Pmk;

//Apply s tep by changing PTPER r e g i s t e r , apply f r equency l im i t e ri f ( s tep !=0)

//Convert f r equency to per i od f o r PTPER r e g i s t e rFk = Fk + step ;Tk = 120192308/ Fk ;

//Apply swi tch ing f r equency ( per i od ) l i m i t e ri f (Tk>=Ts MAX)

PTPER = Ts MAX;e l s e i f (Tk <= Ts MIN)

PTPER = Ts MIN ;e l s e

PTPER = ( i n t ) Tk ;

ADSTATbits .P0RDY = 0 ; // Clear s t a tu s b i t i n d i c a t i n g data has been read

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ I2C Slave In t e r r up t Se r v i c e Routine and Communication Cont r o l l e r∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/void a t t r i b u t e ( ( inter rupt , no auto psv ) ) SI2C1Inter rupt ( void )

uns igned char din ;

//Detect that communication has s ta r t ed with START b i ti f ( I2C1STATbits . S==1)

//Write to s l av e operat i oni f ( I2C1STATbits .RW==0)

// I f l a s t wr i te was an addres si f ( I2C1STATbits .D A==0)

din = I2C1RCV ; //need to read r e c e i v e bu f f e r to prevent over f l owe l s e


Converter . Status = I2C1RCV ;// r e l e a s e SCL i f c l ock s t r e t c h occuredI2C1CONbits .SCLREL = 1 ;

//Read from s l ave operat i one l s e i f ( I2C1STATbits .RW==1)

//Need to read addres s b e f o r e sending f i r s t bytei f ( I2C1STATbits .D A==0)

din = I2C1RCV ; //need to read r e c e i v e bu f f e r to prevent over f l ow

// send f i r s t byteConverter . I2CTXIndex = 0 ;I2C1TRN = Converter . I2CTXBuffer [ Converter . I2CTXIndex ] ;Converter . I2CTXIndex++;I2C1CONbits .SCLREL = 1 ;

//Send remainder o f bytese l s e

// check i f master i s done r e c e i v i ng , i e . s l av e done transmi tt ingi f ( I2C1STATbits .ACKSTAT==1)

I2C1CONbits .SCLREL = 1 ;//done transmi tt ing !

e l s e

// check tx bu f f e r rangei f ( Converter . I2CTXIndex==5)

Converter . I2CTXIndex = 4 ;I2C1TRN = Converter . I2CTXBuffer [ Converter . I2CTXIndex ] ;Converter . I2CTXIndex++;I2C1CONbits .SCLREL = 1 ;

IFS1b i t s . SI2C1IF = 0 ; //Clear the DMA0 In t e r r up t Flag ;

Appendix F

PV Emulator Microcontroller

Source Code

Software development was done using the Microchip MPLAB IDE with an academic

license for the C30 C compiler. The Microchip PICKit 2 was used for in-circuit program-

ming and debugging of the microcontroller.

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗Pro j ect : Photovo l ta i c I−V Curve Emulator Cont r o l l e r∗∗FileName : PV main . c∗Proces sor : Microchip dsPIC33FJ06GS202∗Author : Gregor Simeonov∗Company : Univer s i ty o f Toronto − Energy Systems Group∗Date : 06/07/2010∗∗Notes : D i g i t a l buck conver ter c o n t r o l l e r implementing up to two independent PV∗ I−V ch a r a c t e r i s t i c s . A vo l tage loop measures output vo l tage and r e gu l a t e s a∗ cur r ent r e f e r e n c e cor r espond ing to the I−V ch a r a c t e r i s t i c o f the programmed∗ PV curve .∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/#inc l ude ” p33 f j 06gs202 . h”#inc l ude ”math . h”

//Def ine I /O b i t p o s i t i o n s#de f i n e LO DRV (0 x0008 )#de f i n e HI DRV (0 x0010 )#de f i n e PB START (0 x0100 )#de f i n e LED ON (0 x0800 )#de f i n e PB SEL (0 x0200 ) // b i t 9

//PV I−V Curve Model Var i ab l e sf l o a t Voc , Isc ,Vmp, Imp , Ct , Tr , Rs , Di ,C1 ,C2 , Ins ,A,B;f l o a t Vr ;f l o a t Va ;f l o a t I r ;f l o a t Ia ;i n t Vpv ;

//ADC Var iab l e s#de f i n e DMAX 9231i n t ADC Ipv a t t r i b u t e ( ( addres s (0 x850 ) ) ) ;i n t ADC Vpv a t t r i b u t e ( ( addres s (0 x852 ) ) ) ;

103

Appendix F. PV Emulator Microcontroller Source Code 104

//Current c o n t r o l l e r v a r i a b l e s#de f i n e K 1/2i n t IREF ;i n t Ik ;i n t Duty ;i n t Dpre ;i n t Dnew ;i n t e r r ;

//LUT f o r I−V ch a r a c t e r i s t i cuns igned char Ipv [ 2 5 6 ] ;uns igned char Ipv2 [ 2 5 6 ] ;i n t PVsel ; //0=CURVE1, 1=CURVE2

// I n i t i a l i z e f unc t i on suns igned i n t debounce B ( uns igned i n t bit num ) ;

i n t main ( void )

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ In t e r na l O s c i l l a t o r Conf i gurat i on∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗///Fosc= Fin∗M/(N1∗N2) , Fcy=Fosc /2 , Fin = 7.37 Mhz//Fosc= 7.37∗(43)/(2∗2)=80Mhz f o r Fosc , Fcy = 40MhzPLLFBD=43; // M = PLLFBD + 2CLKDIVbits .PLLPOST=0; // N1 = 2CLKDIVbits .PLLPRE=0; // N2 = 2

builtin write OSCCONH (0 x01 ) ; // New Os c i l l a t o r FRC w/ PLLbuiltin write OSCCONL (0 x01 ) ; // Enable Switch

whi le (OSCCONbits.COSC != 0b001 ) ; // Wait f o r new Os c i l l a t o r to become FRC w/ PLLwhi le (OSCCONbits.LOCK != 1 ) ; // Wait f o r P l l to Lock

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ I /O Port Conf i gurat i on∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/// Set AN0 and AN1, AN2 as analog inputADPCFG = 0xFFF8 ;

//PORT A − s e t analog p ins as inputsTRISA = 0x0000 ;TRISA |= BIT0 + BIT1 + BIT2 ;

//PORTB − s e t push buttons as inputsTRISB = 0x0000 ;TRISB |= PB START + PB SEL + BIT10 ;

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ PWM and ADC Clock Conf i gurat i on∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗///PWM and ADC Clock = ( (FRC ∗ 16) / APSTSCLR ) = (7 . 37 ∗ 16) / 1 = ˜ 120MHzACLKCONbits .FRCSEL = 1 ; //FRC prov ides input f o r Aux i l i a ry PLL ( x16 )ACLKCONbits .SELACLK = 1 ; // Auxi l i a ry O s c i l l a t o r prov ides c l ock sour ce f o r PWM & ADCACLKCONbits .APSTSCLR = 7 ; //Divide Aux i l i a ry c l ock by 1ACLKCONbits .ENAPLL = 1 ; //Enable Aux i l i a ry PLLwhi le (ACLKCONbits .APLLCK != 1 ) ; //Wait f o r Aux i l i a ry PLL to LockPWMCON1bits.CAM = 0 ; //Edge−Aligned ModePWMCON1bits.MDCS = 1 ; //Duty cyc l e sour ce = Master Duty Cycle r e g i s t e r

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ PWM Module Conf i gurat i on∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/PTCON2bits .PCLKDIV = 0 ; //PWM Pre s ca l e r s e t to 1

PTPER = 9616; //PWM Per iod PTPER = P des i r ed /( p r e s c a l e r ∗1.04 e−9)// P des i r ed = 10us , Fs = 100 kHz

MDC = 0 ; // I n i t i a l Duty Cycle s e t to 0IOCON1bits .PENH = 0 ; //PWM1H i s c on t r o l l e d by PWM moduleIOCON1bits .PENL = 0 ; //PWM1L i s c on t r o l l e d by PWM moduleIOCON1bits .PMOD = 0 ; // S e l e c t Complementary Output PWM mode

DTR1 = 0 ; //No Deadtime


ALTDTR1 = 0 ; //No ALTDeadtimePHASE1 = 0 ; //No phase s h i f t

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ADC Module Conf i gurat i on∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/ADCONbits .FORM = 0; // In t eg e r data formatADCONbits . EIE = 0 ; //Early In t e r r up t d i s ab l edADCONbits .ORDER = 0 ; //Convert odd channel f i r s tADCONbits .SEQSAMP = 0 ; // S e l e c t s imultaneous samplingADCONbits .ADCS = 0 ; //ADC clock = FADC/6 = 120MHz / 6 = 20MHz

IFS6b i t s .ADCP0IF = 0 ; //Clear ADC Pair 0 i n t e r r up t f l a gIPC27bits .ADCP0IP = 5 ; // Set ADC Pair 0 i n t e r r up t p r i o r i t yIEC6bits .ADCP0IE = 1 ; //Enable the ADC Pair 0 i n t e r r up t

ADSTATbits .P0RDY = 0 ; //Clear Pai r 0 data ready b i tADCPC0bits . IRQEN0 = 1 ; //Enable ADC Inte r r up t pa i r 0ADCPC0bits .TRGSRC0 = 4 ; //ADC Pair 0 t r i g g e r e d by PWM1 Tr igger

TRGCON1bits .DTM=0; //SINGLE t r i g g e r modeTRIG1bits .TRGCMP=0; //Primary t r i g compare value

TRGCON1bits .TRGDIV = 0x5 ; // Tr i gger generated every 6 th PWM cyc l eTRGCON1bits .TRGSTRT = 63; // enable Tr i gger generated a f t e r 63 PWM cyc l e sTRIG1 = 0 ; // Set ADC to sample at beginning o f sw i tch ing per i odSTRIG1 = 0x0000 ; // secondary t r i g compare value

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ PV I−V Curve Look−up−t ab l e (LUT) Generation∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗///PV Model ParametersVoc = 120 ; //Open c i r c u i t vo l tage (V)I s c = 4 . 7 7 ; // Short c i r c u i t cur r ent (A)Vmp = 90; //Maximum power point vo l tage (V)Imp = 4 . 5 ; //Maximum power point cur r ent (A)A = 0.88 e−3; // alpha − curent temperature c o e f f i c i e n t (amps/deg C)B = −0.172; // beta − vo l tage temperature c o e f f i c i e n t ( v o l t s /deg C)Tr = 25 ; // r e f e r e n c e temperature

//CURVE1 i r r a d i a n c e and temperature v a r i a b l e sIns = 0 . 8 ; // cur r ent i r r a d i a n c e input (0 = 0 W/mˆ2 , 1 = 1000 W/mˆ2)Ct = 25 ; // cur r ent temperature input ( deg C)

// Cal cu l ate C2 and C1 c o e f f i c i e n t s f o r CURVE1C2 = (Vmp/Voc − 1)/ l og (1 − Imp/ I s c ) ;C1 = (1 − Imp/ I s c )∗ exp(−Vmp/(C2∗Voc ) ) ;

//Generate PV panel LUT f o r CURVE1 us ing PV c e l l modelf o r (Vpv=0;Vpv<256;Vpv++)

Va = ( f l o a t ) (Vpv∗123/255) ; //8 b i t Vpv sensor value can measure 0 − 123 VVr = Va + B∗(Ct−Tr ) ;I r = I s c ∗(1−C1∗( exp (Vr/(C2∗Voc )) −1)) ;Ia = I r + A∗ Ins ∗(Ct−Tr)+( Ins −1)∗ I s c ;// Limit negat i ve cur r enti f ( ( f l o a t ) Ia <= 0)

Ia = 0 ;//Converter f l o a t r e s u l t to 8−b i t LUT value//8 b i t Ipv r e s o l u t i o n can output max of 6 . 37 AIpv [Vpv ] = ( uns igned char ) ( Ia ∗255/6 . 37 ) ;

//CURVE2 i r r a d i a n c e and temperature v a r i a b l e sIns = 0 . 5 ;Ct = 25 ;

// Cal cu l ate C2 and C1 c o e f f i c i e n t s f o r CURVE2C2 = (Vmp/Voc − 1)/ l og (1 − Imp/ I s c ) ;C1 = (1 − Imp/ I s c )∗ exp(−Vmp/(C2∗Voc ) ) ;

//Generate PV panel LUT f o r CURVE2 us ing PV c e l l modelf o r (Vpv=0;Vpv<256;Vpv++)


Va = ( f l o a t ) (Vpv∗123/255) ;Vr = Va + B∗(Ct−Tr ) ;I r = I s c ∗(1−C1∗( exp (Vr/(C2∗Voc )) −1)) ;Ia = I r + A∗ Ins ∗(Ct−Tr)+( Ins −1)∗ I s c ;i f ( ( f l o a t ) Ia <= 0)

Ia = 0 ;Ipv2 [Vpv ] = ( uns igned char ) ( Ia ∗255/6 . 37 ) ;

PVsel = 0 ; // S e l e c t CURVE1 i n i t i a l l y

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ Main Program Loop∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/whi le (1)

PORTA &= ˜LO DRV & ˜HI DRV; //Turn o f f gat ingPORTB &= ˜LED ON; //Turn o f f Status l ed

//Wait f o r START button to i n i t i a t e conver terwhi l e ( (PORTB & PB START) != 0)debounce B (PB START) ;

PORTB |= LED ON; //Turn on Status l ed

IOCON1bits .PENH = 1 ; //PWM1H i s c on t r o l l e d by PWM moduleIOCON1bits .PENL = 1 ; //PWM1L i s c on t r o l l e d by PWM modulePTCONbits .PTEN = 1 ; //Enable PWM

ADCONbits .ADON = 1 ; //Enable ADC and Current Cont r o l l e r

//Converter ON, wait f o r user to togg l e conver ter o f fwhi l e ( (PORTB & PB START) != 0)

//Push Button t o g g l e s CURVE1 or CURVE2 c h a r a c t e r i s t i ci f ( (PORTB & PB SEL) == 0)

i f ( PVsel == 0)

PVsel = 1 ;e l s e

PVsel = 0 ;debounce B (PB SEL ) ;

IOCON1bits .PENH = 0 ; //PWM1H i s c on t r o l l e d by PORTAIOCON1bits .PENL = 0 ; //PWM1L i s c on t r o l l e d by PORTAPTCONbits .PTEN = 0 ; // Di sab l e PWM

ADCONbits .ADON = 0 ; // Di sab l e ADC and Current Cont r o l l e r

PORTA &= ˜LO DRV & ˜HI DRV; //Turn o f f FET swi tchesdebounce B (PB START) ;

r e turn 1 ;

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ADC Inte r r up t Se r v i c e Routine and Current Cont r o l l e r Algorithm∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/void a t t r i b u t e ( ( i n t e r r u p t , no auto psv ) ) ADCP0Interrupt ( )

IFS6b i t s .ADCP0IF=0; //Clear ADC Inte r r up t FlagADC Ipv = ADCBUF0 − 0x0008 ; //Read inductor cur r ent s ensorADC Vpv = ADCBUF1; //Read output vo l tage sensor


Vpv = ADC Vpv/4 ; //LPF measured PV vol tage w/ b i t s h i f t

//Read LUT of CURVE1 or CURVE2 f o r I r e f at Vpvi f ( PVsel == 0)

IREF = ( i n t ) Ipv [Vpv ] ;e l s e

IREF = ( i n t ) Ipv2 [Vpv ] ;// Propor t i ona l Current Cont r o l l e rDpre = MDC;Ik = ADC Ipv /4 ;e r r = IREF − Ik ;Duty = er r ∗K;Dnew = (Duty+Dpre ) ;//Duty cyc l e l im i t e ri f ( ( i n t )Dnew <= 0)

MDC = 0 ;e l s e i f ( ( i n t )Dnew >= DMAX)

MDC = DMAX;e l s e

MDC = Dnew ;ADSTATbits .P0RDY = 0 ; // Clear the data i s ready in bu f f e r b i t s

/∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ PORTB Push Button Switch Debouncer∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗/uns igned i n t debounce B ( uns igned i n t bit num )

//Switch must be in steady high s ta t e f o r 10ms to be cons ider ed r e l e a s e di n t done = 0 ;uns igned i n t count = 0xFFFF ;whi le ( done == 0)

//Check i f push button pressed , r e s e t counteri f ( (PORTB & bit num)==0)

count = 0xFFFF ;e l s e

count−−;i f ( count==0)

done = 1 ;

r e turn 1 ;

resonantboostconverterfordistributedmaximumpower …...abstract resonant boost converter for...

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