Ramya Srinivasan GLOBALFOUNDRIES 22FDX: Tempus Body-Bias Interpolation QoR April 12 2017

22FDX: Tempus Body-Bias Interpolation QoR Presenter: Ramya Srinivasan Authors GLOBALFOUNDRIES: Haritez Narisetty and Venkat Ramasubramanian Cadence: Swamy Lokanadham

April 11-12, 2017 CDN LIVE: Silicon Valley

2

GLOBALFOUNDRIES 22FDx Technology

3

• What is 22FDX technology? • It is the new 22nm Fully Depleted Silicon-

on-Insulator (FDSOI) technology from GLOBALFOUNDRIES

• Delivers FinFET-like performance and power-efficiency at 28nm cost

• Software-controlled transistor body-biasing for flexible trade-off between performance and power

• Integrated RF for reduced system cost and back-gate feature to reduce RF power

• Enables applications across mobile, IoT and RF markets

Effects of Body Biasing in Bulk Transistor and FDSOI Transistor

Planar Bulk Transistor Planar FDSOI Transistor with “green” Insulator layer

Body-biasing Provides Greatest Design Flexibility

• Forward body-bias (FBB) enables low voltage operation

• Reverse body-bias (RBB) enables low leakage

• Dynamic body-biasing enables active tradeoff of performance versus power

• FDSOI variability is smaller across die due to lower doping effort

• Improve within die or die-to-die uniformity • Post-silicon tuning/trimming

4

-2V to +2V Body-Biasing

Body-Biasing

• Power/Performance Trade-off

5

Max Frequency

Reverse Body-bias (RBB)

Forward Body-bias (FBB)

Maximum Performance Operating Mode

Minimum Leakage In Standby Mode

GLOBALFOUNDRIES 22FDX Technology FBB versus RBB

• Bias voltage is applied to P-well and N-well

• Reverse Body Bias (RBB)

• raising VT of device • nMOS neg. substrate voltage,

pMOS pos. substrate voltage • Forward Body Bias (FBB)

• lowering VT of device • nMOS pos. substrate voltage,

pMOS neg. substrate voltage

6

What is body-biasing? A new dimension to design closure

• Substrate biasing is a low power technique • For tuning performance and static power consumption of a device

• Body-biasing applied through voltage variation on PWELL and NWELL terminal • Same implementation can be timed with different Bias voltages resulting in different

performance results • Different Body-Biasing domains on one chip are enabling new design architectures

and design styles • Due to the variation in Body Bias as a new variable, now the corners are PVTB

(Process/Voltage/Temperature/Body Bias)

7

PVT + BIAS PVTB Bulk Flow New Step

for 22FDX

Library Char +

LVF variability

Lib char with BB (Added

corners)

Body-Bias in Design Flow…. Concept of 22FDx Body-Bias Trimming

8

Design Post Silicon TRIM Block 1

FBB

Block 3 RBB

Block 2 FBB

Top

VNW = 0 VPW = 0

Slow parts VNW = 0 VPW = 0

• Design implementation performed at TT-FFG corner and STA is done at SSG with FBB to recover silicon dies that land in SSG material.

• Si Trimming currently focused to meet performance for silicon dies landing on SSG material

• FBB Blocks - Design to TT&FF

VNW=0+ VPW=0-

Body-Bias in Design Flow…. Concept of 22FDx Body-Bias Trimming • RBB Blocks - Design to TT&SS

9

Block 1 FBB

Block 3 RBB

Block 2 FBB

Top

VNW = 0 VPW = 0

Fast parts VNW = 0 VPW = 0

Post Silicon TRIM

• RBB Blocks get slower with increase in BB - RBB blocks need to be reverse biased to be able adjust fast/leaky parts to the spec using TRIM

VNW = 0+ VPW = 0-

Design

Design Methodology for BB Trim

10

Signoff/ECO with TRIM-BB-SS (interpolation/LVF),

TT (LVF) & FF (LVF)

Block

Design to TT & FF

Post silicon TRIM the SS parts with TRIM-BB-

SS

Identify the TRIM-BB to shift SS to TT.

Call it TRIM-BB-SS

• Process Control Monitor driven BB voltage generator

• Dynamic: Can use BB optimization on the spot after implementation (Interpolation in Tempus)

Design Chip VDD

VSS TRIM-BB-SS VNW, PWN

Process Contrrol Monitor

BB Gen

Body-Bias Interpolation in Tempus

• Body-Bias Flow • Library set creation using four libraries on the boundary at different bias-voltages using

the command create_library_set

• Power domain definition for the supply nets VDD, VNW and VPW • Operating condition definition for all the supply nets VDD, VNW, VPW using the command

create_op_cond • create_op_cond -name op_1 -P 1 -V 0.80 -T 25 -library_file TT_0P80V_0P00V_0P00V_0P00V_25C.lib • create_op_cond -name op_2 -P 1 -V -0.5 -T 25 -library_file TT_0P80V_0P00V_0P00V_0P00V_25C.lib • create_op_cond -name op_3 -P 1 -V 0.5 -T 25 -library_file TT_0P80V_0P00V_0P00V_0P00V_25C.lib

11

VNW

VPW

1,0 0,0

0,-2 1,-2

Lib1: 0.8v,25c (0v,0v)

Lib4: 0.8v,25c (1v,-2v)

Lib2: 0.8v,25c (0v,-2v) Lib3: 0.8v,25c (1v,0v)

Tempus Body-Bias Interpolation Flow

• STA Settings • Waveform propagation enabled • SI analysis turned off • PBA Mode • LVF libraries

• Tempus Tool Version: 16.20.000 • Tempus to Spectre Validation:

• Bias voltage scaling is validated with spice accuracy correlation for uncoupled path delay

• Bias scaling can be performed for any point on the surface (yellow points) • Blue points are pre-characterized points • Both delay and local variation interpolation supported in Tempus

12

Load UPF (has bias PG info)

Update timing and generate reports

Read netlist and link design

Library set creation and enable bias voltage scaling

Tempus STA Flowchart

VPW

1,0 0,0

0,-2 1,-2

VNW

Testcase Setup

• Testcase: data engine of 32 bit core • Cell-count: 150K (std-cells) • Setup Analysis with PBA mode • Forward-Bias Mode • Placement Utilization: 65% • Library: 8T CNRX • Metal Stack: 8M layers

13

Results-Delay Interpolation • Delay Interpolation at VNW:0.5V and VPW: -0.5V

14

1,0 0,0

0,-2 1,-2

VNW

VPW

0.5V,-0.5V

-30

-25

-20

-15

-10

-5

01 51 101 151 201 251 301 351 401

Abs

olut

e D

iffer

ence

in D

ata

Arr

ival

Ti

me

(in p

s)

Path ID

Data Arrival Time Comparison between Tempus and Spectre

Tempus to Spectre

-5

-4

-3

-2

-1

01 51 101 151 201 251 301 351 401

Perc

enta

ge D

iffer

ence

be

twee

n Te

mpu

s an

d Sp

ectr

e(in

%)

Path ID

Data Arrival Time Comparison between Tempus and Spectre

Tempus to Spectre

Results-Delay Interpolation

• Delay Interpolation at VNW:1.0V and VPW: -1.0V

15

1,0 0,0

0,-2 1,-2

1.0V,-1.0V

-4

-3

-2

-1

01 51 101 151 201 251 301 351 401

Perc

enta

ge D

iffer

ence

be

twee

n Te

mpu

s an

d Sp

ectr

e (in

%)

Path ID

Percentage difference in data arrival time

Tempus to Spectre

-30

-25

-20

-15

-10

-5

01 51 101 151 201 251 301 351 401

Abs

olut

e D

iffer

ence

bet

wee

n Te

mpu

s an

d Sp

ectr

e (in

ps)

Path ID

Abolute difference in data arrival time

Tempus to Spectre

Results—Tempus to Monte-Carlo

• Delay and Variation Interpolation at VNW:0.5V and VPW: -0.5V • Monte-Carlo simulations in Spectre with 5000 seed

16

1,0 0,0

0,-2 1,-2

VNW

VPW

0.5V,-0.5V

-4.1

-4.05

-4

-3.95

-3.9

-3.85

-3.8

-3.75

-3.71 2 3 4 5 6 7 8 9 10

Perc

enta

ge D

iffer

ence

bet

wee

n Te

mpu

s an

d Sp

ectr

e (in

%)

Path ID

Percentage Difference in Data Arrival Time

Tempus to Spectre

Conclusion

• Body-Bias algorithm works accurately in Tempus • Good correlation seen between Tempus to Spectre for delay and variation

interpolation • Some paths see correlation greater that 3%. Work in progress with

Cadence to improve correlation for the outliers • GLOBALFOUNDRIES will deploy body-bias scaling capability in

Tempus in digital reference flows • Future Work: GLOBALFOUNDRIES is working with Cadence to

include body-bias interpolation capability in upstream flows (Genus/Innovus) and power interpolation in Voltus.

17