qoriq product roadmap update and core...

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-

Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor

Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale

Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis,

Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play,

SafeAssure, the SafeAssure logo, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are

trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of

their respective owners. © 2013 Freescale Semiconductor, Inc.

Jeffrey Ho

March 2013

2

TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC,

Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet,

Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, Tower, TurboLink, Vybrid and

Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc.

3





• Overview

− QorIQ Portfolio Overview

− Market Overview

− Roadmap

− Enablement

• Core Comparison for e500 to e6500

• Product Details

− P5040

− T4240

− T2080

− T1042

• Summary

4





The industry-leading QorIQ processor portfolio offers advanced multiprocessing solutions for high-performance communications and computing for a smarter, more connected world.

Leading performance, power and scalability

5





5

• Leading innovation in networking architectures

− QorIQ: Broadest scalable family of processors in the

market

− Industry-leading integration, performance, power

• Increasing software investment

− Innovative Software-aware solutions

− Industry-leading virtualization support

• Strong enablement & ecosystem

− True programmability and Ease of use focus

− Rich set of reference designs and development platforms

• Trusted partner

− Longevity program

− Global support resources, quality, service

QorIQ T4240

T2080, T1042

QorIQ P10xx – P50xx

PowerQUICC

Host Processors

1-8 Core

CPU

2-24 Core

CPU

Service Provider Enterprise Consumer Access Industrial and Aerospace

6





Multiservice routers

WLAN access points

Ethernet switches

Security / UTM appliances

Home media distribution

Residential gateways

Small form-factor control systems

Factory & building automation

Machine to machine communications

Power protection

Medical imaging & networks

Aerospace communications, radar, sonar

Core routers

RNC

Edge routers

Central office / broadband access

Service Provider Enterprise/Data Center

Industrial & Aerospace SOHO / Consumer

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7





• The Internet of Things is fast becoming real

− Connected devices = 3x global population

− Global IP traffic will reach 1.3 zettabytes per year

• Tremendous growth in mobility

− 60% of users will generate 1GB+ traffic / month

− Traffic increase of 10x from 2011 to 2016

• Rapid growth in M2M communications

− Emergence of “new nodes”

− Projected 22x traffic increase

from 2011 to 2016

Source: Cisco Visual Networking Index (VNI)

zettabyte = 1021 bytes

8





• Elastic resources and services

− Multitenancy support

− Network optimizations for latency

• Changing application topology

− Emergence of specialized servers

− WAN optimization impacting productivity

• Growing importance of security

− Maintain seamless connectivity

− Ensure IT control & management

− Guarantee collaboration technologies

Mobile GPS

Touchpad

Notebook

Appliance

Home

Entertainment

9





2012 2013 2Q 3Q 4Q Existing 1Q 4Q

P3041

P2041/40

P1023/17

P1010/14

T4160

T4240

P1021/12

P1022/13

P2020/10

MPC8569

P4080/40

P5040

P5020/10

P5021

P1020//11

2014 2Q 3Q 4Q 1Q 2Q 1Q

LS1xxx

T1040/42

T2080

T2081

T1020/22

SDK 1.6 SDK 1.7 SDK 1.5 SDK 1.4 SDKs

SDK 1.3 Biannual

releases

LS1 Family

Next generation

High Performance

Mid Performance

Value Performance

LS3xxx

LS2xxx

Sample

Production

10





Virtualization 1.0

e500mc

Hypervisor layer

Platform

I/O MMU

I/O

DPAA for multi-core

simultaneous

access

Accelerators

DPAA for multi-core

simultaneous

access

Partitioning 1.0

Platform

Partitionable

Caches

Snoop domains

NG Core

Virtualized Interrupts

SW context-based QoS

Guest timers

Platform

I/O MMUv2 (4k paging)

PCIe RC SRIOv

Virtualized DMA

I/O

Partition based

buffer allocation

(Ethernet, SRIO)

2 x threads = SWP

External PCIe/SRIO

virtualization

I/O

Partition-able I/O

(SRIO, Interlaken)

PCIe EP SRIOv

Virtualization 1.1 Virtualization 2.0

Platform

Interpartition messaging

Dyn resource realloc

I/O

I/O Partition (Ethernet)

Accelerators

Inter-partition protection

Partition resets

P4080/P5020/P3041 T4240 Next Gen

Partitioning 1.1 Partitioning 2.0

Topaz HV

Linux/KVM

Linux Containers Linux/KVM

Linux Containers

11





Security Appliance WLAN EAP

Multiservice

Gateway

SmartNIC

Factory

Automation

12





New friendly development tools

PX-Series

PowerQUICC

QorIQ

Power on Tower MQX Operating System

QorIQ Configuration

& Optimization Suites

Online Selector Tool www.freescalewiki.com Beyond Bits

http://www.freescalewiki.com/

13





L2 Cache

T4240, T2080

CoreNet 2x BW

v6

L3Cache DDRC

v6 v6 v6

e6500

• e5500 plus

• Dual SMT Thread

• 2 load/store per core (1 per thread)

• 4 issue (2 decode/completion per thread)

• 2x wide fetch

• AltiVec

• Banked L2

• 2.0GHz in 28nm many core

L3Cache DDRC

• E500mc plus

• 64b ISA 2.06, 36b (64GB) per process

• Extended Branch Predictor

• Full speed DP FPU (classic)

• Larger L2

• 2.2GHz in 45SOI

P5040, P5021, P5020,

T1040

CoreNet

e5500 L3Cache

L2 Cache

DDRC

e5500

• E500v2 enhanced for multi-core

• Hypervisor, MMU TLB w/64 variable size

• DP FPU (classic), decorated L/S instructions

• CoreNet Coherency Fabric (2x snoop BW),

• L3 cache

• Up to 8 cores, 1.5GHz nominal

P40xx, P30xx, P204x

CoreNet

e500mc L3Cache

L2 Cache

DDRC

e500mc

• 32b PPC-E

• SS, OOO, DI, 7st

• SPE & EFPU

• ECM Bus & Platform L2

• Up to 2 cores, 1.5GHz nominal

e500 v2 L2 Cache

DDRC

MPC85xx, P10xx, P202x

e500v2

14





• Embedded Hypervisor support − Hypervisor privilege level − Allows SMP/AMP operation

without OS modifications

• Cache Enhancements − 32-Kbyte Data and Instruction

Caches w/ tag and data parity − Recovery from single-bit L1

errors w/ Write shadow mode − Back Side L2 w/ tag parity and

ECC data − 64byte cache lines − Cache intervention, stashing

and MESI cache coherency − Cache line locking supported

• Classic Double Precision FPU • Expanded interrupt model

− HW interrupt ACKs

• Interprocessor Signaling APU − Msgsnd instruction and

Doorbell interrupts

• Decorated Storage APU − Lockless Atomic updates of

shared counters and statistics

• Enhanced Debug Capabilities − NEXUS Level II ++

Data trace lite Enhanced trace filtering

− Performance Monitor Watchpoint triggering

Simple

Integer

Unit 2

CoreNet Bus Architecture 36-bit Address Bus 128-bit Rd & Wr Data Buses

Instruction Unit

CTR

LR

BTB

512 Entry

Branch Prediction Unit

Inst

Queu

e

Memory Unit

32-Kbyte I Cache

Tags

32-Kbyte D Cache

Tags

8-Entry

L1 VSP

64-Entry

L1 TLB 4K

L1 Instruction MMU

512-Entry TLB Array (TLB 0)

L2 MMU Load/Store Unit (64/32 bit)

Store

Queue

Load Miss

Queue

Data Line Fill

Buffer Data Write

Buffer

Fetch Stages

Backside L2

128K

Tag &

Status

Arrays

Data

Array

8-Entry

L1 VSP

64-Entry

L1 TLB 4K

L1 Data MMU

Complex

Integer

Unit

Simple

Integer

Unit 1

Classic

Single /

Double

FPU

CoreNet

Branch

Execution

Unit

GPR

Rename Buffers

FPR

• Power Architecture compatible

• Superscalar dual-decode, quad-issue: out-of-order execution/in-order completion

• 64 TLB SuperPages, 512-entry 4K Pages, 36-bit Physical Address

• Branch unit with a 512-entry, 4-way set associative Branch Target/History

• Three integer units: 2 Simple, 1 Complex for integer Multiply, Divide

64-Entry TLB Array (TLB 1)

Comp

Buffer

14 12

15





• 64-bit Power Architecture • Embedded hypervisor

support • Caches

− 32-Kbyte Data and Instruction Caches w/ tag and data parity

− Recovery from single-bit L1 errors w/ write shadow mode

− 512KB Back Side L2 w/ tag parity and ECC data

− 64byte cache lines − Cache intervention, stashing

and MESI cache coherency − Cache line locking

supported

• Classic Double Precision FPU − Faster FPU: 2X faster SP,

4X faster DP over e500mc

• New Power ISA v.2.06 Instr − instructions for byte- and bit-

level acceleration: Parity, population count, bit permute, compare bytes , FPU convert to/from 64-bit integer

• Enhanced Debug Capabilities

• 45-nm Technology • 2 GHz Implementation point • 20% DMIPS/MHz

improvement over e500mc

Simple

Integer

Unit 2

36-bit Address Bus 128-bit Rd & Wr Data Buses

Instruction Unit

CTR

LR

BTB

512 Entry

Branch Prediction Unit

Inst

Queu

e

Memory Unit

32-Kbyte I Cache

Tags

32-Kbyte D Cache

Tags

L1 VSP

64-Entry

L1 TLB 4K

L1 Instruction MMU

512-Entry TLB Array

(TLB 0)

L2 MMU Load/Store Unit (64/32 bit)

Store

Queue

Load Miss

Queue

Data Line Fill

Buffer Data Write

Buffer

Fetch Stages

L1 VSP

64-Entry

L1 TLB 4K

L1 Data MMU

Complex

Integer

Unit

Simple

Integer

Unit 1

CoreNet

Branch

Execution

Unit

GPR

Rename Buffers

FPR

• Superscalar dual-decode, quad-issue: out-of-order execution/in-order completion

• 64 TLB SuperPages, 512-entry 4K Pages, 36-bit Physical Address

• Branch unit with a 512-entry, 4-way set associative Branch Target/History

• Three integer units: 2 Simple, 1 Complex for integer Multiply, Divide

TLB Array (TLB 1)

Comp

Buffer

14 12

16





• 64-bit Power Architecture®

• 28nm technology

• Superset of e5500

• Two threads per core (SMT)

• Dual load / store units, one per thread

• Shared L2 in cluster of 4 cores (8 threads

per cluster) − 2048KB 16-way, 4 banks

− High-performance eLink bus between to

Ld/St and instruction fetch units

• Power − Drowsy core and caches

− Power Mgt Unit

− Wait-on-reservation instruction

• Enhanced MP Performance − Accelerated atomic operations

− Optimized barrier instructions

− Fast intra-cluster sharing

• AltiVec SIMD Unit

• CoreNet BIU − 256-bit Din and Dout data busses

• 36/40-bit Real Address − 1 Terabyte physical addr. space

• Hardware Table Walk

• LRAT − Logical to Real Addr. Translation

mechanism for improved hypervisor

performance

• Each thread: superscalar, seven-issue, out-of-order execution / in-order

completion, branch units with a 512-entry, 4-way set associative branch

target / history

• Execution units: 1 load / store unit per thread, 2 simple integer per thread,

1 complex for integer multiply & divide, 1 floating-point unit, AltiVec

technology

• 64 TLB superpages, 1024-entry 4K pages, 36 or 40-bit physical Address

17





18





Observation:

• Quad decode / dispatch

(2 per thread)

• Quad completion

(2 per thread)

• 14 issue (7 per thread)

• 12 execution units

19





Networking

Functions

Compute

Functions

20





Networking

Functions

Compute

Functions

21





Data Center Ethernet Switch Based Fabric

Management

&

Orchestration

Servers Storage

Network Services

Security

WAN Optimization

ADC/SLB

Monitoring

22





Requirement Freescale’s Approach

Data Virtualization

Single Address space shared by multiple tenants.

Configuration/Run time data on per tenant basis.

Support large number of tenants, but no isolation.

Process based virtualization

Set of processes dedicated to a tenant.

Efficient isolation and number of tenants support

Container based virtualization Similar to process based virtualization.

More isolation (file system, OS tunable, hostname)

Decent number of containers

Server Virtualization

KVM/QEMU based virtualization.

OS & Application instantiated for tenants.

Very good isolation, but only few VMs are possible

Hardware (Cores)

Core performance still matters

Focus on high performance, high IPC

Hardware (DPAA)

Leveraging data path for traffic management

Associations with tenancy

Hardware (Accelerators)

Access to accelerators with minimal overhead

Sharing of resources for performance

Software

Access to H/W + User space abstraction

Efficient use of resources

Target: Scalable & Efficient Performance

Multi Tenancy

23





High Performance I/O

Dual DDR3/3L 64-bit, 1600MT/s

Dual 10GbE 24Gbps Classify, Parse, Distribute

10x 1GbE

PCIe Gen2.0 3x PCIe controllers (5Gbps)

USB Dual with integrated PHY

IFC Legacy ASIC connectivity & modern flash controller

Serial Peripherals SATA, USB, UART, SPI, etc

24





Balanced Architecture

− High-performance cores – power efficiency

− Up to 64-bit addressable memory space

− Up to 2.4GHz with < 35W TDP

CoreNet On-chip Fabric

− Designed to “feed” the cores

− Eliminates bus contention

− Optimizes efficiency of each core

High Speed Interconnect

− PCIe, SGMII, XAUI, SATA, Aurora

Tightly Coupled Cache Hierarchy

− Optimum memory architecture

− Cores are closer to the data to reduce latency

Application-Specific Accelerators

− Provides optimum performance/power

− Security, Packet-processing offload, RAID5/6

Enterprise /

Service Provider

Equipment

Fabric

Controller

Storage

Networks

Aerospace

& Defense

The P5040 and P5021 embedded

processors were architected to provide

maximum benefit for the target markets

25





16-Lane 10 GHz SerDes

64-bit

DDR2/3

Memory

Controller

CoreNet Coherency Fabric

PAMU PAMU PAMU

Peripheral Access

Mgmt Unit

Security Fuse

Processor

Security Monitor

2x USB 2.0 w/PHY

IFC

Power Management

SD/MMC

2x DUART

2x I2C

SPI, GPIO

64-bit

DDR2/3

Memory

Controller

64-bit

DDR3

Memory Controller

64-bit

DDR3

Memory Controller

512KB

CoreNet

Platform Cache

512KB

CoreNet

Platform Cache

PAMU

Queue

Mgr.

Buffer

Mgr.

Pattern

Match

Engine

2.0

Security 5.0

64-bit

DDR2/3

Memory

Controller

64-bit

DDR3

Memory Controller

512KB

CoreNet

Platform Cache

RMAN

DCE

1.0

Parse, Classify,

Distribute

1/ 10G

1/ 10G

1G

1G

1G

1G

FMan

1G

1G

Parse, Classify,

Distribute

1/ 10G

1/ 10G

1G

1G

1G

1G

FMan

1G

1G

16-Lane 10 GHz SerDes

HiGig DCB HiGig DCB

Pre

-fe

tch

2MB Banked L2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

2MB Banked L2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

2 MB Banked L2

Power Architecture®

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power Architecture

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power Architecture

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power Architecture

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Watchpoint Cross

Trigger

Perf Monitor

CoreNet Trace

Aurora

Real Time Debug

Inte

rlaken L

A

SA

TA

2.0

SA

TA

2.0

PC

Ie

PC

Ie

2xDMA

sR

IO

sR

IO

PC

Ie

PC

Ie

26





Virtualization

Features Increased System Performance

with added Security

Co

re

Hypervisor

Cores have an extended address space and a

hypervisor privilege mode to provide system

security

Virtual CPU Allow guest operating systems to perform key

operations safely with zero overhead

Virtual CPU

MMU

Allows guest OS MMU management safely

with zero overhead

So

C P

latfo

rm

I/O MMU (PAMU) Mechanism to protect the system from

unauthorized I/O devices

DPAA Allows I/O peripherals, hardware accelerators

and security devices to be shared

Virtualization

Software

TM

27





Tie

red

AP

M H

iera

rch

y

• Run, Nap

• Dynamic frequency scaling

• Drowsy cluster

• Dynamic clock gating

• SoC sleep with state retention

• Cascading power management

• Drowsy DDR/ self refresh


• Energy Efficient Ethernet (EEE)

So

C

Clu

ste

r C

ore

• Run, Doze, Nap

• Wait

• AltiVec drowsy

• Core drowsy (state retention)


Cascading Power Management

TMU

T4240

Die temp

sensor

Die temp

sensor

Die temp

sensor

Thermal Management Unit

T T

32K

AltiVec

e6500

32K P

MC

2048KB Banked L2

PM

C

PMC

DPAA

Cache

DD

R

CoreNet

QMAN FMAN

28





Balanced Architecture

− High-performance dual threaded 64b cores

− Multicores up to 1.8GHz with 128b AltiVec

− Power Efficiency

− 4x performance of P4080 App Accelerators

− CoreNet On-chip Fabric

− Designed to efficiently “feed” the cores

− Eliminates bus contention

High Speed Interconnect

− Next gen PCIe, Multiple XAUI, Interlaken LA SATA, Aurora

Tightly Coupled Cache Hierarchy

− Optimum banked and tiered memory architecture

− Cores are closer to the data to reduce latency

High-Performance Virtualization

− Advanced Core and SoC

− Software solutions designed for AMP

Enterprise /

Service Provider

Equipment

Fabric

Controller

Storage

Networks

Aerospace

& Defense

The T4240 and T4160 AMP

Processors are architected to provide

Best in Class performance within an

embedded power envelope

29





High Performance Cores and Memory Subsystem

Power Architecture e6500 cores Up to 1.8 GHz

Dual threaded with 128-bit AltiVec technology

2 MB shared L2 256 KB per thread, low latency

512 KB platform cache Shared

DDR3/3L 64 bit + ECC, up to 2.1 GT/s, Memory pre-fetch engine

30





• Dual-threaded e6500 core

offers the highest

CoreMark/watt rating

• Fixed function acceleration

engines for application offload

• Secure Boot prevents box

hacking and software IP theft

• Advanced virtualization for

safe partitioning between

control and data plane

• AltiVec engine for DSP-like

calculations

Enterprise

Routers/Switches

UTM Security

Appliances

Mobile

Backhaul

Aerospace

& Defense

The T2080 embedded processor was

designed to provide maximum benefit

for mid-range applications

31





High Performance Core/Caches

Power Architecture e5500 core Up to 1.4 GHz

Hybrid 32-bit mode for legacy software support

256 KB/core L2 cache

256 KB platform cache Supports up to 64 GB addressability

32





• Highest performance CPU

cores in the power envelop

• Offload engines – industry

highest IPSec in its class

• Deep packet inspection offload

engine enabling UTM

applications

• DPAA – for QoS and balanced

networking performance

• Virtualization to support

customers and 3rd party

software

• Small form factor, fanless and

convection cooled designs

Enterprise

Routers/Switches

Industrial Computing

and Networking

UTM Security

Appliances

The T1042 embedded processor was

architected to provide maximum

performance per watt

33





P4080

T1042

P3041,

P2041

T2080

Lower

power 2x

performance

increase in

same power

range

Lower

power

Inc

rea

sin

g P

erf

orm

an

ce

Decreasing Power (Watt)

P1020

P2020

2x

performance

in same

power range

34





Tools and

Operating Systems Application

Software Virtualization Systems

Integration & Services Development

Systems

35





• Best-in-class execution on QorIQ Industry leading reach and transparency.

• Exciting roadmap for the future Leadership in multicore for the next 10 years.

• Infrastructure to accelerate your design reference designs, collateral, new

exciting products!

Freescale is leading innovation in next-generation

network infrastructure

qoriq product roadmap update and core...

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