pt lab1 flow

7/24/2019 PT Lab1 Flow

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Introduction to STA using PT 1-1Synopsys 34000-000-S36

Given the design, library and script files, your task will be tosuccessfully perform STA using the PrimeTime GUI andgenerate reports.

After completing this lab, you should be able to:

Add index(es) to ease searching of information in SOLD

Invoke PrimeTime GUI and perform 4 STA steps:READ, CONSTRAIN, CHECK and ANALYZE

Analyze the designs timing using the 4 GUI windows:Histogram, Path profiler, Schematic viewer andWaveform viewer

Generate and interpret timing and constraint reports

Report cell and net delay calculations

Introduction to STAusing PT

UNIT

60 minutes

Unit 1

Learning Objectives


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Lab 1

1-2 Introduction to STA using PTPrimeTime: Introduction to Static Timing Analysis

Getting Started

Directory structure and relevant files

../Libs/ Directory with Library files

core_slow.db Cell library for setup check

Lab1_Intro/ Directory to perform this lab

.synopsys_pt.setup PrimeTime Setup

Scripts/ Scripts directory

1_read_design.pt Read a design into PT

2_constrain_design.pt Constrain the design read in

3_check_design.pt Check constraints completeness 4_timing_analysis.pt Perform STA to generate reports

Source/

Verilog/ Verilog design directory

RISC_CORE*.v Top level netlist

Reports/ Reports directory

$SYNOPSYS/ Root install directory

doc/online/static STA documentation directory

index.pdx Index file

If you need help

Use the lecture material, SOLD or the Quick Reference Guide or ask yourInstructor.


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Introduction to STA using PT 1-3PrimeTime: Introduction to Static Timing Analysis

Introduction to STA using PrimeTime

Add Search index(es) to SOLD

Invoke PT and verify setup

READ, CONSTRAIN and

CHECK

ANALYZE Graphically

Generate Timing, Constraint and

Delay Calculation reports

Your goals are to:

-

Perform STA on the given design using the Histogram, Pathprofiler, Schematic and Waveform windows of PrimeTime GUI

- Generate STA reports for analyzing the Timing, Design Rules andNet and Cell delays


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Lab 1


Background

You are provided with the gate level netlist of a design, library, a setup file, aset of script files and the online documentation (SOLD)

The Unix directory for this entire lab is ./Lab1_Intro.

Answers to the Questions are located at the end of this lab forcomparison

Task 1. Open SOLD and add search index

You need to have Adobe Acrobat Reader to see and search the contents ofSOLD. For this lab the Acrobat Reader is already installed. If you do nothave the Acrobat Reader, you can download one from http://www.adobe.com.You need version 4.05 or newer for the Sun Workstation, or 5.05 or newer for

the PC.

1. Change directory and list the contents

Unix> cd $SYNOPSYS/doc/onlineUnix> ls l

NOTE: If the online documentation is not installed for you (OR) if youcannot locate the top.pdf file, skip this task and move onto Task-2. Youmay be able to revisit this task at a later time.


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2. Opening SOLD

Unix> acroread top.pdf

This window appears:


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Click on PrimeTime, the following window will appear.

3. Search using Contents window:

In the window above, click on PrimeTime User Guide: Fundamentals,then click on Contentsin the left side window. The window bellow will

appear. You can scroll this window up or down to do your search.


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4. Search using Index window:

Click on the Index in the left side window (see picture above). Youwill see the window below:

Scroll down the Index window (right side window), look for clock, then lookfor transition time.

5. Search using key word:

You need to make sure you have the proper index installed to do searches.

To install the index, click on:

Edit --> Search --> Select Indexes


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Edit --> Search --> Select Indexes opens a Index Selection window:

6. Click on Add

The Add Index window will appear:

7. Double click on one directory, for example: /release/2002.03/doc/online/vcs .Double click on index.pdx (on the right side window).


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An Index Selection window opens

If the box to the left of an index is pushed in, the index is enabled. The

boxes not pushed in are disabled. Click the box to toggle between enableand disable. The search will be done using the indices that are enabled.

8. Search using key word:

Click EditSearchQuery

Type timing reports in the search window, then click Search.


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The Search Results window will appear.

9. Click on one title and click on View to see the contents.

After viewing an article, you can reopen this Search Result window byclicking EditSearchResults. If any of the search results do not let yousee the corresponding document, then you have to add and enable a new indexor indices and perform the search again.


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Task 2. Invoke PrimeTime GUI and Verify Setup

1. Invoke PrimeTime from the Lab1_Introdirectory.

unix% cd Lab1_Intro

unix% primetime &

It will take a few moments for the GUI to show up. Familiarize yourself withthe following key areas of the GUI:

Pull down menu options (Ex: File, View, Design, ...)

Quick Icons or radio buttons (Ex: STOP button)

Scoreboard (Ex: Current Design, Linked, Timed, PVT, ...)

Console Display area (occupying most area of the GUI)

Command line interface (primetime> (OR) pt_shell> prompt)

2. From the GUI pull down menu, verify that the Search and Link paths areconsistent with that of the .synopsys_pt.setup file. Click OK once done.

GUI: File -> Search and Link Path

unix% more .synopsys_pt.setup

Question 1. What directories are available under search_path?...............................

Question 2. What are the 2 items of link_path? .......................................................


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Task 3. READ, CONSTRAIN and CHECK

1. Read the Verilog design netlist using the script provided.

GUI: File -> Run Script

Run Script: Browse ..

Run Script File: Scripts 1_read_design.pt Open

Run Script: Select Echo Command and Verbose OK

Question 3. Is design RISC_CORE successfully linked? ........................................

Question 4. What is theCurrent Designname from the Scoreboard? .....................

Question 5. Is the design state Linked and/or Timed ? .....................................

2. Constrain the design by specifying a clock period of 2.5 ns (400 MHz).Instead of using the provided script, do this interactively.

GUI: Attributes -> Clock -> Create

Create Clock: Browse ..

Hierarchy Explorer: Double Click on Clk OK

Create Clock: Enter 2.5 for Period OK

Question 6. What pt_shell command has been executed?........................................

3. Use the man page to look at the details of the above command.

GUI: Help -> Man Pages

Manual Page: create_clock OK

4. Verify that you sufficiently constrained the design using the clock periodalone. Do this step using the command line interface:

pt_shell> check_timing -verbose

Question 7. Are there any Warnings or Errors? .......................................................

Question 8. Are there any changes to the Scoreboard?............................................


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Task 4. Analyze the design using GUI

1. Analyze the design timing using the Endpoint slack Histogram.(Search for Endpoint Slack Histogram in SOLD)

GUI: Reports -> Histograms -> End Point Slack

Endpoint Slack: OK (accept the defaults)

Question 9. How many (out of 8) bins violate timing (Red)? .................................

Question 10. Where do you find Worst slack, To the left or right most side ofthe X axis ? ........................................................................................

Question 11. How many endpoints are contained in the worst violating bin? ......... (Hint:Click on the bin and note the number from bottom of the GUI)

Question 12. What is the largest amount of Negative slack in the design?.............. (Hint:Look at the Top most Endpoint on the Right Hand window)

Question 13. Does the above agree with the Scoreboard reading? ..........................

2. Display the Path Profiler. (To invoke Path profiler, you need to start with theHistogram)

Histogram: Click on the Worst violating endpoint

Histogram: Window -> Create Path Profiler

Question 14. How many higher level modules (partitions) does the Timingpath pass through? .............................................................................

Question 15. Which module in the path causes the maximum delay? ....................

Question 16. How many libraryleaf cells are present in each module?................... (Double Click Module Use Up arrow icon to go back)

Question 17. In I_ALU, which library leaf cell causes the largest percentageof delay?.............................................................................................


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3. Display the Schematic Window (You can invoke it from the Histogram or thePath Profiler).


Histogram: Window -> Create Schematic Viewer

Question 18. What is the Start point of the timing path (input port or register)?......... (HINT: Simply place the mouse at the start point and look for an yellow info tip box)

Question 19. What is the End point of the timing path (output port or register)?.... (HINT:If you do not see an yellow info tip box, then look at the lower left

corner for the end point name)

Question 20. How many combinational library cells (do not count anyregisters) are present on the timing path? ..........................................

4. Display the Waveform Window (you can invoke it from the Histogram or thePath Profiler).


Histogram: Window -> Create Waveform Viewer

Question 21. How many waveforms are displayed? ................................................

Question 22. Do the start and end points agree with that of Schematic viewer? .....

Question 23. What is the path delay? .......................................................................

Question 24. What is the slack? ...............................................................................

Question 25. What is Registers setup time requirement? .......................................

Question 26. Is there a timing violation? .................................................................

You may now close all EXCEPT the PrimeTime Console window.

Note: (If you accidentally quit from the Console, you will need to redo Tasks 2 and3 before going to Task 5)


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Task 5. Generate Reports

1. Generate the Setup timing report from the command prompt:

pt_shell> report_timing

Question 27. What is the Data arrival time? ............................................................

Question 28. What is the Data required time?..........................................................

Question 29. What is the Clock period?...................................................................

Question 30. What is the slack? Is it MET or VIOLATED?...................................

Question 31. What is the register CLK to Q delay?.................................................

Question 32. What is the library setup time ? ..........................................................

2. Generate the hold timing report by typing the command:

pt_shell> report_timing delay min

Question 33. What is the Data arrival time? ............................................................

Question 34. What is the Data required time?..........................................................

Question 35. What is the slack? Was it MET or VIOLATED? ..............................

Question 36. What is library hold time?...................................................................

3. Generate a constraint report:

pt_shell> report_constraints

Question 37. What 2 design rules are checked in the library? .................................


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4. Generate reports to explain the delay calculations of cell and net delays.

To generate the report, you need to know the start and end points of

cells and nets. Note:the net delays are very small, you need at least 4

significant digits to see non zero net delays.

pt_shell> report_timing input_pins significant 4

Question 38. Why is every library cell name on this path shown twice?.................

Question 39. What is the longest cell delay on this path?........................................

5. Choose the CLK to Q cell delay arc and report its delay calculation:

HINT: To copy text from the Console into the command prompt, select thetext using left mouse click; to paste into the command prompt, use the right

mouse click and then select Paste with a left mouse click. Its more easilydone, than said

pt_shell> report_delay_calculation from \

I_DATA_PATH/Oprnd_B_reg[3]/CLK to \

I_DATA_PATH/Oprnd_B_reg[3]/Q

Question 40. What are the CLK2Q delays for rise and fall?....................................

Question 41. What are the rise and fall output transitions of this register?..............

6. Choose the net that ends at the D0 pin of the register (end point):

pt_shell> report_delay_calculation from \

I_ALU/U537/Y to \

I_ALU/Zro_Flag_reg/D0

Question 42. What is the net delay during rise or fall? ............................................


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Task 6. Quit Primetime

1. Exit PrimeTime GUI

GUI: File -> ExitPrimeTime: OK (for Exit PrimeTime?)

CONGRATULATIONS! Give yourself a pat on the back. You have just conductedSTA on the RISC_CORE design using PrimeTime.

Back to the lecture


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Answers for Lab 1

Task 2. Invoke PrimeTime GUI and Verify Setup

Q 1. What directories are available under search_path?

. ./Libs ./Scripts ./Source/Verilog

Q 2. What are the 2 items of link_path?

* core_slow.db

Task 3. READ, CONSTRAIN and CHECK

Q 3. Is design RISC_CORE successfully linked?

Yes

Q 4. What is theCurrent Designname from the Scoreboard?

RISC_CORE

Q 5. Is the design state Linked and/or Timed?

Linked

Q 6. What pt_shell command has been executed?

create_clock

Q 7. Are there any Warnings or Errors?

Yes, there are 2 warnings. The input and output ports have not been

constrained. Clock period constrained ONLY the Register to Registerpaths. This is OK for this lab.

Q 8. Are there any changes to the Scoreboard?

Yes, the design has been Timed (due to an update_timing invoked

by check_timing) and the Worst case setup violation in the design is1.2919 ns


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Task 4. Analyze the design using GUI

Q 9. How many (out of 8) bins violate timing (Red)?

3

Q 10. Where do you find worst slack, to the left or right most side of the Xaxis?

Left

Q 11. How many endpoints are contained in the worst violating bin?

127

Q 12. What is the largest amount of Negative slack in the design?

1.291897

Q 13. Does the above agree with the Scoreboard reading?

Yes

Q 14. How many higher-level modules (partitions) does the Timing pathpass through?

2 (DATA_PATH, ALU)

Q 15. Which module in the path causes the maximum delay?

ALU (82%)

Q 16. How many libraryleaf cells are present in each module? (Double ClickModule Use Up arrow icon to go back)

1 in I_DATA_PATH, 13 in I_ALU

Q 17. In I_ALU, which library leaf cell causes the largest percentage of

delay?

and6a6, 12.32%

Q 18. What is the Start point of the timing path (input port or register)?

Register Oprnd_B_reg[3] (fdesf1a9)


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Q 19. What is the End point of the timing path (output port or register)?(NOTE:If you do not see an yellow info tip box, then look at thelower left corner for the end point name)

Register Zro_Flag_reg (fdesf1a9)

Q 20. How many combinational library cells (do not count any registers) arepresent on the timing path?

13

Q 21. How many waveforms are displayed?

2 (Data arrival time and Data required time)

Q 22. Do the start and end points agree with that of Schematic viewer?

Yes

Q 23. What is the path delay?

3.4 ns

Q 24. What is the slack?

1.3 ns

Q 25. What is Registers setup time requirement?

0.4 ns

Q 26. Is there a timing violation?

Yes, -1.3 ns

Task 5. Generate Reports

Q 27. What is the Data arrival time?

3.43 ns

Q 28. What is the Data required time?

2.14 ns


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Q 29. What is the Clock period?

2.50 ns

Q 30. What is the slack? Was it MET or VIOLATED?

1.29 ns (VIOLATED)

Q 31. What is the register CLK to Q delay?

0.62 ns

Q 32. What is the library setup time?

0.36 ns

Q 33. What is the Data arrival time?

0.22 ns

Q 34. What is the Data required time?

0.11 ns

Q 35. What is the slack? Was it MET or VIOLATED?

0.11 ns (MET)

Q 36. What is the library hold time?

0.11 ns

Q 37. What 2 design rules are checked in the library?

max_capacitance and max_transition

Q 38. Why is every library cell name on this path shown twice?

Once to show the input pin of the cell, another to show the output pinof the cell

Q 39. What is the longest cell delay on this path?

CLK to Q


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Q 40. What are the CLK2Q delays for rise and fall?

0.617072ns , 0.536889 ns

Q 41. What are the rise and fall output transitions of this register?

0.319435 ns, 0.18629 ns

Q 42. What is the net delay during rise or fall?

9.02512e-05 ns

The End of Lab-1

pt lab1 flow

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