Project Part 1 A

Circuit Description and Diagrams:

The task was to design a 4 to 1 multiplexer that uses 8 – bit buses on the inputs with an output of

a single 8 – bit bus.

Shown below is a jpeg screenshot of the task completed.

As shown in the picture, there are four 8 - bit buses labeled A – D. Each of the 8 - bit buses are

connected to its respective location on the 4 to 1 multiplexer with the multiplexer connected to

the output vector labeled “Output”.

Function of 4 to 1 multiplexer:

The manner in which the multiplexer works is that the output of the vector “Output” is a number

in decimal format that is computed by the addition of the bits (For example 2^N + 2 ^ N, where

N is the selected bit) that are 1’s in the selected 8 - bit bus. 8 - bit buses are selected depending

on the combination of the selectors (S0 & S1).

To give a visual, a truth table is provided below to provide all possible combinations of the

selectors with the output vector labeled “Output” being the 8 - bit bus chosen labeled by a letter.

A similar truth table can also be found on section 3.9 page 151 of Morris Mano’s book, Logic

and Computer Design Fundamentals: 4th

Edition.

S1 S0 Output

0 0 A

0 1 B

1 0 C

1 1 D

Another way to visualize the truth table above is by the equation provided by the book on page

151.

Y = (~S1) (~S0) A + (~S1) (S0) B + (~S1) (S0) C + (S1) (S0) D

To give an example of the output, let us look at the truth table above. If S1 and S0 are turned on,

then the 8 - bit bus labeled D is the one chosen to be computed with the 4 to 1 multiplexer. If the

8 - bit input bus D shows 10 then the output must be 10. The 10 that is displayed by the 8 - bit

input bus D is computed by the addition of single bits that are turned on in the 8 - bit bus.

So like in my example, if 10 is displayed, then D1 and D3 are turned on. With D1 and D3 turned

on, the addition is as follows

(2^1) + (2^3) = 2 + 8 = 10.

The following picture shows a visual of the example from the last page.

Below is a visual displaying the 8 - bit input bus C showing 131 which is computed by the bits

C0, C1, and C7 added.

So as stated above…

(2 ^ 0) + (2 ^ 1) + (2 ^ 7) = 1 + 2 + 128 = 131

NOTE: Selectors S1 is on and S0 is off in order for 8 bit C bus to display its output.

Although D is still displaying the number 10 only the input bus C is shown on the output because

S1 is turned on and S0 is off. Look back at the truth table on page 2 of this report to confirm.

Sub design Diagram(s): I created a total of 4 sub designs. First is the 4 to 1 MUX,

which is shown below.

Second, is the decoder which was taken directly from section 3 – 9 page 151 from Mano’s book.

In short, the decoder chooses which output (1 – 4) to be selected depending on the combination

of the selectors.

Third is the AND sub design.

NOTE: This is a custom AND gate which takes in an 8 - bit bus as an input then expands it. With

the bits expanded, each bit is anded with the selector. The basic AND gates are then connected to

its respective location in the merge bit bus which is then connected to an output vector. 4 of these

AND sub designs are used within the 4 to 1 MUX. The idea to do this was by my own intuition

but also with help from the single bit 4 to 1 multiplexer diagram on page 151 in Mano’s book.

Lastly is the OR sub design. *Design is messy*

NOTE: This is a custom OR gate that acts exactly as the 4pin OR gate inside the 4 X 2 AND-

OR displayed in Mano’s book on page 151. In the case of an 8 - bit input buses; each input

vector is expanded with each bit connected to its respectful place. If you notice in the picture

below, every 4 pin OR gates has their own purpose. The bottom most 4 pin OR gate ors A0, B0,

C0, D0; the second OR gate ors A1, B1, C1, D1, and so on. The output should be the same as the

input.

Waveforms: Waveforms provide a verification of the design on whether it is properly

working.

Following is the waveform for the 4 to 1 MUX sub design. Only 4 inputs were chosen at random

for each 8 - bit bus for accuracy. As long as the inputs match the output, the MUX works.

NOTE: Disregard the UUU shown in the output after every 3 inputs, Hades resets the output

vector to not initialized after the combination of enablers changes.

Following is the waveform for the AND sub design. The chosen inputs were from 0 to 7. Again,

as long as the input matches the output while the enabler is turned on then this sub design works.

NOTE: Not sure why Hades decided to color the wave forms black but the above shows correct

waveforms for the enabler being on for a particular 8 - bit bus with the input showing as the

output which shows verification of working AND sub design.

Next, is the wave form for the Decoder sub design.

NOTE: The little vertical rectangular spike a little after 13.0 is Hades acting up. That spike

should not be there, but the rest of the waveform itself satisfies the truth table on section 3 – 9,

page 150 of Mano’s book.

The last waveform to show is of the OR sub design. The OR sub design waveform needed all

input vectors to start at 0 in order for the output to get initialized but this is not needed for the

multiplexer overall. I decided to just test the first 6 powers of 2(7 wouldn’t fit well on Microsoft

word) on the C input bus. As long as the inputs match the outputs, there was no need to further

test anything.

Project Part B

Circuit Description and Diagram:

The task was to design an 8 bit adder with two 8 – bit values as input, and a single 8 bit value

produced as a result.

Below is a picture of the completed task.*Messy but works nonetheless.* Bit A0 and B0

correspond to the bottom 1 bit adder design, A1 and B1 correspond to second to bottom and so

on.

As shown in the picture above, there are two 8 - bit vectors labeled A and B with a single 8 - bit

output vector along with a Carry_In and Carry_Out.

Function of the 8 - bit adder:

The function of the 8 - bit adder is to perform the sum of 8 - bit input bits. The adders will add

the bits from each 8 - bit input and sum both 8 - bit inputs to display an output.

Page 170 of Mano’s depicts both an equation and truth table of a single bit full adder.

S = (~X) (~Y) (Z) + (~X) (Y) (~Z) + X (~Y) (~Z) +XYZ

X Y Z C(Carry In) S(Sum)

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

So for example if A = 25 and B = 14 then the sum should be 39. Looking at the picture below

should confirm this.

Sub design Diagram(s):

Only 1 sub design was used for the 8 - bit adder. That sub design was the full adder used in the

mini project shown below. This full adder adds the 3 inputs (A + B + Carry_In) with S as the

Sum and Carry_Out as the output that displays whether or not there is a carry bit.

Following is the sub design of the single bit full adder.

Waveforms:

As with project part A, a waveform is needed for the circuit and any sub designs in order to

verify that the final product is actually working.

Only 2 wave forms need to be shown, the sub design full adder used in the mini project and the

entire 8 bit adder itself. Below is the waveform of the single bit full adder.

NOTE: I decided to go through every possible input shown in the truth table on page 9 of this

report.

The following waveform on this page pertains to the entire 8 bit adder.

NOTE: I used the example used in the Circuit Descriptions and Diagrams along with a carry in.

With A = 25 B = 14 along with a carry in (No Carry Out should be on); the sum should be 40.

The waveform below confirms this.

References

1. Mano, M. Morris., and Charles R. Kime. Logic and Computer Design Fundamentals.

Upper Saddle River, NJ: Pearson Prentice Hall, 2008. Print.