Project 1 Report Part 1A

This is my 4 to 1 Multiplexor that I based off the example we had in lecture for week 4 day 2 where the 8 bit bus was implemented into the mux.

The first column consists of the 8 bits pertaining to input ‘A’ where each bit has its own enable to easily control which bit can be selected. Each

bit is connected to an AND gate that requires both the bit and the enabler to send a 1 signal. The Second column has all the bits for ‘B’; the third

column pertains to ‘C’ and the last to ‘D’. What I love about this design is that I am able to turn on all the bits, but as long as the enabler to each

bit isn’t on, then nothing gets sent through. To test this design, I used the truth table used in the Logic and Computer Design Fundamentals book

on page 132. According to the truth table, depending on which selector is on, only one of the inputs from A, B, C or D can go through the mux.

This happens because of the way the mux is designed as it has to selectors that run through it that select which of the four bits can go through.

This picture above depicts the inside of the 4:1 box that you see on the complete 4 to 1 mux that I built on the first page. I got the design for this

example from the Logic and Computer Design Fundamentals book on page 133. This picture helps me describe a bit more of how the 4 to 1

multiplexor works. The two selectors above control the flow of the four inputs below them. When the selectors are both zero, the inverters that

they are both connected to change the signal to 1. This triggers the first AND gate to send a signal of 1 through it because both inputs are 1. The

first AND gate in the second column also sends a signal of one because it receives a 1 signal from the bit ‘A’ as well as the 1 from the AND gate

triggered by the two selectors that were inverted by the inverters. The signal keeps going through until it reaches the output pin because the

next two gates are OR gates which take which ever input has an input value of 1. When S0 has a signal of 1, it cancels the first AND gate and

triggers the second one which allows for the signal of ‘B’ to go through. When S1 has a signal of 1 and S0 has a signal of 0, it cancels the first two

AND gates and triggers the third AND gate which allows for the ‘C’ signal to go through. When both selectors are 1, the fourth AND gate is

triggered and the ‘D’ signal is able to go through this time. The waveform below explains it a bit more.

The only difference with the multiplexor that uses 8 bit busses as inputs is that it sends 8 bits as an input and as an output. What I noticed when I

was testing the 8 bit Mux is that depending on how many bits I send through it, it displays the output as a decimal. So if I turned on bits A0 and

A1 plus their enablers then the output gives me a decimal of 3 because the input I placed was the input 00000011 which is binary for the decimal

3.

Part 1B

This is my 8 bit adder which I built using sub designs of my 1 bit adder that I designed for the mini project we did in lab on week 1. The design for

the way I built the 8 bit adder I kind of got from the lecture notes on week 4 day 1. What I love about my design is that it’s not a giant clump of 1

bit adders all on one screen and instead it has them in sub designs. Had I not done it this way, then it would have been harder to read and to

follow. The pictures below show my 1 bit adder and the wave form for it.

In designing and testing my 1 bit adder, I turned to the book for help. In chapter 4 of the Logic and Computer Design Fundamentals there is an

example of a 1 bit adder and a truth table to test it. The way the adder works is that it does the sum of the three inputs and the reason that

there are two outputs is because one is the total of the sum and the other is the carry of the sum if there is an extra sum of more than 1. The

only difference with the 8 bit adder is that it adds the 3 bits of each separate adder and creates 8 outputs of their own sums and each carry is

carried over from one adder to another to connect all of them together.