• Programmable System on Chip

• Fully Configurable Mixed Signal Array

• Allows for Completely Customizable System Designs

• Capable of Internal MCU

• Minimum operating voltages– 24MHz - 5V +/- 5% (4 MIPs)– 12MHz - 3V +/- 10%

• Harvard Architecture• Efficient Addressing Modes

– Source and Destination addressing • Direct logical operations to memory or

I/O ports– Support Immediate, Direct and Indexed

modes for efficient use of table and array structures

Full Features

Note: 4 other pin-out configurations available (28, 44, two different 48, and a 100 pin)

Instruction Set

• CISC style instructions– 1, 2 and 3 byte instructions– 4 to 13 CPU cycles per instruction (6 average)– Predominately memory <--> register– also memory <--> memory and register <--> register

• First byte encodes:– Function and address mode or– Function and first nibble of address

• Major Groups– Data Movement– Arithmetic– Logical / Test– Program Flow

Registers

• Accumulator, A, 8-bits

• Index Register, X, 8-bits

• Stack Pointer, SP, 8-bits

• Program Counter, PC, 16-bits

• Flags, F, 8-bits– Zero, Carry & Interrupt Enable: Z, C & IE– Address Extensions XA, XIO and Super

Development/Design

• PSoC Designer (Free Development Software)• Two viewable versions of the system available in the GUI-IDE

– Device Editor (Physical Design Editor)– Application Editor (Code Editor)– Debugger view also included in the PSoc Designer Software– In-Circuit Emulator (ICE) allows for easy access to registers and other

program information• Allows for dynamic, simplified development and changes in

development and design• Analog and Digital Blocks allow developer to dynamically custom

build PWMs, ADCs, DACs, etc• Assembly Compiler (Ready to use)\• Fully supports C Compiler custom built by Imagecraft (additional

license required)• Cost

– Cost of Basic Dev. Kit: $398 (w/out C Compiler License)– C Compiler Cost: Additional $145

• Full support of products available on Cypress’ Website– Several PDFs available