programmable logic devices

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1/2550 A. Yaicharoen 1 Programmable Logic Devices

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Programmable Logic Devices. General structure of PLDs. Buffer/inverter. ( a ) Symbol ( b ) Logic equivalent. Programming by Blowing Fuses. ( a ) Before programming ( b ) After programming. PLD Notation. - PowerPoint PPT Presentation

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Page 1: Programmable Logic Devices

1/2550 A. Yaicharoen 1

Programmable Logic Devices

Page 2: Programmable Logic Devices

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General structure of PLDs

Page 3: Programmable Logic Devices

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(a) Symbol (b) Logic equivalent

Buffer/inverter

Page 4: Programmable Logic Devices

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(a) Before programming (b) After programming

Programming by Blowing Fuses

Page 5: Programmable Logic Devices

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(a) Unprogrammed and-gate (b) Unprogrammed or-gate (c) Programmed and-gate realizing the term ac (d) Programmed or-gate realizing the term a + b (e) Special notation for an and-gate having all its input fuses intact (f) Special notiation for an or-gate having all its input fuses intact (g) And-gate with nonfusible inputs (h) Or-gate with nonfusible inputs

PLD Notation

Page 6: Programmable Logic Devices

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Types of PLDs

• Programmable ROM (PROM) Fixed AND-array, programmable OR-array

• Programmable Logic Array (PLA) Programmable AND-array and OR-array

• Programmable Array Logic (PAL) Programmable AND-array, Fixed OR-array

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Structure of a PROM

Page 8: Programmable Logic Devices

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A 2nm PROM

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Using a PROM for logic design

Page 10: Programmable Logic Devices

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Logic diagram of an n p m PLA

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Page 13: Programmable Logic Devices

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Example of combinational logic design using a PLA. (a) Maps showing the multiple-output prime implicants. (b) Partial covering of the f1 and f2 maps. (c) Maps for the multiple-output minimal sum. (d) Realization using a 3 4 2 PLA.

Example

Page 14: Programmable Logic Devices

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(a) Circuit diagram. (b) Symbolic representation.

Ex-Or-gate with a Programmable Fuse

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General structure of a PLA having true and complemented output capability

More on PLA

Page 16: Programmable Logic Devices

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Karnaugh maps for the functions

f1(x,y,z) = m(1,2,3,7) and

f2(x,y,z) = m(0,1,2,6)

Example

Page 17: Programmable Logic Devices

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Two realizations of f1(x,y,z) = m(1,2,3,7) and f2(x,y,z) = m(0,1,2,6).

(a) Realization based on f1 and 2

(b) Realization based on 1

and 2

f

ff

Example

Page 18: Programmable Logic Devices

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A simple 4-input, 3-output PAL device