Professor Chuan Seng TanProfessor Chuan Seng Tan (( 陈全胜陈全胜 ))Nanyang Assistant ProfessorSchool of Electrical and Electronic EngineeringNanyang Technological University

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Professor Chuan Seng Professor Chuan Seng TanTan

ACADEMIC QUALIFICATIONS Ph.D. in Electrical Engineering and

Computer Science, Massachusetts Institute of Technology, USA (2006)

M.Eng. in Advanced Materials, Singapore-MIT Alliance, National University of Singapore, Singapore (2001)

B.Eng (Hons) in Electrical Engineering, University of Malaya, Malaysia (1999)

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Professor Chuan Seng TanProfessor Chuan Seng Tan

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Professor Chuan Seng TanProfessor Chuan Seng TanRESEARCH INTERESTSMy research interest covers the larger area

semiconductor materials, structures, devices, and architecture. I am currently actively forming a group to take three-dimensional integrated circuits (3-D ICs) research to new heights.

Briefly, I am looking at: 3-D interconnects (Block/Core level

stacking) - This project explores enabling technology and process to enable vertical stacking of integrated circuits. This is for applications in high density stand-alone memory, embedded memory on logic, and multi-core. This entails chip-to-wafer and wafer-to-wafer bonding of Cu/Low-K hybrid at temperature < 200C. This project also covers formation of through layer via with a targeted density > 10e6 cm-2;

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Professor Chuan Seng TanProfessor Chuan Seng Tan

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Professor Chuan Seng TanProfessor Chuan Seng Tan Group-IV Heteroepitaxy and

Heterostructure - I am particularly interested in direct buffer-less Ge growth on Si substrate for applications in CMOS, photonics, and solar cells (who can say no to SCs these days?). The epitaxy is performed in an Rapid Thermal Chemical Vapor Depostion (RTCVD) reactor from ASM (if you talk to ASM guys, they dislike the terms RTCVD, they prefer to call their tool "reduced pressure epitaxy"). I am also investigating the feasibility of wafer bonding for similar applications.

I undertake the above research in the Microfabrication Laboratory (MFL). Our group is funded generously by these agencies.

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Professor Chuan Seng TanProfessor Chuan Seng Tan

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Professor Chuan Seng TanProfessor Chuan Seng TanAWARDS AND SCHOLARSHIPS Nanyang Assistant Professorship - Nanyang Technological

University, Singapore (2008-2011) Lee Kuan Yew Postdoctoral Fellowship – Lee Kuan Yew

Endowment Fund, Singapore (2006-2008) Applied Materials Graduate Fellowship - Applied Materials,

USA (2003-2005) Research Assistantship – Massachusetts Institute of

Technology, USA (2001-2006) Research Scholarship – Singapore-MIT Alliance, Singapore

(1999-2001) Book Prize – Department of Electrical Engineering, University

of Malaya (1999) Dean List – Faculty of Engineering, University of Malaya

(1997, 1998, 1999) The Lion-ASM Undergraduate Scholarship – The Lion Group,

Malaysia (1996-1999) Physics Prize – Malaysian Institute of Physics, Malaysia (1996)

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Professor Chuan Seng TanProfessor Chuan Seng TanWorking Experience Nanyang Technological University

Singapore (08/2008-Present) Assistant Professor - Supported by the Nanyang Assistant Professorship. Major research activities cover new integration concepts of group-IV based microelectronics. Activity in solar cells will also be initiated. Besides research, I also teach at undergraduate and graduate levels in analog electronics and advanced silicon processing.

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Professor Chuan Seng TanProfessor Chuan Seng TanNanyang Technological University

Singapore (09/2006-07/2008) Research Fellow – Supported by the prestigious Lee Kuan Yew Postdoctoral Fellowship that includes stipend and research grant. Research on new concepts of semiconductor process integration such as three-dimensional integrated circuits (3-D ICs).

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Professor Chuan Seng TanProfessor Chuan Seng TanIntel Corporation, Hillsboro, OR

(06-08/2003)Summer Intern - Investigated interconnect signal integrity at high frequencies, both measurement and modeling.

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Professor Chuan Seng TanProfessor Chuan Seng TanMicrosystems Technology

Laboratories, MIT, Cambridge, MA (09/2001 – 03/2006)Research Assistant – Developed fabrication technology for 3-D ICs using low temperature wafer bonding and thin films handling/transfer.

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Professor Chuan Seng TanProfessor Chuan Seng TanInstitute of Microelectronics

Singapore (03-08/2001)Research Engineer – Responsible for process integration of strained-Si/relaxed-SiGe heterostructures.

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