production of the atlas pixel detector modules vertex2004, como, september 15 th 2004

Production of the ATLAS Pixel Detector Modules

Vertex2004, Como, September 15th 2004

Claudia Gemme INFN and University of Genova

on behalf of the ATLAS Pixel Collaboration

Production of the ATLAS Pixel Detector Modules

Vertex2004, Como, September 15th 2004

Claudia Gemme INFN and University of Genova

on behalf of the ATLAS Pixel Collaboration

22C.Gemme - ATLAS Pixel Modules production

The ATLAS Pixel Detector The ATLAS Pixel Detector It is the innermost part of the

silicon vertex tracker .

It consists of two parts:

Barrel: 3 layers (12 cm, 10 cm and 5 cm radii);

End-cap: 3+3 forward-backward disks.

Only the ‘reduced’ layout is approved (2 layers +2+2 disks), due to budget reason: the 3-layer system may be approved soon.

Going from 3 to 2-layer system means a reduction of 30%.

~1.7 m2 of sensitive area with 67M (barrel) + 13M (disks) channels.

Total dose 50 Mrad on the middle layer in 10 years of LHC.

Installation foreseen mid-2006~1850 mm~1850 mm

~380 mm~380 mm


Pixel ModulesPixel Modules• Modules are the basic building elements of the detector (1456 in the barrel, 288 in the end-caps).

• Each module has an active area of 16.4 mm x 60.8 mm.

•The sensitive area is read out by 16 FE chips which are controlled by a Module Controller Chip (MCC). Each FE read-outs 2880 channels organized in a matrix of 18x160 channels. Each pixel has a 400m x 50m area.

•A Flex-Hybrid circuit glued on the sensor backside provides the signal/power routing. the signal routing between the 16 FE chips and the MCC.

•A pigtail (only for barrel modules) + Al/Cu wire bundle connect flex hybrid to patch panels at either end of pixel detector. Pigtail is the only difference between barrel and disks modules.Schematic cross

section (through here)

sensor

Flex HybridMCC

FE chipFE chip

Wirebondings

bumps


Work packages (PPT) da sostitire con una frase o schema piu’

semplice ( e in inglese) Work packages (PPT) da sostitire con una frase o schema piu’

semplice ( e in inglese) Operazione Quantità Stato Deadline Tempo rimanente

Bump bonding: 2005/09/29 72 sett

AMS 1500 66 ~20/sett

IZM 600 33

Bare module test: 2005/10/15 74 sett

Milano 1100 57 ~15/sett

NRW 1000 37

Assembly: 2005/10/15 74 sett

Genova 800 36 ~10/sett

LBL 400

NRW 800

Flex module test: 2005/10/30 76 sett.

CPPM 100 0

Genova 600 36 ~8 sett.

LBL 400 16

NRW 900 24

Fornituradi chip da LBL

Target 20/sett.

Target >10/sett.


Production Status of basic components:Sensors

Electronics

Flex Hybrids


Sensors (necessary? Ci passi veloce…5”)

Sensors (necessary? Ci passi veloce…5”)

Baseline design:n+ pixel in n-bulk

material:Moderated p-spray

isolation.Bias grid to allow testing

before module assembly.Oxygenated silicon to

improve radiation resistance and increase allowable time to room temperature (for repair/upgrades).

Two vendors: Cis and Tesla

3 tiles wafer, n side

Charge collection efficiency (meas) n+ implants and bias grid


Sensors ProductionSensors Production• Two vendors have produced the sensor tiles:

• CiS delivered 1121 good tiles during 2002/03. All of them have been tested and 1094 are fine. A replacement of 55 tiles is on-going.

• Tesla (now ON Semiconductor) began its deliveries in April 04. After an initial yield problem, now it is ending its 900 tiles contract. The only problem for us is the lower fraction of wafers with 3 good tiles (24% ON).

Rifare il totale?Rifare il totale?


Sensors ProductionSensors Production• Performances are very similar between ON and CIS.

• We have the possibility (option expiring Feb05) to order other tiles if the 3-layers project will be definitevely approved.

• Testing is done in 4 labs and 100 tiles/months could be easily achieved thus ending the test of the delivered tiles in ~6 months time.


On-detector ElectronicsOn-detector Electronics

On-detector chips are fabricated in 0.25m DSM by IBM. Used circuit library with special layout rules for radiation tolerance.

MCC: decode data/cmd signals, generate control signal for 16 FEs, collect data from FEs and accumulate in FIFOs, check event consistency, build module event and sends to DAQ, handle errors.

FE chip: control 18x160 pixels. Amplify sensor signal, on-chip data buffering in EOC FIFOs until trigger signal arrives, send data on serial link to MCC.

FE chip

senso

r

FE chip MCC

Optical Driver (VDC)

OpticalReceiver (DORIC)

power

HV bias

1m100m

LVDS controlLVDS data out bump bonds

optical

……....


MCC-I2.1MCC-I2.1• After one year of experience with modules of first generation DSM, we

have received back in May03 the second generation of chips (MCCI2).

• Some problems have been easily fixed and respin of wafers not completely processed has produced chips good for production (MCCI2.1) .

• Out of 6 wafers we have obtained 2666 good MCC-I2 with a yield of 83% (1744 needed in the 3-layers detector).

1133

44 22

55667788


FEI3: Wafer statusFEI3: Wafer status The first engeneering run (6 wafers) was delivered in Dic 03. After that, we received three production runs (48 wafers each). Another

two are expected in the next months, before the end of the year. A complete test on each chip is performed at the wafer level (LBL and

Bonn). Testing speed is coping well with deliveries. The mean yield on wafer is 79% (but varies from 60 to 92%,sembra migliorare ultimamente )


FEI3: Good dies statusFEI3: Good dies status An electric test and a visual inspection are performed after wafer

bumping deposition, thinning and dicing on the singled dies. Yield of electric test is very high: 99.4% (however on modules would

mean 90% yield);Yield of visual inspection is 88% (mainly damaged bumps); this step is

critical as debris can damage the chip or the sensor after flip-chipping. Considering a yield

of 79% at wafer level and ~ 85% at chip level, having 288 chips on each wafer, we get 11-12 modules/wafer.

IBM will deliverd a total of 246 wafers thus sufficient for more than 2700 modules,i.e enough for the 3-layers detector.


Flex HybridFlex Hybrid

2000 delivered and tested. 1000 more delivery foreseen

Oct 1st. SMD are mounted on the kapton,

then the Flex is glued on a frame that will be used for further tests. This frame makes easy the module handling until it is cut to be loaded on its final support.


Having parts, how we build and qualify a ‘good’ module?


Module Assembly and Testing (da animare)

Module Assembly and Testing (da animare)

Flex+MCCGenova/Bonn/LBL

Bare moduleAMS/IZM

PigtailBonn

MCC operation+ connectivity

Flex+MCC+Pigtailgluing PT

wire bonding

Elco connectivity

HV+voltage drop+peel test

Bare module test

Flex modulegluing

wire bonding/ pullpotting

Assemblytest

Burn-inPost burn-in

test

Cold full characterization

Sorting for loading

16 FEs SensorON/Cis

1122

33

44


IZM – PbSnAMS - In

• Hybridization is done by AMS and IZM. It consists of bump deposition on wafer, thinning and cutting FE-wafers (in US), cutting of sensor tiles and flip-chip of 1 tile with 16 FEs.•Techniques are different but electrical results and yield are comparable.•Tests on the bare module before further assembling are:

A X-rays scan to verify the quality of bumps;A visual inspection and IV curve;An electrical test contacting each chip individually. In case of failure, a chip reworking can be tried (i.e. chip substitution).

•Total test time: 2h/module.

Bare Modules (si deve capire che e’ lo step 1)Bare Modules (si deve capire che e’ lo step 1)

16 thinned FEs, ~50k bumps

Sensor

60.8mm

16.4

mm


QA check using X-raysQA check using X-rays Yield on x-ray is very high.

Few chips (HOW?) not attached and one rotated in AMS.


Yield bare modules Yield bare modules

Yield is (90+21)/134=83% and (71+10)/87=93% (IZM)Losses in reworking is 7/28 (AMS) and 2/12 (IZM)(There are a few accepted re-worked bare modules that failed later. some bare module rejection after rework will be needed. Should be order 2%)

Main problems in the table

Bare modules - FE-I3 delivered

0

200

400

600

800

1000

1200

1400

1600

1800

Aug-03 Dec-03 Apr-04 Aug-04 Dec-04 Apr-05 Aug-05 Dec-05 Apr-06

time

nu

mb

er

of

mo

du

les

IZM-FEI3

AMS_FEI3Total FE-I3

2-layer3-layer

bare modules tested

0

200

400

600

800

1000

1200

1400

1600

1800

2000

2200

Aug-03 Dec-03 Apr-04 Aug-04 Dec-04 Apr-05 Aug-05 Dec-05 Apr-06

time

num

ber o

f mod

ules

virgin accepted

total acceptedtrashed

2-layer3-layer

Delivered bare modules 122 74Bump problems 1 5VDDA short 24 3VDD short 3 3bad sensor 5damaged during probing 1No answer to analog injection 0Others 0bad 34 31! 12REPAIRED 22 7Total good bare modules 110 69

AMS IZM

Rifare I Rifare I grafici piu’ chiarigrafici piu’ chiariEventualmente Eventualmente Aggiungere la Aggiungere la frazione di AVDDfrazione di AVDDRispetto alle Rispetto alle failure totalifailure totaliCome nella slide Come nella slide 3232


DVDD/AVDD shortsDVDD/AVDD shorts• VDDA/DVDD shorts represents the first cause of failure (80%??).• VDDA/DVDD shorts show up as about 300 mA current at power up (instead of

few mA) on the analog (mainly) or digital supply.• They are due to silicon fragments which get trapped between the bumps and

damage the electronics when pressure is applied during the flip-chipping.• These fragments are due to back-side chipping during dicing.• These particles are hard to be recognized during the visual inspection and

moreover they could reach the bumps even during the shipments/handling. • Some attempts to reduce the problem have been tested (changing dicing

parameters and/or polishing wafers, improving cleaning before flip-chipping), but for the time being we should live with this problem (i.e. rework).

Fragment onthe electronic chip (reworking possible)

or on the sensor (reworking not possible).


Flex Hybrid Assembling (si deve capire che e’ lo step 2)

Flex Hybrid Assembling (si deve capire che e’ lo step 2)

Step Time

Gluing, bonding, pull test MCC 60’/flex

Test Flex+MCC 45’/flex

Gluing pigtail 90’/flex

Bonding pigtail 30’/flex

Test Flex+MCC+pigtail 30’/flex

Critical point is the MCC bonding as, due to the geometrical limitations, the bonding loop can not be standard.

Using an Al 25um wire we get a large fraction of peel off or lift (63%) even if obtained with a sufficiently high mean force (12g).

Alternative solutions are under study:2 bondings, 17 um each per pad;Gold ball bonding (not much experience)…


Module Assembling (si deve capire che e’ lo step 3)Module Assembling (si deve capire che e’ lo step 3)

Step TimeGluing Flex Hybrid on module

1 day/4 modules

Bow 15’/module

Wire-bonding FE/ pull test 60’/module

Potting 60’/module

Assembling modules is a complex operation but we have a large experience so that in each lab 10-15 modules can be assembled per week (expected rate from bump-bonding firm is 30 modules/week).

For each module a pull- test is done: 20 bondings are pulled in order to qualify the quality. We still have some not-stick bondings when cleaning is not perfect.

Inserire un plot con DGRID forceInserire un plot con DGRID force


PottingPotting Potting e’ fatto sui bonding del pigtail,

MCC, HV e dei FE. Reworking di questo potting e’

possibile.

Aggiungere test di risonanaza e perche’ abbiamo deciso di pottare solo I piedi (vedi articolo Amanda)


Test Flex Modules (si deve capire che e’ lo step 4)Test Flex Modules (si deve capire che e’ lo step 4)

Step Time Comments

Electrical test after assembling 180’/module If the test is passed, bondings are potted

Burn-in 2 gg/group of modules

8 thermal cycles (-30C,30C) in environmental chamber + power cycles

Electrical test after burn-in 120’/module

Final characterization at operational temperature (-10C)

8-12h/module This test will produce final data for ranking

Up to now module testing is the longest operation: even if all the tests are completely automatized, ~10 modules/week/lab is the maximum speed (this means ~40-50 modules/week in the collaboration).


FEI3 modules yieldFEI3 modules yield

Yield of Flex module assembling/burn-in and testing is ~95%.


Module problemsModule problems

Rate of low quality modules

-0,20

0,00

0,20

0,40

0,60

0,80

1,00

1,20

15/03

/04

29/03

/04

12/04

/04

26/04

/04

10/05

/04

24/05

/04

07/06

/04

21/06

/04

Time

Fra

ctio

n

Defects

Merged bumps

Defectivecolumn pairs

Unsuccessfulreworking

AMS IZMAssembled modules 76Damaged during assembly 1Increased leakage current 1Elco connector faults 2VDDA shorts 2ToT problems 3XCK/DVDD shorts 1MCC faults 1Flex faults 1REPAIRED 4

Problems mainly showed up in the very first electrical tests. No infant mortality has been observed so far after/during the burn-in. We have observed few modules in which the AVDD/DVDD shorts

appeared after few hours of electrical functioning. The main problems are (see table): AVDD/DVDD shorts not observed

at the bare module level, MCC faults, Elco connector faults. Some of these problems will be reduced as we have had more tests

on the components before module assembling; other are intrinsic and will not decrease.


Merged bumps (questo forse e’ un po’ troppo specifico…)

Merged bumps (questo forse e’ un po’ troppo specifico…)

Sometimes merged bumps have been observed on the edge columns of AMS modules.

This kind of defect have been traced to an excessive depth of the shim in some Genova test boards.

Add a small picture with a Add a small picture with a threshold scan threshold scan for a channel to explain what for a channel to explain what the plot is.the plot is.


Source scan (questa e la seguente si possono evitare)Source scan (questa e la seguente si possono evitare)

Source SCAN with source located on the module centre (distance source-module ~ 3cm, source: 241Am, 10 mCi).

If the source stays on the module centre, the scan takes 4hours/200kevs. If the source is moved on the scanned chip, it takes 2-3 min/200Kevs.


Fe 6 Fe 7Fe 6 Fe 7

Fe 9 Fe 8Fe 9 Fe 8


PDB & raw data server (Necessary?)PDB & raw data server (Necessary?) Penso sia necessario dire che e’ necessario e che lo abbiamo, niente

di piu’.


ConclusionsConclusions Module Production has started: components are there

and assembling and testing are fine. We still have some critical step that we are better

investigating (MCC wire-bonding, dealing with dies back-side chipping to reduce reworking).

Data analysis for sorting is to be finalized soon. Emphasis is now moving on the next steps: loading on

local supports!

Sector front side: 3+3 modules

Stave: 13 modules


FE-I3 Bare modulesFE-I3 Bare modules

0

20

40

60

80

100

120

140

Dec-03 Jan-04 Feb-04 Mar-04 Apr-04 May-04Month

Bar

e M

od

ule

s (c

um

ula

tive

)

All Reworked + bad bad FE-I3/16


YieldsYields

AMS chip probing: Electrical: 99.4 +/- 0.1%, Visual: 86%

Bare Modules

AMS defect rate

-0,050,000,050,100,150,200,250,300,350,40

01/02

/04

15/02

/04

29/02

/04

14/03

/04

28/03

/04

11/04

/04

25/04

/04

09/05

/04

23/05

/04

06/06

/04

20/06

/04

Time

Rat

e VDDAshorts

Allfailures


FE-I3 ModulesFE-I3 Modules

0

10

20

30

40

50

60

70

Feb-04 Mar-04 Apr-04 May-04

Month

FE

-I3

Fu

ll M

od

ule

s (

cu

mu

lati

ve

)All modules Used+Trashed Trashed


Module qualityModule quality

Rate of low quality modules

-0,20

0,00

0,20

0,40

0,60

0,80

1,00

1,20

15/03

/04

29/03

/04

12/04

/04

26/04

/04

10/05

/04

24/05

/04

07/06

/04

21/06

/04

Time

Fra

ctio

n

Defects

Merged bumps

Defectivecolumn pairs

Unsuccessfulreworking


510903: leakage current510903: leakage current

production of the atlas pixel detector modules vertex2004, como, september 15 th 2004

Documents

atlas pixel collaboration

n pixel

disks modules

end of pixel detector

sensor tiles

good tiles

delivered tiles

tiles contract