principles of digital design - iuma - ulpgcnunez/clases-fdc/irvine-gajski-digital-design/... ·...

Principles OfPrinciples Of

Digital DesignDigital DesignChapter 7Chapter 7

Storage Components

2Copyright © 2004-2005 by Daniel D. Gajski Slides by Zheng Zhao, University of California, Irvine

Chapter previewChapter preview

Logic gates and flip-flops

3Boolean algebra

3

Finite-state machine

6

2

8

4

5

6

7

8

9

Logic design techniques

Binary system and data

representation

Generalized finite-state machines

Combinational components

Sequential design techniques

Storage components

Register-transfer design

Processor components


Storage componentsStorage components

Storage components store data and perform some simple operations.

Storage components include:registersregisterscounterscountersregister filesregister filesqueuesqueuesstacksstacks

Combinatorial and storage components are used for construction of:

datapathsdatapathscontrollerscontrollers

which are main subsystems of modern processors and other microchips.


RegistersRegistersRegisters are bit wise extensions of flip-flops.Registers store one data word.

Q0D0Q1D1Q2D2Q3D3

I3 I2 I1 I0

Graphic symbol

• Qi = Ii when Clk =

Q3 Q2 Q1 Q0

I0I1I2I3

Q0Q1Q2Q3

RegisterClk

Clk

Register schematic


Registers with asynchronous set and resetRegisters with asynchronous set and reset

Asynchronous setting and resetting is independent ofclock signal.Asynchronous inputs are used to initialize the register.

I0I1I2I3

Q0Q1Q2Q3

RegisterSet

Reset

Graphic symbol

I3 I2 I1 I0

Q3 Q2 Q1 Q0

Set

1

0 X

X X

R Clk

Ii

0

1

Qi

1

X

0

S

ClkReset

Operation table

Register schematic


Register with parallel loadParallel load register can hold data indefinitely.It can also load new data when load signal is 1.

Register with parallel load

I0I1I2I3

Q0Q1Q2Q3

RegisterLoad

Present state Next stateLoad Q3 Q2 Q1 Q0

01

No changeI3 I2 I1 I0

Operation table Graphic symbol

I3 I2 I1 I0

Y3 Y2 Y1 Y0

Load

Clk

Register schematic


SerialSerial--in, parallelin, parallel--out shift registerout shift register

Serial-in, parallel-out register converts serial data stream into parallel data stream.

Present state Next stateShift Q3 Q2 Q1 Q0

01

No changeIL Q3 Q2 Q1

Graphic symbol Operation table

IL

Q0Q1Q2Q3

Shift RegisterShift

Clk

Y3 Y2 Y1 Y0

Shift

IL

Register schematic


Shift register with parallel loadShift register with parallel load

Q3 Q2 Q1 Q0

I3 I2 I1 I0Q2 Q1 Q0 IRIL Q3 Q2 Q1

No changeLoad inputShift left

Shift right

0 00 00 10 11 01 01 11 1

Q3 Q2 Q1 Q0Operation S1 S0

Next statePresent state


Y3 Y2 Y1 Y0

I3 I2 I1 I0IRIL

S0

S1

Clk

D0 =S1’S0’Q0 + S1’S0 I0 +S1S0’I R +S1S0 Q1Register schematicDi =S1’S0’Qi + S1’S0 Ii +S1S0’Ii-1 +S1S0 Qi+1

D3 =S1’S0’Q3 + S1’S0 I3 +S1S0’Q2 +S1S0 IL


44--bit binary counterbit binary counterCounters increment (decrement) their content when enabled.

Q0Q1Q2Q3

Counter E

Reset

E Operations 01

No changeCount

Qi Ci Ci+1 Di0 00 11 01 1

0 00 10 11 0Operation table

HA truth table Di = Qi ⊕ Ci

Graphic symbol

Ci+1 = QiCi

Q3 Q2 Q1 Q0

E

ClkReset

Output carry

C4C3 C2 C1 C0

HA HA HA HA

Counter schematic


44--bit up/down binary counterbit up/down binary counterE D Operations 0 X1 01 1

No changeCount up

Count down

E D Qi Ci Ci+1 Di1 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

0 00 10 11 00 01 10 10 0

Operation table Graphic symbol

Di = Qi ⊕ CiCi+1 = D’QiCi+DQi’Ci HAS truth table

Q0D0Q1D1Q2D2Q3D3

Q0'Q1'Q2'Q3'

D

Reset

E

Clk

Q3 Q2 Q1 Q0Output carry Counter schematic

C4 C3 C2 C1C0

HAS HAS HAS HAS


44--bit up/down binary counter with parallel loadbit up/down binary counter with parallel load• This counter is sometimes called presettable counter.

Load E D Operations 0 0 X0 1 00 1 11 X X

No changeCount up

Count downLoad the input


DE

Load

ClkOutput carry

I3 I2 I1 I0

Y3 Y2 Y1 Y0Register schematic


BCD countersBCD countersUp sequence: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, ......Down sequence: 0, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 9, ......

Up counter loads 0 when counter content is 9 (1001)Up/down counter loads 0 when counter content is 9 (1001) and direction bit D=0Up/down counter loads 9 when counter content is 0 (0000) and direction bit D=1

Q0Q1Q2Q3

Up/Down Counter E

Load

D I0I1I2I3

“0”“0”“0”“0”

“0”

Q0Q1Q2Q3

Up/Down Counter E

Load

D I0I1I2I3

1 0Selector

“0 0 0 0”“1 0 0 1”

BCD up-counter

BCD up/down-counter


Asynchronous countersAsynchronous counters

Each FF in synchronous counters changes its output at the same time.

FFs in asynchronous counters change values at different times.

Advantage of asynchronous counters is low cost (less gates).

Weakness of asynchronous counters is longer delays in comparison with synchronous CLA counters.


44--bit asynchronous up counterbit asynchronous up counter

Q3 Q2 Q1 Q0

Reset

E

ClkGraphic symbol

Logic schematic

t0 t1 t2 t3 t4 t5 t6 t7

0 1 2 3 4 5 6 7 8Clk

2 2

3 3

4Q3

Q2

Q1

Q0

Timing diagram


88--bit mixedbit mixed--mode up countermode up counterMixed-mode counter consists of

(1) asynchronous counters connected synchronously(2) synchronous counters connected asynchronously

Synchronous counter with 4-bit asynchronous slices

Asynchronous counter with 4-bit synchronous slices


RegisterRegister--filefileRegister-file is used as fast temporary storage.

RF2n x m

Q3 Q2 Q1 Q0

I3 I2 I1 I0

WE

WA0

WA1

RE

RA0

RA1

2

1

0

3

2

1

0

3

2-to-4 read

decoder

2-to-4 write

decoder

Register-file cell

QD

Read select

Output

Write select

Input Clk

RARE

Clk

O

m

m

nn

RFC

I

WAWE

Graphic symbol

Logic schematic


RegisterRegister--file with 1 write port and 2 read portsfile with 1 write port and 2 read portsThis register-file is used for reading two operands and writing one result in each clock cycle.

QD

Write select

Input Clk

Read select

(port A)

OutA

Read select

(port B)

OutBRFC

2n x m

RAAREA

WAWE

Clk

I

A

RABREB

B

m

m

nn

m

n

Graphic symbol

Register-file cell

I3 I2 I1 I0WEWA0WA1 REBRAB0RAB1

REARAA0RAA1

A3 A2 A1 A0B3 B2 B1 B0

2

1

0

32-to-4 write

decoder

2

1

0

3

2

1

0

3

2-to-4 read

decoder

2-to-4 read

decoder

Logic schematic


Random access memory (RAM)Random access memory (RAM)011…0100011…0100101…1100101…0001011…0101010…0101110…0011101…0001

000…0010111…0110

Decimal 01234567

2n-22n-1

Binary 0…0000…0010…0100…0110…1000…1010…1100…111

1…1101…111

MEMORY CONTENTADDRESSMEMORY

011…0100011…0100101…1100101…0001011…0101010…0101110…0011101…0001

000…0010111…0110

Decimal 01234567

2n-22n-1

Binary 0…0000…0010…0100…0110…1000…1010…1100…111

1…1101…111

MEMORY CONTENTADDRESSMEMORY

m bits

... ... ...

CS

Im-1 I1 I0

An-1

A1

A0

RWS

2n x m RAM

...

. . .

Om-1 O1 O0. . .

. . .

. . .

...

CS

An-1

A1

A0

RWS

2n x m RAM

...

I/Om-1 I/O1I/O0. . .

...

Memory address and content

. . .

Graphic symbols


RAM organizationRAM organization• Ram memory cells can be static or dynamic.• Static RAM’s do not lose data with time.• Dynamic RAM’s must be refreshed.

2

1

0

32-to-4

address decoder

Write enable

Row select

Output Input

MC A0

A1

Write enable

Memory cell

RWS

CS

IO3 IO2 IO0IO1

Memory schematic


RAM timingRAM timingRWS

CS

t0 t1 t2 t3 t4 t5

Output-disable time

Output-enable time

Output-hold timeAccess time

t0 t1 t2 t3 t4 t5

Valid address

Valid data

Address

Data

Read-cycle timing

RWS

CS

Address

Address-hold timeData-setup time

Address-setup time

Data-hold timeWrite pulse width

Valid address

Valid dataData

Write-cycle timing


16K x 32 RAM design with 16K x 8 16K x 32 RAM design with 16K x 8 RAMsRAMs

148 8 8 8

32

8 8 8 8

32

IA

CS

RWS

O

M3

IA

CS

RWS

O

M2

IA

CS

RWS

O

M1

IA

CS

RWS

O

M0

Input bus

Output bus

A

CSRWS


64K x 8 RAM design with 16K x 8 64K x 8 RAM design with 16K x 8 RAMsRAMs

Addresses

0

214-1

...

215-1

...

214

215+214+1

...

215

216-1

...

215+214


PushPush--down stack principledown stack principle

34

23 empty

empty

Top

Top-1

Top-2

Top-3

45

34

23

empty

34

23

empty

empty

45 45

Stack content before 45 is pushed down

Stack content after 45 is pushed down

Stack content before 45 is popped up


44--Word pushWord push--down stackdown stack

X 00 11 1

0 01 11 0

X 0X 00 10 11 01 0

D ES1 S0Push/Pop Enable

Counter controls

Shift register controls

X 00 11 1

0 01 11 0

X 0X 00 10 11 01 0

D ES1 S0Push/Pop Enable

Counter controls

Shift register controlsNo change

PushPop

X 00 11 1

Operations Push/Pop EnableNo change

PushPop

X 00 11 1

Operations Push/Pop Enable00001

10000

0 0 00 0 00 0 10 0 10 1 00 1 00 1 10 1 11 0 01 0 0

Full Empty Q2 Q1 Q0

Counter outputs

00001

10000

0 0 00 0 00 0 10 0 10 1 00 1 00 1 10 1 11 0 01 0 0

Full Empty Q2 Q1 Q0

Counter outputs

Control logic

Output logic

IN0

Push/pop

Reset

INm-1

Enable

OUTm-1

...

...

Control table Output table

Stack schematic

•Push=Shift right

•Pop=Shift left

Operation table

OUT0

Empty

Full


PushPush--down stack with a 1K RAMdown stack with a 1K RAM

empty empty empty

empty

emptydatadata

Top-1Top

012

102110221023

No changePushPop

X 00 11 1

Operations Push/Pop EnableNo change

PushPop

X 00 11 1

Operations Push/Pop Enable

0 01 11 0

X10

X 0X 00 10 11 01 0

CS RWSS Push/Pop Enable

Memory controls

Selector control

0 01 11 0

X10

X 0X 00 10 11 01 0

CS RWSS Push/Pop Enable

Memory controls

Selector control

X 00 11 1

D E

Counter controls

X 00 11 1

D E

Counter controls

Operation table

Control table

Symbolic design

Stack schematic

• Push: Data RAM (TOP); Increment Top, Top 1

• Pop: RAM (Top-1) Date; Decrement Top, Top-1

• Stack is full when Top=1023; Stack is empty when Top=0

• Location with address 1023 is never loaded

Reset

Push/pop

Enable

Control logic

Output logic

I/O busEmptyFull


FIFO queue principlesFIFO queue principles• Queue is used for irregular “burst” communication

34

23

Top

Top-1

Top-2

Top-3

45

34

23

empty

45

34

empty

empty

45

23

empty

empty

Queue content after 45 is stored

Queue content before 45 is stored

Queue content after 23 is read


44--word FIFO queueword FIFO queueNo change

Read Write

X 00 11 1

OPERATIONSREAD/WRITE ENABLENo change

Read Write

X 00 11 1

OPERATIONSREAD/WRITE ENABLEX 01 10 1

0 00 01 0

X 0 0 11 1

D ES1 S0READ/WRITE ENABLEX 01 10 1

0 00 01 0

X 0 0 11 1

D ES1 S0READ/WRITE ENABLE

Operation table Control table

Queue schematic

●●●

●●●

●●●

OUT0

OUTm-1

Full

Empty

Read/Write

Reset

INm-1

Enable

Control logic

Output logic

IN0


FIFO queue implemented with a 1K RAMFIFO queue implemented with a 1K RAM

0 X 0 01 0 1 01 1 0 1

X10

X 0X 00 10 11 01 0

CS RWS (Front) (Back)S Read/Write Enable E E

0 X 0 01 0 1 01 1 0 1

X10

X 0X 00 10 11 01 0

CS RWS (Front) (Back)S Read/Write Enable E E

No changeReadWrite

X 00 11 1

Operations Read/Write EnableNo change

ReadWrite

X 00 11 1

Operations Read/Write Enable

Front EReset Back

EReset

Selector 01

S

ACSRWS

1K RAM

Comparator < = >

10101 1

Reset

Read/writeEnable

I/O busEmptyFull

Clk

Operation table Control table

Stack schematic

Symbolic design


Simple datapath with one accumulatorSimple datapath with one accumulator• Datapath are used for temporary variable storage and operation execution

ALUM

Selector 01

AccumulatorS0

S1

S0

S1

IRIL

BA

S

OInput

8

765

4321

Clk

0

Datapath schematic

Input select

ALUcontrols

Shiftvalues

Accumulator controls

Out enable

8 7 6 5 4 3 2 1 0

Control word


Datapath with 3 port registerDatapath with 3 port register--filefile

PassPass

Not usedNot usedShift left

Rotate leftShift right

Rotate right

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

Shift Operations S2 S1 S0PassPass

Not usedNot usedShift left

Rotate leftShift right

Rotate right

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

Shift Operations S2 S1 S0

Complement AAND

EX-OROR

Decrement AAdd

SubtractIncrement A

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

ALU Operations M S1 S0Complement A

ANDEX-OR

ORDecrement A

AddSubtract

Increment A

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

ALU Operations M S1 S0

Datapath schematic

ALU operations

Shifter operations

IE Write address

Read address A

Read address B

ALU operation

Shifter operation

OE19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Control word


OneOne’’ss--count algorithmcount algorithmExample: OneExample: One’’ss--counter implementation counter implementation Problem: Using a datapath with a 3 port registerProblem: Using a datapath with a 3 port register--file, design a onefile, design a one’’s counter that will counts counter that will count

the number of ones in an input the number of ones in an input dataworddataword, and return the result after completion. , and return the result after completion.

Control words IE

Write address

Read address A

Read address B

ALU operation Shifter operation OE

1 1 R1 X X X X 02 0 R3 0 0 Add Pass 03 0 R2 0 X Increment Pass 04 0 R4 R1 R2 AND Pass 05 0 R3 R3 R4 Add Pass 06 0 R1 R1 0 Add Shift right 07 0 None R3 0 Add Pass 1

1. Data := Inport2. Ocount := 03. Mask := 1while Data = 0 repeat4. Temp := Data AND Mask5. Ocount := Ocount + Temp6. Data := Data >> 1

end while7. Outport := Ocount

Data R1:

R2:

R3:

R4:

Mask

Ocount

Temp Basic algorithm for one’s counter Register assignment

Repeated while

Data = 0

Control words for one’s counter


FSM representation of OneFSM representation of One’’ss--countercounter• State lasts for a clock cycle.

• In each state the datapath executes the statement indicated on its right side.Start = 0

Data = Input

Data = Data >> 1 (shift right)

Mask = 1

Temp = Data AND Mask

Ocount = Ocount + Temp

Ocount = 0

Outport =Ocount

Start = 1

Done = 1

Data = 0

Data = 0


Design modelDesign model

Control unit

Datapath

Control signalsStatus signals

Control inputs

Datapathinputs

Datapathoutputs

Control outputs

Control unit

Datapath

Control signalsStatus signals

Control inputs

Datapathinputs

Datapathoutputs

Control outputs

High-level block diagram

Register-transfer-level block diagram

Control unit Datapath

Bus 1Bus 2

Bus 3Status signals

Control signals

Control outputs Datapath outputs

Datapathinputs

Control inputs

State register


NextNext--state logic for Onestate logic for One’’ss--countercounter

000 000 001 001010 010 010 010011 011 011 011100 100 100 100101 101 101 101110 110 110 110100 111 100 111000 000 000 000

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

s0

s1

s2

s3

s4

s5

s6S7

00 01 10 11Q2Q1Q0States Start, (Data = 0)

000 000 001 001010 010 010 010011 011 011 011100 100 100 100101 101 101 101110 110 110 110100 111 100 111000 000 000 000

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

s0

s1

s2

s3

s4

s5

s6S7

00 01 10 11Q2Q1Q0States Start, (Data = 0)

Q2(next) = Q2’ Q1Q0+Q2Q1’+( Data=0 )Q2Q0’

Q1(next) = Q1’ Q0+Q2’Q1Q0’+( Data=0 )Q1Q0’

Q0(next) = Q2’ Q1Q0’+Q2Q1’Q0’+Start Q2’Q0’( Data=0 )Q2Q0’Next-state table

Next-state equations

000 010 100 011 101 110 000 100000 010 100 011 101 110 000 111001 010 100 011 101 110 000 111001 010 100 011 101 110 000 100

Start, (Data = 0)Q1Q0

00 01 11 10 00 01 11 10Q2 = 0 Q2 = 1

00

01

11

10

Q2Q1Q0 Karnaugh map


Output logic for OneOutput logic for One’’ss--counter controllercounter controller

00000001

X X XX X X0 0 00 0 00 0 00 0 01 1 00 0 0

X X XX X X1 0 11 1 10 0 11 0 11 0 11 0 1

X X X 0X X X 0X X X 0X X X 00 1 0 11 0 0 1X X X 0X X X 0

X X X 0X X X 0X X X 0X X X 00 0 1 10 1 1 10 0 1 10 1 1 1

X X X 00 0 1 10 1 1 10 1 0 11 0 0 10 1 1 10 0 1 1X X X 0

01000000

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

s0

s1

s2

s3

s4

s5

s6

S7

OES2 S1 S0M S1 S0RAB2 RAB1 RAB0 REBRAA2 RAA1 RAA0 REAWA2 WA1 WA0 WEIEQ2Q1Q0State

Shift operations

ALU operations

Read address BRead address AWrite address

00000001

X X XX X X0 0 00 0 00 0 00 0 01 1 00 0 0

X X XX X X1 0 11 1 10 0 11 0 11 0 11 0 1

X X X 0X X X 0X X X 0X X X 00 1 0 11 0 0 1X X X 0X X X 0

X X X 0X X X 0X X X 0X X X 00 0 1 10 1 1 10 0 1 10 1 1 1

X X X 00 0 1 10 1 1 10 1 0 11 0 0 10 1 1 10 0 1 1X X X 0

01000000

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

s0

s1

s2

s3

s4

s5

s6

S7

OES2 S1 S0M S1 S0RAB2 RAB1 RAB0 REBRAA2 RAA1 RAA0 REAWA2 WA1 WA0 WEIEQ2Q1Q0State

Shift operations

ALU operations

Read address BRead address AWrite address

Output logic table

IE = Q2’ Q1’Q0 RAA2 = 0 RAB2 = Q0 M = Q1 + Q0

WA2 = Q1’ Q0’ RAA1 = Q0 RAB1 = Q0’ S1 = Q2’ Q0

WA1 = Q2Q0+Q2Q1’ RAB0 = 0RAA0 = 1 S0 = 1

WA0 = Q1’Q0+Q1Q0’ REA = Q1 REB = Q2Q1 S2 = S1 = Q2Q1Q0’

WE = Q2Q1’+Q2’Q0+Q1Q0 S0 = 0OE = Q2Q1Q0

Output equations


OneOne’’ss--counter schematiccounter schematicQ2 Q2’ Q1 Q1’ Q0 Q0

Q2 Q2’ Q1 Q1’ Q0 Q0

Output logic

Control unit01

0

1

0

Next-state logic

Data = 0Data = 0

Start

Clk

Done


Parallel datapathParallel datapathDatapath allows 2 operations in each clock cycle.

Choice of operations performed simultaneously is limited.

Register file

Selector Selector

Shifter Multiplier Divider ALU

Bus 1Bus 2Bus 3Bus 4

Result Bus 2Result Bus 1 Input 1 Input 2


An example of a custom datapathAn example of a custom datapathUses latches as temporary storage on the input and output of functional units.Latches allow shorter clock cycles and more concurrency.

Bus 1Bus 2Bus 3Bus 4


ControlControl--unit implementation stylesunit implementation styles

Control unit model Control unit with state-register and decoder

Control unit with counter Control unit with state-register and push-down stack

Output logic

Next-state logic

D Q

D Q

D Q

Datapathcontrolsignals

Controloutputs

.

.

....

.

.

....

Control inputs Status signals

State register Control

outputs

Datapathcontrolsingals

Status signals

Control inputs

Next-Stata logic

Output logic

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

..

.

..

.

..

.

.

.

Dec

oder

Stat

e re

gist

er

01

23 Se

lect

or

Stat

e re

gist

er

Push

dow

n st

ack

Control inputs

Status signals

Datapathcontrolsignals

Controloutputs

Sele

ctor

Cou

nter

Next-stage logic

Output logic

.

.

.

Load

C

ount

Externalbranch

Internalbranch


ControlControl--unit implementation stylesunit implementation styles

Address selection logic

ConditionSelector

Push

dow

n st

ack

ROMor

PROM

Statussignals

Datapath Control signals

Controloutputs

External address

Control inputs

01

23 Se

lect

or 0

1 Sele

ctor

Stat

e re

gist

er

Incrementer

.

.

.

.

.

.

Control unit with state-register, ROM and push-down stack ( microprogrammed control unit )


Chapter SummaryChapter Summary

We introduced sequential componentsSimple (registers, counters)Simple (registers, counters)Storage (registerStorage (register--files, memories)files, memories)Complex (stacks, queues, datapaths and control units)Complex (stacks, queues, datapaths and control units)

Datapath and control units are used to implement standard processors and application specific integrated circuits (One’s count example)

principles of digital design - iuma - ulpgcnunez/clases-fdc/irvine-gajski-digital-design/... ·...

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