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Princess Sumaya Univ. Computer Engineering Dept. Chapter 5: Chapter 5:

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Page 1: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya Univ.Computer Engineering Dept.

Chapter 5:Chapter 5:

Page 2: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Stored Program ArchitectureStored Program Architecture

Instruction Cycle

● Fetch an instruction from memory

● Decode the instruction

● Get the operands

● Execute the instruction

Where is the next instruction?

Program Counter (PC)

Instruction Pointer (IP)

Where is the operand?

06:29 AM06:29 AM

Instructions(Program)

Operands(Data)

Opcode Operands

Binary Operand

22 / 54 / 54

Page 3: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.CPUCPU

Datapath

Control Unit

06:29 AM06:29 AM

Register File

CU

ALU

33 / 54 / 54

Page 4: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.General-Purpose Register OrganizationGeneral-Purpose Register Organization

06:29 AM06:29 AM

R1

R2

R3

R4

R5

R6

R7

MUX MUX

ALU

3 x 8Decoder

DSEL

ASEL BSEL

OPR

Memory& I/O

A B

44 / 54 / 54

Page 5: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.General-Purpose Register OrganizationGeneral-Purpose Register Organization

06:29 AM06:29 AM

R1

R2

R3

R4

R5

R6

R7

MUX MUX

ALU

3 x 8Decoder

DSEL

ASEL BSEL

OPR

Memory& I/O

A B

Examples:

55 / 54 / 54

Page 6: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.General-Purpose Register OrganizationGeneral-Purpose Register Organization

06:29 AM06:29 AM

Examples:

Instructions(Program)

Operands(Data)

00101 010 011 001 00

0000 0000 0000 0000

66 / 54 / 54

Page 7: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Memory InterfaceMemory Interface

Address / Data Buses

Read / Write Control

Bidirectional /UnidirectionalData Bus

06:29 AM06:29 AM

Read

Write

77 / 54 / 54

Page 8: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Building a DatapathBuilding a Datapath

Datapath Elements

06:29 AM06:29 AM

InstructionInstructionMemoryMemory

Addr

Data

AL

UA

LU

Reg A(Read)

Reg B(Read)

Reg C(Write)

DataA

DataB

Register FileRegister File

DataC

Write a program & compile it.Where do you want to put it?Where is the first instruction?What comes out of memory?Where to perform operation?Where are the operands?Who well tell us which reg?Where to store result?Can we save this reg to mem?

32

32

32

88 / 54 / 54

Page 9: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Building a DatapathBuilding a Datapath

Datapath Elements

06:29 AM06:29 AM

InstructionInstructionMemoryMemory

Addr

Data

AL

UA

LU

DataDataMemoryMemory

Addr Data

Data

Reg A(Read)

Reg B(Read)

Reg C(Write)

DataA

DataB

Register FileRegister File

DataC

99 / 54 / 54

Page 10: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Building a DatapathBuilding a Datapath

06:29 AM06:29 AM

InstructionInstructionMemoryMemory

Addr

Data

AL

UA

LU

DataDataMemoryMemory

Addr Data

Data

How can we read it back?

Reg A(Read)

Reg B(Read)

Reg C(Write)

DataA

DataB

Register FileRegister File

DataC

1010 / 54 / 54

Page 11: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Building a DatapathBuilding a Datapath

06:29 AM06:29 AM

InstructionInstructionMemoryMemory

Addr

Data

AL

UA

LU

DataDataMemoryMemory

Addr Data

Data

Finished executing instruction. Where is the next instruction?Why +4?

4

Ad

der

Ad

der

Reg A(Read)

Reg B(Read)

Reg C(Write)

DataA

DataB

Register FileRegister File

DataC

1111 / 54 / 54

Page 12: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Building a DatapathBuilding a Datapath

06:29 AM06:29 AM

InstructionInstructionMemoryMemory

Addr

Data

AL

UA

LU

DataDataMemoryMemory

Addr Data

Data

4

Ad

der

Ad

der

How can we add “immediate”?What if it is 8-bit negative?

SignSignExtendExtend

Reg A(Read)

Reg B(Read)

Reg C(Write)

DataA

DataB

Register FileRegister File

DataC

1212 / 54 / 54

Page 13: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Building a DatapathBuilding a Datapath

06:29 AM06:29 AM

InstructionInstructionMemoryMemory

Addr

Data

AL

UA

LU

DataDataMemoryMemory

Addr Data

Data

4

Ad

der

Ad

der

SignSignExtendExtend

What about “JMP Rel Disp”?It can be positive or negative!

Reg A(Read)

Reg B(Read)

Reg C(Write)

DataA

DataB

Register FileRegister File

DataC

1313 / 54 / 54

Page 14: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Building a DatapathBuilding a Datapath

06:29 AM06:29 AM

4

DataDataMemoryMemory

Addr

Data

SignSignExtendExtend

Addr Data

Data

InstructionInstructionMemoryMemory

Shift Shift Left 2Left 2

Ad

der

Ad

der

Ad

der

Ad

der

AL

UA

LU

Reg A(Read)

Reg B(Read)

Reg C(Write)

DataA

DataB

Register FileRegister File

DataC

1414 / 54 / 54

Page 15: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Building a DatapathBuilding a Datapath

06:29 AM06:29 AM

4

DataDataMemoryMemory

Addr

Data

SignSignExtendExtend

DataA

DataB Addr Data

Data

InstructionInstructionMemoryMemory

Register FileRegister File

Shift Shift Left 2Left 2

Ad

der

Ad

der

Ad

der

Ad

der

AL

UA

LU

DataC

Why the shift?

Answer:

Reg A(Read)

Reg B(Read)

Reg C(Write)

1515 / 54 / 54

Page 16: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Building a DatapathBuilding a Datapath

06:29 AM06:29 AM

4

DataDataMemoryMemory

Addr

Data

SignSignExtendExtend

DataA

DataB Addr Data

Data

InstructionInstructionMemoryMemory

Register FileRegister File

Shift Shift Left 2Left 2

Ad

der

Ad

der

Ad

der

Ad

der

AL

UA

LU

DataC

Why not use ALU instead of another adder?

Answer:

Reg A(Read)

Reg B(Read)

Reg C(Write)

1616 / 54 / 54

Page 17: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.

Cy, Z, etc

Adding Control Signals to the DatapathAdding Control Signals to the Datapath

06:29 AM06:29 AM

4

DataDataMemoryMemory

Addr

Data

SignSignExtendExtend

DataA

DataB 00

MMUUXX11

Addr Data

Data

11

MMUUXX

00

InstructionInstructionMemoryMemory

Register FileRegister File

Shift Shift Left 2Left 2

00

MMUUXX11A

dd

erA

dd

er

Ad

der

Ad

der

AL

UA

LU

DataC

Control Unit

Opcodeetc

Reg A(Read)

Reg B(Read)

Reg C(Write)

1717 / 54 / 54

Page 18: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Adding Control Signals to the DatapathAdding Control Signals to the Datapath

06:29 AM06:29 AM

4

DataDataMemoryMemory

Addr

Data

SignSignExtendExtend

DataA

DataB 00

MMUUXX11

Addr Data

Data

11

MMUUXX

00

InstructionInstructionMemoryMemory

Register FileRegister File

Shift Shift Left 2Left 2

00

MMUUXX11A

dd

erA

dd

er

Ad

der

Ad

der

AL

UA

LU

DataC

Control Unit

Reg A(Read)

Reg B(Read)

Reg C(Write)

1818 / 54 / 54

Page 19: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.A Simple Implementation SchemeA Simple Implementation Scheme

ALU Control

06:29 AM06:29 AM

ALUALU

3232

32

4ALU Cntrl

CyZ

slt R1, R2, R3

otherwise

RRifR

0

3211

Cy = 1 Carry from last adder

Z = 1 The result = 0

1919 / 54 / 54

Page 20: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.A Simple Implementation SchemeA Simple Implementation Scheme

Instruction Format

● Arithmetic/Logic

06:29 AM06:29 AM

Opcode Operand(s), Address, Code

0

6

Rs

5 5 5 5 6

Rt Rd Shift FunctRd = Rs Funct Rt

Funct ALU Operation ALU Cntrl Lines

100000 Add 0010

100010 Subtract 0110

100100 AND 0000

100101 OR 0001

101010 SLT 0111

Example:000000 00011 00111 00101 00000 100000

Reg A(Read)

Reg B(Read)

Reg C(Write)

DataA

DataB

Register FileRegister File

DataC

2020 / 54 / 54

Page 21: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.A Simple Implementation SchemeA Simple Implementation Scheme

Instruction Format

● Load Immediate

06:29 AM06:29 AM

Opcode Operand(s), Address, Code

Lower Rt = Value

Upper Rt = Value

Example: R1 = 12

001101 00000 00001 0000 0000 0000 1100

13

6

0

5 5 16

Rt Immediate (Lower)

16 0 Rt Immediate (Upper)

010000 00000 00001 0000 0000 0000 0000

2121 / 54 / 54

Page 22: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.A Simple Implementation SchemeA Simple Implementation Scheme

Instruction Format

● Load Memory

06:29 AM06:29 AM

Opcode Operand(s), Address, Code

35

6

Rs

5 5 16

Rt AddressRt = M [Rs + Addr]

32 bits 16 bits (can be positive or negative)

Example: R6 = M [R4 – 1 ]

100011 00100 00110 1111 1111 1111 1111

2222 / 54 / 54

Page 23: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.A Simple Implementation SchemeA Simple Implementation Scheme

Instruction Format

● Store Memory

06:29 AM06:29 AM

Opcode Operand(s), Address, Code

43

6

Rs

5 5 16

Rt AddressM [Rs + Addr] = Rt

Example: M [R7 – 2 ] = R9

101011 00111 01001 1111 1111 1111 1110

2323 / 54 / 54

Page 24: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.A Simple Implementation SchemeA Simple Implementation Scheme

Instruction Format

● JE Operation

06:29 AM06:29 AM

Opcode Operand(s), Address, Code

4

6

Rs

5 5 16

Rt OffsetIf Rs = Rt then

PC = PC + 4*Addr

Example:

000100 00001 00100 1111 1111 1111 1111

PC is already incremented

2424 / 54 / 54

Page 25: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.

MMUUXX

Final Datapath DesignFinal Datapath Design

06:29 AM06:29 AM

4

DataDataMemoryMemory

Addr

Data

SignSignExtendExtend

DataA

DataB 00

MMUUXX11

Addr Data

Data

11

MMUUXX

00

InstructionInstructionMemoryMemory

Register FileRegister File

Shift Shift Left 2Left 2

00

MMUUXX11A

dd

erA

dd

er

Ad

der

Ad

der

DataC

Reg A(Read)

Reg B(Read)

Reg C(Write)

AL

UA

LU

Rs

Rt

Offset, Addr, Immediate

Rt

Rd

2525 / 54 / 54

Page 26: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Program SetupProgram Setup

Write a Program

Assemble itStore it in Memory

06:29 AM06:29 AM

Example:

001101 00000 00001 0000 0000 0000 1010

000000 00001 00001 00001 00000 100000

3 4 0 1 0 0 0 A

0 0 2 1 0 8 2 0

0

4

8000100 00001 00001 1111 1111 1111 1111

1 0 2 1 F F F F

2626 / 54 / 54

Page 27: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Datapath OperationDatapath Operation

Fetch Instruction

Decode Instruction

Get Operands

Execute it

06:29 AM06:29 AM

CLKPC

I-Mem0

ƮM3401000A (LLI R1, 10)

13 0 1 10Rs Rt Immediate

Reg ASel0

0Data A ƮReg

1Reg CSel

Reg CWrite

ALU MUX2 (Add)ALU Ctrl

Mem MUX

10Sign Ext10ALU ƮALU

10Data C

Adder MUX4PC Adder ƮAdder

ƮReg

2727 / 54 / 54

Page 28: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Datapath OperationDatapath Operation

How Fast Can the Clock Be?

06:29 AM06:29 AM

CLKPC

I-Mem0

ƮM

Reg ASel

Data A ƮReg

Reg CSel

Reg CWrite

ALU MUXALU Ctrl

Mem MUX

Sign Ext

ALU ƮALU

Data C

Adder MUXPC AdderƮclk

ƮReg

2828 / 54 / 54

Page 29: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Datapath OperationDatapath Operation

Fetch Instruction

Decode Instruction

Get Operands

Execute it

06:29 AM06:29 AM

CLKPC

I-Mem4

00210820(Add R1,R1,R1)

Reg ASel1

10Data A

1Reg CSel

Reg CWrite

ALU MUX2 (Add)ALU Ctrl

Mem MUX

10Data B20ALU20Data C

Adder MUX8PC Adder

0 1 1 32Rs Rt FunctRd

1 0Shift

0

4

0

1

2

0

10

10

2929 / 54 / 54

Page 30: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Datapath OperationDatapath Operation

Fetch Instruction

Decode Instruction

Get Operands

Execute it

06:29 AM06:29 AM

CLKPC

I-Mem8

1021FFFF (JE R1,R1,-1)

Reg ASel1

20Data A

1Reg CSel

Reg CWrite

ALU MUX6 (Sub)ALU Ctrl

20Data B0ALU

12PC Adder

4 1 1 – 1Rs Rt Offset

4

8

1

1

2

10

20

10

PC Adder 2 8

Adder MUX

3030 / 54 / 54

Page 31: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Datapath OperationDatapath Operation

How Fast Can the Clock Be?

06:29 AM06:29 AM

CLKPC

I-Mem8

Reg ASel

Data A

Reg CSel

Reg CWrite

ALU MUXALU Ctrl

Data B

ALU

PC Adder

4

8

1

1

2

10

20

10

PC Adder 2Adder MUX

ƮM

ƮReg

ƮALU

3131 / 54 / 54

Page 32: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Datapath OperationDatapath Operation

How Fast Can the Clock Be?

06:29 AM06:29 AM

CLKPC

I-Mem8

Reg ASel

Data A

Reg CSel

Reg CWrite

ALU MUXALU Ctrl

Data B

ALU

PC Adder

4

8

1

1

2

10

20

10

PC Adder 2Adder MUX

ƮAdder

ƮAdder

Ʈclk

ƮReg

ƮALU

ƮM

3232 / 54 / 54

Page 33: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Single-Cycle ImplementationSingle-Cycle Implementation

Fetch Instruction

Decode Instruction

Get Operands

Execute it

06:29 AM06:29 AM

CLKPC

I-Memi

8C640007 (LD R4,[R3+7])

35 3 4 7Rs Rt Address

Reg ASel 3

dData A

4Reg CSel

Reg CWrite

ALU MUX

2 (Add)ALU Ctrl

Mem MUX

7Sign Ext

d+7ALU

vData CD-Mem v

3333 / 54 / 54

Page 34: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Single-Cycle ImplementationSingle-Cycle Implementation

Clock Speed?

06:29 AM06:29 AM

CLKPC

I-Memi

Reg ASel

Data A

Reg CSel

Reg CWrite

ALU MUX

ALU Ctrl

Mem MUX

Sign Ext

ALU

Data CD-Mem

ƮM

ƮReg

ƮALU

Ʈclk

ƮReg

ƮM

3434 / 54 / 54

Page 35: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Single-Cycle ImplementationSingle-Cycle Implementation

Example:ƮM = 200 picosecondsƮALU = 100 picosecondsƮAdder = 100 picosecondsƮReg = 50 picoseconds

Fastest Clock?

06:29 AM06:29 AM

Load Immediate/ALU: Ʈclk > ƮM + 2 ƮReg + ƮALU

Conditional Jump:

Ʈclk > Max 2 ƮAdder

ƮM + ƮReg + ƮALU

Load Memory: Ʈclk > 2 ƮM + 2 ƮReg + ƮALU

Store Memory: Ʈclk > 2 ƮM + ƮReg + ƮALU

Type Delay

LI / ALU 400 ps

LD 600 ps

ST 550 ps

Cond. Jump 350 ps

Ʈclk = ps GHz

3535 / 54 / 54

Page 36: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Multicycle ImplementationMulticycle Implementation

Instructions take different number of clock cycles

Functional units can be shared within the execution of a single instruction

06:29 AM06:29 AM

DataA

DataB

Register FileRegister File

DataC

Reg A(Read)

Reg B(Read)

Reg C(Write)

XX

YY

AL

UA

LU

MemoryMemory

Addr

DataData

3636 / 54 / 54

Page 37: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Multicycle ImplementationMulticycle Implementation

Some registers are not visible to the programmer

06:29 AM06:29 AM

DataA

DataB

Register FileRegister File

DataC

Reg A(Read)

Reg B(Read)

Reg C(Write)

XX

YY

AL

UA

LU

MemoryMemory

Addr

DataData

4

SignSignExtendExtend

Shift Shift LeftLeft 2 2

Exercise: Can you do all the previous instruction here? 3737 / 54 / 54

Page 38: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Multicycle ImplementationMulticycle Implementation

Some registers are not visible to the programmer

06:29 AM06:29 AM

DataA

DataB

Register FileRegister File

DataC

Reg A(Read)

Reg B(Read)

Reg C(Write)

XX

YY

AL

UA

LUAddr

Data

Data

4

SignSignExtendExtend

Shift Shift LeftLeft 2 2

0011

0011223300

11

001100

11

MemoryMemory

0011

3838 / 54 / 54

Page 39: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Multicycle Datapath OperationMulticycle Datapath Operation

Fetch Instruction

06:29 AM06:29 AM

CLKPC 0

ƮM

3401000A

Y MUX2 (Add)ALU Ctrl

PC MUX

X MUX

4ALUƮALU

0

IRLD

MemRd

PCLD

Ʈclk

1

IR

Mem Out

3939 / 54 / 54

Page 40: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Multicycle Datapath OperationMulticycle Datapath Operation

Fetch Instruction

Decode Instruction

Get Operands

06:29 AM06:29 AM

CLKPC 4 0

2

3401000A (LLI R1, 10)

13 0 1 10Rs Rt Immediate

Reg ASel0

XLD

0Data A ƮReg

X

10Sign Ext

Ʈclk

IRLD

MemRd

IR

Mem Out

4040 / 54 / 54

Page 41: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Multicycle Datapath OperationMulticycle Datapath Operation

Fetch Instruction

Decode Instruction

Get Operands

Execute it

06:29 AM06:29 AM

CLKPC 4

IR 3401000A (LLI R1, 10)

13 0 1 10Rs Rt Immediate

3

X 0

Y MUX

ALU Ctrl

X MUX

ALU

2

2 (Add)

10ƮALU

ResultLD

Result

Ʈclk

XLD

4141 / 54 / 54

Page 42: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Multicycle Datapath OperationMulticycle Datapath Operation

Fetch Instruction

Decode Instruction

Get Operands

Execute it

06:29 AM06:29 AM

CLKPC 4

IR 3401000A (LLI R1, 10)

13 0 1 10Rs Rt Immediate

4

ResultLD

Result

Ʈclk

10

C MUXReg CWrite

ƮReg

Ʈclk

Reg CSel 1

4242 / 54 / 54

Page 43: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Multicycle Datapath OperationMulticycle Datapath Operation

CLK

PCMemRd

Mem OutIRLD

IR

ALU CtrlALU

PCLD

Reg ASel

Data A

Sign Ext

0 4

3401000A

3401000A (LLI R1, 10)

2 (Add)

10

0

0

XLD

X10

0

ResultLD

Result 10

4

IR M[PC]PC PC + 4

X Reg[IR[25:21]]

Rs

R X+IR[15:0]

Immediate

Reg[IR[20:16]] R

Rt .

13 0 1 10Rs Rt Immediate

2 (Add)

Reg CSel 1

Reg CWrite

4343 / 54 / 54

Page 44: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Multicycle Datapath OperationMulticycle Datapath Operation

CLK

PCMemRd

Mem OutIRLD

IR

ALU CtrlALU

PCLD

Reg ASel

Data A

Sign Ext

i

Add

result

XLD

X

ResultLD

Result result

i+4

IR M[PC]PC PC + 4

X Reg[IR[25:21]]Y Reg[IR[20:16]]R PC+IR[16:0]]

ALU Operation:R X op Y

R X op IR[16:0]

Opcode

Reg CSel Rd

Reg CWrite

i+4

instruction

instruction

i+4+disp

i+4+disp

Add

value

Rs Selection

Rs

Rs

Reg[IR[15,11]] RMDR Mem[R]

Mem[R] Y

Rt

LD Operation: Reg[IR[20:16]] MDR.

Page 45: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Multicycle ImplementationMulticycle Implementation

Example:ƮM = 200 picosecondsƮALU = 100 picosecondsƮAdder = 100 picosecondsƮReg = 50 picoseconds

Fastest Clock?

06:29 AM06:29 AM

Load Immediate/ALU: 4 Clocks

Load Memory: 5 Clocks

Store Memory: 4 Clocks

Type Instr. Mix

LI / ALU 52%

LD 25%

ST 10%

Cond. Jump 13%

Ʈclk = GHz

Conditional Jump: 3 Clocks

On Average: CPI = Instr. Exec. Time = ps

4545 / 54 / 54

Page 46: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Control ImplementationControl Implementation

06:29 AM06:29 AM

Control Unit

CU

Data Processing Unit

DPU or Datapath

• •

••

• •

Datapath Control Signals:ALU Operation, MUX Selection,

Memory Rd/Wr, etc

Datapath Status Signals:IR Fields, ALU Flags

4646 / 54 / 54

Page 47: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Control ImplementationControl Implementation

Hardwired

● Standard Logic Components

● Fast

● Not Flexible, i.e. Difficult to Change Control Operation

Microprogrammed

● Memory-Based

● Speed Function of Memory (slower than hardwired)

● Flexible Design

06:29 AM06:29 AM4747 / 54 / 54

Page 48: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Control ImplementationControl Implementation

Hardwired

● FiniteStateMachine

06:29 AM06:29 AM

State Register

• • •

• •

CombinationalControlLogic

• •

• Datapath Control Outputs

• • •

Datapath Control inputs

4848 / 54 / 54

Page 49: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Microprogrammed Control ImplementationMicroprogrammed Control Implementation

Each Linein the Micro-ProgramExecutesMicro-Operations(in 1 Clock)

Fetch,Decode,ExecuteCycle

06:29 AM06:29 AM

ALU Operation, MUX Selection,Memory Rd/Wr, etc

4949 / 54 / 54

Page 50: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Microprogram Control UnitMicroprogram Control Unit

Datapath Control Signals:

06:29 AM06:29 AM5050 / 54 / 54

Page 51: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Microprogram Control UnitMicroprogram Control Unit

06:29 AM06:29 AMC19 C0

1

Opcode

Funct

ZCyetc

AdderAdder

5151 / 54 / 54

Page 52: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Microprogram Control UnitMicroprogram Control Unit

Fetch Instruction

06:29 AM06:29 AM

IR M[PC]PC PC + 4

5252 / 54 / 54

0

1

μPC M0 S1 S0 C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4 C3 C2 C1 C0

Page 53: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Microprogram Control UnitMicroprogram Control Unit

Decode / Get Operands

06:29 AM06:29 AM

IR M[PC]PC PC + 4

X Reg[IR[25:21]]Y Reg[IR[20:16]]

R PC+4*IR[15:0]]

Opcode = 0

Funct = 100010

= 8

5353 / 54 / 54

0

10 0 1 1 1 0 1 0 0 0 0 0 1 00 0 0 0 0 1 0 0 1

μPC M0 S1 S0 C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4 C3 C2 C1 C0

Page 54: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Microprogram Control UnitMicroprogram Control Unit

Execute Instruction

06:29 AM06:29 AM

IR M[PC]PC PC + 4

X Reg[IR[25:21]]Y Reg[IR[20:16]]

R PC+4*IR[15:0]]

R X – Y

Opcode = 0

Funct = 100010

= 8

5454 / 54 / 54

1 0 0

0

1

8

9

0 0 1 1 1 0 1 0 0 0 0 0 1 00 0 0 0 0 1 0 0 1 μPC M0 S1 S0 C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4 C3 C2 C1 C0

1 1 0 1 1 0 0 1 0 1

Page 55: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Microprogram Control UnitMicroprogram Control Unit

Execute Instruction

06:29 AM06:29 AM

IR M[PC]PC PC + 4

X Reg[IR[25:21]]Y Reg[IR[20:16]]

R PC+4*IR[15:0]]

R X – Y

Opcode = 0

Funct = 100010

= 8

5555 / 54 / 54

1 0 0

0

1

8

9

0 0 1 1 1 0 1 0 0 0 0 0 1 00 0 0 0 0 1 0 0 1 μPC M0 S1 S0 C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4 C3 C2 C1 C0

0 0 1 0 0 1 0 0 1 1 0 1 0 1 1 0 1

Reg[IR[15,11]] R

1 1 0 1 1 0 0 1 0 1

Page 56: Princess Sumaya Univ. Computer Engineering Dept. Chapter 5:

Princess Sumaya University 22343 – Computer Organization & DesignPrincess Sumaya University 22343 – Computer Organization & Design Computer Computer Engineering Dept.Engineering Dept.Chapter 5Chapter 5