# power dissipation cmos

Post on 13-Dec-2014

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POWER DISSIPATIONTRANSCRIPT

- 1. Power DissipationCMOS

2. Outline Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power dissipation Metrics Conclusion 3. Need to estimate power dissipationPower dissipation affects Performance Reliability Packaging Cost Portability 4. Where Does Power Go in CMOS? Dynamic Power ConsumptionCharging and Discharging Capacitors Short Circuit CurrentsShort Circuit Path between Supply Rails during Switching LeakageLeaking diodes and transistors 5. Node Transition Activity and PowerDue to charging and discharging of capacitanceConsider switching a CMOS gate for N clock cyclesEN= 2 nNCLVddEN : the energy consumed for N clock cyclesn(N): the number o f 0->1 transition in N clock cyclesPavglimN ENN-------- fclk= nNN lim------------ C N LVdd2fclk= = lim0 1nN------------NN Pavg= C0 1L 2 fVddclk 6. Activity factors of basic gates AND OR XORA B A B (1 p p ) p p(1 )(1 )[1 (1 )(1 )] A B A B p p p p[1 ( 2 )]( 2 ) A B A B A B A B p p p p p p p p 7. Dynamic Power dissipation Power reduced by reducing Vdd, f, C and also activity A signal transition can be classified into two categories a functional transition and a glitch 8. Glitch Power Dissipation Glitches are temporary changes in the value of the output unnecessary transitions They are caused due to the skew in the input signals to a gate Glitch power dissipation accounts for 15% 20 % of theglobal power Basic contributes of hazards to power dissipation are Hazard generation Hazard propagation 9. Glitch Power Dissipation P = 1/2 .CL.Vdd . (Vdd Vmin) ;Vmin : min voltage swing at the output Glitch power dissipation is dependent on Output load Input pattern Input slope 10. Glitch Power Dissipation Hazard generation can be reduced by gate sizing and pathbalancing techniques Hazard propagation can be reduced by using less number ofinverters which tend to amplify and propagate glitches 11. Short Circuit Power Dissipation Short circuit current occurs during signal transitions whenboth the NMOS and PMOS are ON and there is a direct pathbetween Vdd and GND Also called crowbar current Accounts for more than 20% of total power dissipation As clock frequency increases transitions increaseconsequently short circuit power dissipation increases Can be reduced : faster input and slower output Vdd

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