porting helenos to risc-v
TRANSCRIPT
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http://d3s.mff.cuni.cz
Martin Děcký
CHARLES UNIVERSITY IN PRAGUE
Faculty of Mathematics and PhysicsFaculty of Mathematics and Physics
Porting HelenOS to RISC-VPorting HelenOS to RISC-V
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2Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
IntroductionIntroduction
Two system-level projectsRISC-V is an instruction set architecture,HelenOS is an operating system
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3Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
IntroductionIntroduction
Two system-level projectsRISC-V is an instruction set architecture,HelenOS is an operating systemBoth originally started in academia
But with real-world motivations and ambitionsBoth still in the process of maturing
Some parts already fixed, other parts can be still affected
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4Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
IntroductionIntroduction
Two system-level projectsRISC-V is an instruction set architecture,HelenOS is an operating systemBoth originally started in academia
But with real-world motivations and ambitionsBoth still in the process of maturing
Some parts already fixed, other parts can be still affected
→ Mutual evaluation of fitness
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5Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
IntroductionIntroduction
Martin DěckýComputer science researcher
Operating systemsCharles University in Prague
Co-author of HelenOS (since 2004)Original author of the PowerPC port
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7Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V in a NutshellRISC-V in a Nutshell
Free (libre) instruction set architectureBSD license, in development since 2014Goal: No royalties for analyzing, designing, manufacturing and selling chips (and related software)http://riscv.org
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8Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V in a Nutshell (2)RISC-V in a Nutshell (2)
Based on reduced instruction set (RISC) principlesDesign based on time-proven ideas, but avoiding mistakes and anachronisms
High-performance Z-scale, Rocket and BOOM prototype chips manufactured (at 45 nm and 28 nm)
Scalable and extendable clean-slate designFrom small embedded systems (low-power minimal 32-bit implementations)To large computers (powerful implementations, 64-bit or even 128-bit, SIMD, VLIW, etc.)
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9Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Context of RISC-VContext of RISC-V
Comparison with previous free ISAsOpenRISC, OpenSPARC, LaticeMico32, MMIX, Amber, LEONGoals of RISC-V
BSD instead of GPLModularity and scalabilitySupporting 32 bits and 64 bits (128 bits in the future)Not just for research and education
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10Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Context of RISC-V (2)Context of RISC-V (2)
Comparison with commercial ISAsIA-32, AMD64, IA-64, ARM
Complex or rather complexIntellectual property minefield
SPARC, POWER, MIPSStill intellectual property minefield
Old patent-free ISAs(ARMv2, Berkeley RISC, Stanford MIPS)
Obsolete
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11Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Context of RISC-V (2)Context of RISC-V (2)
Comparison with commercial ISAsGoals of RISC-V
FreeRelevantState-of-the-artPracticalReasonable complexity
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12Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Who Is behind RISC-VWho Is behind RISC-V
UC Berkeley, Computer Science DivisionKrste Asanović
Principal designerDavid Patterson
Coined the term RISC and led the original Berkeley RISC project (1980)
Later exploited in SPARC, Alpha and ARMCo-author of DLX (with John Hennessy for Computer Architecture: A Quantitative Approach)
Funding from DARPA, Intel, Microsoft and others
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14Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Who Is behind RISC-V (2)Who Is behind RISC-V (2)
RISC-V FoundationNon-profit corporation
Rick O'Connor (Executive Director)http://riscv.net
Governing the evolution of RISC-V ISAStandardization of extensionsIntellectual property matters (patents, logos, trademarks, etc.)
Founding membersGoogle, Hewlett Packard Enterprise, Lattice, Oracle, lowRISC and others
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15Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Implementors of RISC-VImplementors of RISC-V
Indian Institute of Technology MadrasPlan to produce six CPU designs based on RISC-V
BluespecPreliminary plan to produce RISC-V based CPUs
lowRISCNon-profit organization (cooperating with University of Cambridge and Raspberry Pi Foundation)Implementing open source SoC based on 64 bit RISC-V (scheduled for 2017)Tagged memory
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16Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Features of RISC-VFeatures of RISC-V
RISC architectureWord size of 32 or 64 bits
Word size of 128 bits possible in the future32 general-purpose registers (word-sized)
Load/store architectureR0 always contains 08 bit and 16 bit arithmetics via sign extensionPlain register file (no register windows, register stacks, etc.)
Optional 32 floating point registers (IEEE 754)Little-endian, byte-addressable memory
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17Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Features of RISC-V (2)Features of RISC-V (2)
RISC architecture32-bit instructions
Orthogonal instruction setLimited number of instruction templates
Fixed positions for specific opcode bits for fast decoding and immediate argument sign extension
Three-argument instructionsSynthetic instructions
R0 used to provide two-argument synthetic instructionsImplicit stackMandatory alignment of memory accesses
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18Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Features of RISC-V (3)Features of RISC-V (3)
Beyond RISCNo branch delay slotsNo condition codes, flag registers, carry bits
Conditions evaluated in branch instructionsPractical design of instruction encoding
Opcode bits designed to reduce the number of multiplexers
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19Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Features of RISC-V (4)Features of RISC-V (4)
Beyond RISCNative support for position-independent code
Address calculation relative to the program counterFused multiply-add by future accelerated decodingInstruction set extentions
Mandatory instruction setOptional (non-conflicting) extentions
Green-field and brown-field allocations
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20Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V Instruction SetRISC-V Instruction Set
op (7) rd (5) fnct3 (3) rs1 (5) rs2 (5) fnct7 (7)R-type
I-type op (7) rd (5) fnct3 (3) rs1 (5) immediate (12)
RV32I (Base Integer Instruction Set)
S-type op (7) imm (5) fnct3 (3) rs1 (5) rs2 (5) imm (7)
U-type op (7) rd (5) imm (20)
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21Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V Instruction Set (2)RISC-V Instruction Set (2)
RV32I (Base Integer Instruction Set)Computational
addition, subtraction, set less than, and, or, xor, shift left logical, shift right logical, shift right arithmetic, load upper immediate, add upper immediate to PC, no-op
Control transferunconditional jump (with link), branch (equal, not equal, less than, greater or equal)
Load and storeload, store, memory fence
Systemsystem call, breakpoint, CPU cycles, retired CPU instructions, wall-clock time
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22Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V Instruction Set (3)RISC-V Instruction Set (3)
RV64I (Base Integer Instruction Set)Essentially the same instructions as in RV32I (some variations accommodating the 64-bit word size)
Standard extensionsM (Integer Multiplication and Division)A (Atomic Instructions)
load-reserved, store-conditional, atomic memory operation (swap, addition, and, or, xor, max, min)
F (Single-Precision Floating Point)D (Double-Precision Floating Point)
General purpose ISA: RV64IMAFD = RV64G (164 instructions)
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23Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V Instruction Set (4)RISC-V Instruction Set (4)
More standard extensionsQ (Quad-Precision Floating Point)D (Decimal Floating Point)C (16-bit Compressed Instructions)B (Bit Manipulations)T (Transactional Memory)P (Packed-SIMD)
RV128I (Base Integer Instruction Set)Sketched
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24Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Features of RISC-V (5)Features of RISC-V (5)
Beyond RISCReserved opcodes for non-32-bit instructions
64-bit instructions, variable-length instructions, even instruction bundles (VLIW)Compressed instruction set
16-bit instructionsNo separate execution mode necessary(intermixed with 32-bit instructions)Code on average 20 % smaller than x86,2 % smaller than ARM Thumb-2
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25Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V Instruction LengthRISC-V Instruction Length
11bbbxxxxxxxxxxx xxxxxxxxxxxxxxxxx32-bit(bbb != 111)
aaxxxxxxxxxxxxxx16-bit(aa != 11)
48-bit 111110xxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx
64-bit 1111110xxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx ...
(80+16×n)-bit(n < 15) 1111111nnnnxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx ...
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26Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V Privileged Software StacksRISC-V Privileged Software Stacks
Application
Application Binary Interface
Application Execution Environment
Hardware Abstraction Layer
Hardware
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27Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V Privileged Software StacksRISC-V Privileged Software Stacks
Supervisor Binary Interface
Supervisor Execution Environment
Application
Application Binary Interface
Operating System
Application
Application Binary Interface
Hardware Abstraction Layer
Hardware
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28Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V Privileged Software StacksRISC-V Privileged Software Stacks
Supervisor Binary Interface
Application
Application Binary Interface
Operating System
Application
Application Binary Interface
Application
Application Binary Interface
Operating System
Application
Application Binary Interface
Supervisor Binary Interface
Hypervisor
Hypervisor Binary Interface
Hypervisor Execution Environment
Hardware Abstraction Layer
Hardware
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29Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V Privileged Software StacksRISC-V Privileged Software Stacks
Privilege LevelsMachine (M)Hypervisor (H)Supervisor (S)
Same set of privileged instructions
User/Application (U)Each level own set of Control and Status Registers (CSR)
4×1024 I/O space
Supported combinationsM
Embedded systemsM+U
Embedded systems with protection
M+S+UStandard OS
M+H+S+UStandard OS with virtualization
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30Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V Machine-Level ISARISC-V Machine-Level ISA
CSRsCPU and hardware thread IDMachine status (privilege level, interrupts)Memory management status
No memory translationSingle base-and-boundSeparate instruction/data base-and-bound32-bit virtual addresses (2-level hierarchical page tables)39-bit virtual addresses (3-level hierarchical page tables)48-bit virtual addresses (4-level hierarchical page tables)
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32Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
HelenOS in a NutshellHelenOS in a Nutshell
Microkernel multiserver operating systemBSD license, in development since 2004Goal: General-purpose usability, not limited by any specific use case or hardware platform, component-based design and implementationhttp://helenos.org
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33Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
HelenOS in a Nutshell (2)HelenOS in a Nutshell (2)ar
chit
ectu
re in
depe
nden
t
shar
ed a
rchi
tect
ure
depe
nden
t
arch
itec
ture
depe
nden
t
bootstraproutines
CPUmgmt
atomics&
barriers
I/Omgmt
platformmemory
mgmt
platformdrivers
debuggingsupport
contextswitching
interrupthandling
platformlibrary
routines
sharedplatformdrivers
shareddebugging
support
hierarchicalpage table
support
global pagehash table
support
hardware
layer
abst
ract
ion
kernelunittests
memorybackends
memoryzonesmgmt
frameallocator
slaballocator
addressspacemgmt
memoryreservation
spinlocks
waitqueues
workqueues
interrupt &syscall
dispatch
threadscheduler
thread &task
mgmt
kernellifecyclemgmt
lists,trees,
bitmaps
concurrenthashtable
genericresourceallocator
ELFloader
stringroutines
miscroutines
kernelconsole
IPC
kernellog
hardwareresource
mgmt
systeminformation
cycle &time
mgmt
tracingsupport
read-copy-
update
taskcapabilities
cachecoherency
synchro-nizationinterface
kernel
namingservice loader task
monitor
kloglocationservice logger
devicemanager
device drivers
clientsession
vterm bdsh
vfs
file systemdrivers
FAT exFAT ext4
ISO 9660 UDF MINIX FS
TMPFS Location FS
init
transportlayer protocols
tcp udp
link layerprotocols
loopip ethip
slip
inetsrv
networkingmanagement
dnsrsrv dhcp
nconfsrv
human interface
clipboard audio
outputinput
console compositor
remoteconsole
remoteframebuffer
Kernel subsystems System components
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34Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Features of HelenOSFeatures of HelenOS
Design based on explicit design principlesNon-fundamentalistic metaprincipleGeneral-purpose principleMicrokernel principleFull-fledged principleMultiserver principleSplit of mechanism and policy principleEncapsulation principlePortability principleModularity principle
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35Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Portability of HelenOSPortability of HelenOS
Supporting 8 hardware platformsIA-32, AMD64, IA-64, ARM, PowerPC, MIPS, SPARC V8, SPARC V9Portability case studies
Port to ARM in 53 days by 3 developersPort to SPARC V8 in 13 weeks by 1 developer
Porting efforts improve portabilityPortability simplifies future porting efforts
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36Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Portability of HelenOS (2)Portability of HelenOS (2)
Portability design principle“Do not be biased by any single hardware platform”
Reusable abstract algorithms4-level page tablesASID LRU managementinterrupt routing
Hardware Abstraction Layer defined by a virtual abs32le port
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37Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
HelenOS abs32leHelenOS abs32le
NO_TRACE static inline void atomic_inc(atomic_t *val){#ifdef CONFIG_SMP
asm volatile (”lock incq %[count]\n”: [count] ”+m” (val->count)
);#else
asm volatile (”incq %[count]\n”: [count] ”+m” (val->count)
);#endif /* CONFIG_SMP */}
Atomic increment on IA-32
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38Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
HelenOS abs32leHelenOS abs32le
NO_TRACE ATOMIC static inline void atomic_inc(atomic_t *val)WRITES(&val->count)REQUIRES_EXTENT_MUTABLE(val)REQUIRES(val->count < ATOMIC_COUNT_MAX)
{/* * On real hardware the increment has to be done * as an atomic action. */
val->count++;}
Atomic increment behavior summary on abs32le
plain C behavior summary
semantic annotations
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39Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
HelenOS RISC-V PortHelenOS RISC-V Port
ReasonsFuture combined verification of HW/SW correctness
Current statusStarted in January 2016Finished: Boot loader, initial memory management setup, kernel hand-off
Everything compilesMemory management data structures in place18 hours (net)
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40Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
HelenOS RISC-V PortHelenOS RISC-V Port
Demo
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41Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
HelenOS RISC-V Port (2)HelenOS RISC-V Port (2)
General approachCloning the abs32le virtual port
Changing names, endianity, word width, primitive types, linker script and other basic definitions
Adding the new platform to the build systemAdding basic options to HelenOS.configAdding the compiler toolchain to tools/autotool.py
Checking that everything compiles (mostly trivial)Gradually adding actual working implementation
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42Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
HelenOS RISC-V Port (3)HelenOS RISC-V Port (3)
#define EM_RISCV 243 /* RISC-V */
abi/include/abi/elf.h
.org DEFAULT_MTVEC + TRAP_VECTOR_RESETstart:
/* Set up stack, create stack frame */la sp, boot_stack + BOOT_STACK_SIZEaddi sp, sp, -16
j bootstrap
#define EM_RISCV 243 /* RISC-V */#define EM_RISCV 243 /* RISC-V */
boot/arch/riscv64/src/asm.S
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43Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
HelenOS RISC-V Port (3)HelenOS RISC-V Port (3)
#define EM_RISCV 243 /* RISC-V */#define EM_RISCV 243 /* RISC-V */#define ADDRESS_SPACE_HOLE_START UINT64_C(0x0000800000000000)#define ADDRESS_SPACE_HOLE_END UINT64_C(0xffff7fffffffffff)
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0
#define KERNEL_ADDRESS_SPACE_START_ARCH UINT64_C(0xffff800000000000)#define KERNEL_ADDRESS_SPACE_END_ARCH UINT64_C(0xffffffffffffffff)#define USER_ADDRESS_SPACE_START_ARCH UINT64_C(0x0000000000000000)#define USER_ADDRESS_SPACE_END_ARCH UINT64_C(0x00007fffffffffff)
kernel/arch/riscv64/include/arch/mm/as.h
/** Page Table Entry. */typedef struct {
unsigned long valid : 1; /**< Valid bit. */unsigned long type : 4; /**< Entry type. */unsigned long referenced : 1; /**< Refenced bit. */unsigned long dirty : 1; /**< Dirty bit. */unsigned long reserved : 3; /**< Reserved bits. */unsigned long pfn : 54; /**< Physical frame number. */
} pte_t;
kernel/arch/riscv64/include/arch/mm/page.h
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44Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
HelenOS RISC-V Port (4)HelenOS RISC-V Port (4)
Near futureBasic kernel functionality
Interrupt/exception handlingContext switching, atomicsETA: 18 – 24 hours (net)
Basic user space functionalityThread-local storageUser space context switchingI/OETA: 18 – 24 hours (net)
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45Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Current State of RISC-VCurrent State of RISC-V
User-level ISAVersion 2.0, frozen since May 6th 2014
Compressed ISAVersion 1.9, draft, to be frozen soon
Privileged ISAVersion 1.7, draft, expected to be frozen in mid-2016 or later
Vector ISAOnly sketched so far
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46Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Current State of RISC-V (2)Current State of RISC-V (2)
Holes in the specificationMemory consistency modelApplication Binary Interface (ABI)Performance countersHypervisor supportFormal specification (for verification)
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47Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Current State of RISC-V (3)Current State of RISC-V (3)
Holes in the specificationReference platform
Standard I/O locations (standard memory map)Debugging support (hardware breakpoints, JTAG)Interrupt controller, timer, RTC, reset mechanism, DMA, IOMMUPower managementStandard firmware (standard device tree)Standard boot loader
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48Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Current State of RISC-V (4)Current State of RISC-V (4)
Available toolingDevelopment tools
GNU Binutils, GCC, GDB, LLVM, clang, Go, libfEnviroments
Newlib, glibcSimulators / Emulators
Spike (MSIM-like), QEMU (80 % of privileged ISA), ANGEL (JavaScript), Simics, trace32
Not upstreamed yet
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49Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Current State of RISC-V (5)Current State of RISC-V (5)
Software stackFirmware
coreboot (on Spike, upstreamed)UEFI (a hack of EDKII on QEMU with PC peripherals)
Operating systemsLinux (with busybox), Yocto/OpenEmbeddedFreeBSD, NetBSD (to be upstreamed soon)seL4HelenOS (work-in-progress)
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50Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Preliminary Porting ObservationsPreliminary Porting Observations
RISC-V is like a mixture of MIPS and AMD64HelenOS generic 4-level page tables suitable for RISC-V
RISC-V compressed access permission field in page tables is more cumbersome than access bits
No forced platform-independent code change expectedHelenOS and RISC-V evaluate as good match for each other
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51Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Preliminary Porting ObservationsPreliminary Porting Observations
RISC-V underspecification causes only minor issues
Generally, the CPU specs are fine“Reference platform” documented only in the code of the Spike simulator
E.g. host-target interface implementing basic I/O devices using CSRs
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52Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
ConclusionConclusion
RISC-VInteresting and solid research/development effortGreat potential for both academia and industry
HelenOSRISC-V port underway, no roadblock in sightHistory of HelenOS portability improves future portability
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53Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Q&A
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55Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Backupslides
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56Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Context of RISC-VContext of RISC-V
Not the first free ISA, but the most degrees of freedom
OpenRISC2000, LGPL, based on DLX, fixed ISA (not extendable)
OpenSPARC2005, GPL, based on UltraSPARC T1 (SPARC V9), fixed configuration (i.e. number of cores, etc.)
LaticeMico322006, custom open source license (a mixture of several licenses), 32-bit
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57Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
Context of RISC-V (2)Context of RISC-V (2)
Not the first free ISA, but the most degrees of freedom
MMIX2009, a non-free open source license, Donald Knuth, John Hennessy and Richard Sites (inspired by Knuth's MIX), 64-bit, for educational purposes
Amber2010, LGPL, ARMv2 compatible (32-bit)
LEON2000-2010, LGPL + dual licensing, SPARC V8 compatible (32-bit)
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58Martin Děcký, FOSDEM, January 30th 2016 Porting HelenOS to RISC-V
RISC-V in AcademiaRISC-V in Academia
Highlights of research projects based on RISC-VFormal specification & verification
Chisel open source hardware construction language [UC Berkeley]Novel bespoke weak memory consistency models [MIT]
Novel manycore configurations [Gray Research]First experimental photonic CPU [UC Berkeley]Experimental ISA extensions [ETH Zürich]
Hardware loopsFaster ISA simulators using JIT [Cornell]