physical synthesis buffer insertion, gate sizing, wire sizing,

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Physical Synthesis Buffer Insertion, Gate Sizing, Wire Sizing, Slide 2 2 Physical Synthesis Wire delays Timing closure problem: Integration of synthesis with physical design Not very successful Reason: highly complex tasks Today, design closure: Multi-objectives must be managed: Performance Area Routability Yield Clock skew Power Signal integrity Slide 3 3 Physical Synthesis Physical synthesis: Modify netlist (decisions made at logic synthesis) after/during physical design to achieve design closure Primary purpose: to meet timing constraints (timing closure) Slide 4 4 Physical Synthesis Improve timing critical nets by: 1.Buffer insertion (BI) in the middle of the nets, 2.Gate sizing (GS) for the drivers, 3.Wire sizing, 4.Retiming. Automated BI and GS techniques have been integrated into the timing driven Place and Route design [1] [1] Astro Place and Route, Synopsys Inc. Can fix the timing problems without the iteration back to the logic design. Slide 5 5 Physical Synthesis Flow EC: identify high load gates, insert buffers, resize gate, . Netlist Preparation Initial (timing-driven) Placement and Optimization Timing Analysis Electrical Correction Legalization Cell overlaps (many buffers, many resized gates): Move cells not too far Big movements invalidates previous steps Trend: rely on incremental mode: legal locations are found for cells when they are inserted Slide 6 6 Physical Synthesis Flow (continued) CPO: Can run with incremental STA and legalization to optimize specific nets Routing Critical Path Optimization Compression Constraint met? Compression of remaining paths in the timing histogram Manual intervention And reiterate the flow Slide 7 7 Gate Sizing Needs multiple equivalent logic cells in the cell library High performance, low power, minimum area The tool can change equivalent cells after the placement to improve the timing or reduce the layout size or the power consumption. Small equivalent cell sizes have less circuit device area and thus less power. Can downsize the cells to reduce the power if the timing slack still keeps non-negative. Slide 8 8 Buffer (Repeater) Insertion The number of repeaters is expected to exceed 1 million in nano-scale VLSI systems Huge number of repeaters also results in high power dissipation IBM: 50% of leakage in inverters/buffers Repeater insertion with minimum power subject to timing constraints has been investigated. 0 10 20 30 40 50 60 70 80 90nm65nm45nm32nm %cells used as buffers [Saxena et al., TCAD 04] Slide 9 9 Buffer Model Buffer critical length (L crit ) The minimum net length above which inserting optimal sized and optimal-located buffer can reduce the delay compared to the unbuffered net [12]. At 45nm technology: L crit 235 micron sink source Slide 10 10 Feasible Region feasible region (FR) for one buffer B given a two-pin net a delay constraint T req, [x min, x max ] the maximum region where B can be located while still meeting the delay constraint. Jason Cong, An Interconnect-Centric Design Flow for Nanometer Technologies, Technical Report, 1999. Slide 11 11 Feasible Region runit length wire resistance, cunit length wire capacitance, T b intrinsic delay for the buffer C b input capacitance of the buffer, R b output resistance of the buffer. R d Drivers effective resistance. lwire length C L loading capacitance Slide 12 12 Feasible Region The distance of feasible region (y-axis) for inserting a buffer under different delay constraints (x-axis) for length 6mm to 9mm wires in the 0.18 micron technology x max -x min delay constraints Slide 13 13 Two-Dimensional FR When the route not specified: A 2D region union of 1D feasible regions of all possible routes Routing obstacles need to be deducted from the feasible region. Slide 14 14 Obstacles Buffers must be placed in layer 0 Require white space In Macrocell Design: between macros, suggested to design macros with holes inside[1] Slide 15 15 Obstacles In Standard Cell Design: Empty cells must be placed in placement stage. Slide 16 16 FR for Multiple Buffers When multiple buffers needed to meet the delay constraint: we can compute the FR of each buffer using a simple analytical formula (similar to above) assuming that all other buffers are taking their optimal positions. After a buffer is placed, we need to update the feasible regions of all other unplaced buffers of the same net to safely meet its delay constraint. Slide 17 References Reference: Alpert, Chu, Villarrubia, The coming age of physical design, ICCAD 2007. Further Reading: Alpert, et al, Techniques for fast physical synthesis, Proc. of The IEEE, 95(3), March 2007. 17

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