phoenix bios beep and error codes

BIOS

99 0789729741 DVD 3.07 06•09•2003 1:50 PM

2 BIOS

AMI BIOS POST Checkpoint CodesTable 1 AMI BIOS POST Checkpoint Codes for All AMI BIOS Products with a BIOSDate of 7/15/95 or Later

POST Code Description

D0h The NMI is disabled. Power on delay is starting. Next, the initialization code checksum will beverified.

D1h Initializing the DMA controller, performing the keyboard controller test, starting memory refresh, and entering 4GB flat memory mode next.

D3h Starting memory sizing next.

D4h Returning to real mode. Executing any OEM patches and setting the stack next.

D5h Passing control to the uncompressed code in shadow RAM at E000:0000h. The initializationcode is copied to segment 0, and control will be transferred to segment 0.

D6h Control is in segment 0. Next, checking whether Ctrl+Home was pressed and verifying the system BIOS checksum. If either Ctrl+Home was pressed or the system BIOS checksum is bad, next will go to checkpoint code E0h to perform FLASH BIOS Recovery. Otherwise, skip forward to check-point code 03h.

E0h Begin Flash BIOS Recovery. The onboard floppy controller, if available, is initialized. Next,beginning the base 512KB memory test.

E1h Initializing the interrupt vector table next.

E2h Initializing the DMA and interrupt controllers next.

E6h Enabling the floppy drive controller and timer IRQs. Enabling internal cache memory.

EDh Initializing the floppy drive.

EEh Looking for a floppy disk in drive A:. Reading the first sector of the disk.

EFh A read error occurred while reading the floppy drive in drive A:.

F0h Next, searching for the AMIBOOT.ROM file in the root directory.

F1h The AMIBOOT.ROM file is not in the root directory.

F2h Next, reading and analyzing the floppy disk FAT to find the clusters occupied by the AMIBOOT.ROM file.

F3h Next, reading the AMIBOOT.ROM file cluster by cluster.

F4h The AMIBOOT.ROM file is not the correct size.

F5h Next, disabling internal cache memory.

FBh Next, detecting the type of Flash ROM.

FCh Next, erasing the Flash ROM.

FDh Next, programming the Flash ROM.

FFh Flash ROM BIOS programming and recovery was successful. Next, restarting the system BIOSfrom the beginning.

03h Continuation of normal boot (without Flash BIOS Recovery). The NMI is disabled. Next, checking for a soft reset or a power-on condition.

05h The BIOS stack has been built. Next, disabling cache memory.

06h Uncompressing the POST code next.

07h Next, initializing the CPU and CPU data area.

08h The CMOS checksum calculation is done next.

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AMI BIOS POST Checkpoint Codes 3

Table 1 Continued


0Ah The CMOS checksum calculation is done. Initializing the CMOS status register for date and timenext.

0Bh The CMOS status register is initialized. Next, performing any required initialization before the keyboard Basic Assurance Test (BAT) command is issued.

0Ch The keyboard controller input buffer is free. Next, issuing the BAT command to the keyboardcontroller.

0Eh The keyboard controller BAT command result has been verified. Next, performing any necessary initialization after the keyboard controller BAT command test.

0Fh The initialization after the keyboard controller BAT command test is done. The keyboard com-mand byte is written next.

10h The keyboard controller command byte is written. Next, issuing the Pin 23 and 24 blocking and unblocking command.

11h Next, checking whether the End or Ins key was pressed during power on. Initializing CMOSRAM if the Initialize CMOS RAM in Every Boot AMIBIOS POST option was set in AMIBCP or theEnd key was pressed.

12h Next, disabling DMA controllers 1 and 2 and interrupt controllers 1 and 2.

13h The video display has been disabled. Port B has been initialized. Next, initializing the chipset.

14h The 8254 timer test will begin next.

19h The 8254 timer test is over. Starting the memory refresh test next.

1Ah The memory refresh line is toggling. Checking the 15-second on/off time next.

23h Continuation of normal boot. Reading the 8042 input port and disabling the MEGAKEY GreenPC feature next. Making the BIOS code segment writeable and performing any necessary config-uration before initializing the interrupt vectors.

24h The configuration required before interrupt vector initialization has completed. Interrupt vector initialization is about to begin.

25h Interrupt vector initialization is done. Clearing the password if the POST DIAG switch is on.

27h Any initialization before setting video mode will be done next.

28h Initialization before setting the video mode is complete. Configuring the monochrome mode andcolor mode settings next.

2Ah Bus initialization system, static, output devices will be done next, if present.

2Bh Passing control to the video ROM to perform any required configuration before the video ROM test.

2Ch All necessary processing before passing control to the video ROM is done. Looking for the video ROM next and passing control to it.

2Dh The video ROM has returned control to BIOS POST. Performing any required processing after thevideo ROM has control.

2Eh Completed post-video ROM test processing. If the EGA/VGA controller is not found, performing the display memory read/write test next.

2Fh The EGA/VGA controller was not found. The display memory read/write test is about to begin.

30h The display memory read/write test passed. Look for retrace checking next.

31h The display memory read/write test or retrace checking failed. Performing the alternate displaymemory read/write test next.

32h The alternate display memory read/write test passed. Looking for alternate display retrace checking next.

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4 BIOS

Table 1 Continued


34h Video display checking is over. Setting the display mode next.

37h The display mode is set. Displaying the power-on message next.

38h Initializing the bus input, IPL, and general devices next, if present.

39h Continuation of normal boot. Displaying bus initialization error messages.

3Ah The new cursor position has been read and saved. Displaying the Hit <DEL> message next.

3Bh The Hit <DEL> message is displayed. The protected mode memory test is about to start.

40h Preparing the descriptor tables next.

42h The descriptor tables are prepared. Entering protected mode for the memory test next.

43h Entered protected mode. Enabling interrupts for diagnostics mode next.

44h Interrupts enabled if the diagnostics switch is on. Initializing data to check memory wraparound at 0:0 next.

45h Data initialized. Checking for memory wraparound at 0:0 and finding the total system memorysize next.

46h The memory wraparound test is done. Memory size calculation has been done. Writing patterns to test memory next.

47h The memory pattern has been written to extended memory. Writing patterns to the base 640KBmemory next.

48h Patterns written in base memory. Determining the amount of memory below 1MB next.

49h The amount of memory below 1MB has been found and verified. Determining the amount ofmemory above 1MB next.

4Bh The amount of memory above 1MB has been found and verified. Checking for a soft reset and clearing the memory below 1MB for the soft reset next. If this is a power-on situation, going to checkpoint 4Eh next.

4Ch The memory below 1MB has been cleared via a soft reset. Clearing the memory above 1MB next.

4Dh The memory above 1MB has been cleared via a soft reset. Saving the memory size next. Going to checkpoint 52h next.

4Eh The memory test started, but not as the result of a soft reset. Displaying the first 64KB memorysize next.

4Fh The memory size display has started. The display is updated during the memory test. Performing the sequential and random memory test next.

50h The memory below 1MB has been tested and initialized. Adjusting the displayed memory sizefor relocation and shadowing next.

51h The memory size display was adjusted for relocation and shadowing. Testing the memory above 1MB next.

52h The memory above 1MB has been tested and initialized. Saving the memory size information next.

53h The memory size information and the CPU registers are saved. Entering real mode next.

54h Shutdown was successful. The CPU is in real mode. Disabling the Gate A20 line, parity, and theNMI next.

57h The A20 address line, parity, and the NMI are disabled. Adjusting the memory size depending on relocation and shadowing next.

58h The memory size was adjusted for relocation and shadowing. Clearing the Hit <DEL> messagenext.

59h Continuation of normal boot. The Hit <DEL> message is cleared. The <WAIT...> message is displayed. Starting the DMA and interrupt controller test next.

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AMI BIOS POST Checkpoint Codes 5

Table 1 Continued


60h The DMA page register test passed. Performing the DMA Controller 1 base register test next.

62h The DMA controller 1 base register test passed. Performing the DMA controller 2 base register test next.

65h The DMA controller 2 base register test passed. Programming DMA controllers 1 and 2 next.

66h Completed programming DMA controllers 1 and 2. Initializing the 8259 interrupt controller next.

67h Completed 8259 interrupt controller initialization.

7Fh Extended NMI source enabling is in progress.

80h The keyboard test has started. Clearing the output buffer and checking for stuck keys. Issuing thekeyboard reset command next.

81h A keyboard reset error or stuck key was found. Issuing the keyboard controller interface test command next.

82h The keyboard controller interface test completed. Writing the command byte and initializing thecircular buffer next.

83h The command byte was written, and global data initialization has completed. Checking for a locked key next.

84h Locked key checking is over. Checking for a memory size mismatch with CMOS RAM data next.

85h The memory size check is done. Displaying a soft error and checking for a password or bypassing WINBIOS Setup next.

86h The password was checked. Performing any required programming before WINBIOS Setup next.

87h The programming before WINBIOS Setup has completed. Uncompressing the WINBIOS Setup code and executing the AMIBIOS Setup or WINBIOS Setup utility next.

88h Returned from WINBIOS Setup and cleared the screen. Performing any necessary programmingafter WINBIOS Setup next.

89h The programming after WINBIOS Setup has completed. Displaying the power on screen message next.

8Bh The first screen message has been displayed. The <WAIT...> message is displayed. Performingthe PS/2 mouse check and extended BIOS data area allocation check next.

8Ch Programming the WINBIOS Setup options next.

8Dh The WINBIOS Setup options are programmed. Resetting the hard disk controller next.

8Fh The hard disk controller has been reset. Configuring the floppy drive controller next.

91h The floppy drive controller has been configured. Configuring the hard disk drive controller next.

95h Initializing the bus option ROMs from C800h next.

96h Initializing before passing control to the adapter ROM at C800h.

97h Initialization before the C800h adapter ROM gains control has completed. The adapter ROM check is next.

98h Continuation of normal boot. The adapter ROM had control and has now returned control toBIOS POST. Performing any required processing after the option ROM returned control.

99h Any initialization required after the option ROM test has completed. Configuring the timer data area and printer base address next.

9Ah Set the timer and printer base addresses. Setting the RS-232 base address next.

9Bh Returned after setting the RS-232 base address. Performing any required initialization before the coprocessor test next.

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6 BIOS

Table 1 Continued


9Ch Required initialization before the coprocessor test is over. Initializing the coprocessor next.

9Dh Coprocessor initialized. Performing any required initialization after the coprocessor test next.

9Eh Initialization after the coprocessor test is complete. Checking the extended keyboard, keyboardID, and Num Lock key next. Issuing the keyboard ID command next.

A2h Displaying any soft errors next.

A3h The soft error display has completed. Setting the keyboard typematic rate next.

A4h The keyboard typematic rate is set. Programming the memory wait states next.

A5h Memory wait state programming is over. Clearing the screen and enabling parity and the NMInext.

A7h NMI and parity enabled. Performing any initialization required before passing control to the adapter ROM at E000h next.

A8h Initialization before passing control to the adapter ROM at E000h completed. Passing control tothe adapter ROM at E000h next.

A9h Returned from adapter ROM at E000h control. Performing any initialization required after the E000h option ROM had control next.

AAh Initialization after E000h option ROM control has completed. Displaying the system configurationnext.

ABh Uncompressing the DMI data and executing DMI POST initialization next.

B0h The system configuration is displayed.

B1h Copying any code to specific areas.

00h Continuation of normal boot. Code copying to specific areas is done. Passing control to INT 19hbootstrap loader routine next.

AMI BIOS codes used by permission of American Megatrends, Inc.

Award BIOS POST Checkpoint CodesTable 2 Award BIOS POST Checkpoint Codes

Code Code Type Description

C0h Turn Off Chipset Cache OEM-specific cache control.

01h Processor Test 1 Processor status verification. It tests the following processor status flags: carry, zero, sign, and overflow.

02h Processor Test 2 Read/Write/Verify all CPU registers except SS, SP, and BP with data patterns FF and 00.

03h Initialize Chips Disable NMI, PIE, AIE, UEI, and SQWV. Disable video, parity checking, and DMA. Reset math coprocessor. Clear all page registers, CMOS shutdown byte. Initialize timers 0, 1, and 2, including set EISA timer to a known state. Initialize DMA controllers 0 and 1. Initialize interrupt controllers 0 and 1. Initialize EISA extended registers.

04h Test Memory Refresh RAM must be periodically refreshed to keep the memory from Toggle decaying. This refresh function is working properly.

05h Blank Video, Initialize Keyboard controller initialization.Keyboard

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Award BIOS POST Checkpoint Codes 7

Table 2 Continued

Code Code Type Description

07h Test CMOS Interface and Verifies CMOS is working correctly and detects a bad battery.Battery Status

Beh Chipset Default Program chipset registers with power-on BIOS defaults.Initialization

C1h Memory Presence Test OEM-specific test to size onboard memory.

C5h Early Shadow OEM-specific early shadow enable for fast boot.

C6h Cache Presence Test External cache size detection.

08h Set Up Low Memory Early chip set initialization. Memory presence test. OEM chipset routines. Clear low 64KB of memory. Test first 64KB memory.

09h Early Cache Initialization Cache initialization.

0Ah Set Up Interrupt Vector Initialize first 120 interrupt vectors with SPURIOUS_INT_HDLR andTable initialize INT 00h–1Fh according to INT_TBL.

0Bh Test CMOS RAM Checksum Test CMOS RAM checksum, if bad, or insert key pressed; load defaults.

0Ch Initialize Video Interface Detect type of keyboard controller (optional). Set NUM_LOCK status.

0Dh Initialize Video Interface Detect CPU clock. Read CMOS location 14h to find out type of video inuse. Detect and initialize video adapter.

0Eh Test Video Memory Test video memory; write sign-on message to screen. Set up shadow RAM; enable shadow according to setup.

0Fh Test DMA Controller 0 BIOS checksum test. Keyboard detect and initialization.

10h Continuation of normal Test DMA Controller 1; Test DMA controller 1.boot

11h Test DMA Page Registers Test DMA page registers.

14h Test Timer Counter 2 Test 8254 timer 0 counter 2.

15h Test 8259-1 Mask Bits Verify 8259 channel 1 masked interrupts by alternately turning off andon the interrupt lines.

16h Test 8259-2 Mask Bits Verify 8259 channel 2 masked interrupts by alternately turning off and on the interrupt lines.

17h Test Stuck 8259 Interrupt Turn off interrupts; then verify no interrupt mask register is on.Bits

18h Test 8259 Interrupt Force an interrupt and verify the interrupt occurred.Functionality

19h Test Stuck NMI Verify NMI can be cleared.

1Ah Display CPU Clock Display CPU clock speed.

1Fh Set EISA Mode If EISA nonvolatile memory checksum is good, execute EISA initialization.If not, execute ISA tests and clear EISA mode flag. Test EISA configurationmemory integrity (checksum and communication interface).

20h Enable Slot 0 Initialize slot 0 (system board).

21h-2Fh Enable Slots 1–15 Initialize slots 1–15.

30h Size Base and Extended Size base memory from 256KB to 640KB and extended memory Memory above 1MB.

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8 BIOS

Phoenix BIOS POST Beep CodesTable 3 Phoenix BIOS POST/Beep Error Codes

Code Beeps POST Routine Description

02h Continuation of normal boot Verify Real Mode

03h Disable Non-Maskable Interrupt (NMI)

04h Get CPU type

06h Initialize system hardware

08h Initialize chipset with initial POST values

09h Set IN POST flag

0Ah Initialize CPU registers

0Bh Enable CPU cache

0Ch Initialize caches to initial POST values

0Eh Initialize I/O component

0Fh Initialize the local bus IDE

10h Initialize Power Management

11h Load alternate registers with initial POST values

12h Restore CPU control word during warm boot

13h Initialize PCI Bus Mastering devices

14h Initialize keyboard controller

16h 1-2-2-3 BIOS ROM checksum

17h Initialize cache before memory autosize

18h 8254 timer initialization

1Ah 8237 DMA controller initialization

1Ch Reset Programmable Interrupt Controller

20h 1-3-1-1 Test DRAM refresh

22h 1-3-1-3 Test 8742 Keyboard Controller

24h Set ES segment register to 4GB

26h Enable A20 line

28h Autosize DRAM

29h Initialize POST Memory Manager

2Ah Clear 512KB base RAM

2Ch 1-3-4-1 RAM failure on address lines

2Eh 1-3-4-3 RAM failure on data bits of low byte of memory bus

2Fh Enable cache before system BIOS shadow

30h 1-4-1-1 RAM failure on data bits of high byte of memory bus

32h Test CPU bus clock frequency

33h Initialize Phoenix Dispatch Manager

36h Warm start shutdown

38h Shadow system BIOS ROM

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Phoenix BIOS POST Beep Codes 9

Table 3 Continued


3Ah Continuation of normal boot Autosize cache

3Ch Advanced configuration of chipset registers

3Dh Load alternative registers with CMOS values

42h Initialize interrupt vectors

45h POST device initialization

46h 2-1-2-3 Check ROM copyright notice

48h Check video configuration against CMOS

49h Initialize PCI bus and devices

4Ah Initialize all video adapters in system

4Bh QuietBoot start (optional)

4Ch Shadow video BIOS ROM

4Eh Display BIOS copyright notice

50h Display CPU type and speed

51h Initialize EISA board

52h Test keyboard

54h Set key click if enabled

58h 2-2-3-1 Test for unexpected interrupts

59h Initialize POST display service

5Ah Display prompt Press F2 to enter SETUP

5Bh Disable CPU cache

5Ch Test RAM between 512KB and 640KB

60h Test extended memory

62h Test extended memory address lines

64h Jump to UserPatch1

66h Configure advanced cache registers

67h Initialize Multiprocessor APIC

68h Enable external and CPU caches

69h Set up System Management Mode (SMM) area

6Ah Display external L2 cache size

6Bh Load custom defaults (optional)

6Ch Display shadow-area message

6Eh Display possible high address for UMB recovery

70h Display error messages

72h Check for configuration errors

76h Check for keyboard errors

7Ch Set up hardware interrupt vectors

7Eh Initialize coprocessor if present

80h Disable onboard Super I/O ports and IRQs

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10 BIOS

Table 3 Continued


81h Late POST device initialization

82h Detect and install external RS232 ports

83h Configure non-MCD IDE controllers

84h Detect and install external parallel ports

85h Initialize PC-compatible PnP ISA devices

86h Reinitialize onboard I/O ports

87h Configure motherboard configurable devices (optional)

88h Initialize BIOS data area

89h Enable Non-Maskable Interrupts (NMIs)

8Ah Initialize extended BIOS data area

8Bh Test and initialize PS/2 mouse

8Ch Initialize floppy controller

8Fh Determine number of ATA drives (optional)

90h Continuation of normal boot Initialize hard disk controllers

91h Initialize local bus hard disk controllers

92h Jump to UserPatch2

93h Build MPTABLE for multiprocessor boards

95h Install CD-ROM for boot

96h Clear huge ES segment register

97h Fix up multiprocessor table

98h 1-2 Search for option ROMs (one long, two short beeps onchecksum failure)

99h Check for SMART drive (optional)

9Ah Shadow option ROMs

9Ch Set up Power Management

9Dh Initialize security engine (optional)

9Eh Enable hardware interrupts

9Fh Determine number of ATA and SCSI drives

A0h Set time of day

A2h Check key lock

A4h Initialize Typematic rate

A8h Erase F2 prompt

AAh Scan for F2 keystroke

ACh Enter Setup

AEh Clear Boot flag

B0h Check for errors

B2h POST done; prepare to boot operating system

B4h 1 One short beep before boot

B5h Terminate QuietBoot (optional)

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Phoenix BIOS POST Beep Codes 11

Table 3 Continued


B6h Check password (optional)

B9h Prepare boot

BAh Initialize DMI parameters

BBh Initialize PnP option ROMs

BCh Clear parity checkers

BDh Display MultiBoot menu

BEh Clear screen (optional)

BFh Check virus and backup reminders

C0h Try to boot with INT 19

C1h Initialize POST Error Manager (PEM)

C2h Initialize error logging

C3h Initialize error display function

C4h Initialize system error handler

C5h PnPnd dual CMOS (optional)

C6h Initialize notebook docking (optional)

C7h Initialize notebook docking late

C8h Force check (optional)

C9h Extended checksum (optional)

D2h Unknown interrupt

E0h Initialize the chipset

E1h Initialize the bridge

E2h Initialize the CPU

E3h Initialize system timer

E4h Initialize system I/O

E5h Check force recovery boot

E6h Checksum BIOS ROM

E7h Go to BIOS

E8h Set Huge Segment

E9h Initialize Multiprocessor

EAh Initialize OEM special code

EBh Initialize PIC and DMA

ECh Initialize memory type

EDh Initialize memory size

EEh Shadow boot block

EFh System memory test

F0h Initialize interrupt vectors

F1h Initialize runtime clock

F2h Initialize video

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12 BIOS

Table 3 Continued


F3h Initialize System Management Mode

F4h 1 Output one beep before boot

F5h Boot to Mini DOS

F6h Clear Huge Segment

F7h Continuation of normal boot Boot to Full DOS

Phoenix BIOS beep codes used by permission of Phoenix Technologies, Ltd.

99 0789729741 DVD 3.07 06•09•2003 1:50 PM

phoenix bios beep and error codes

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