phase 2 -- logic implementation & simulation switching & logic design project
TRANSCRIPT
Phase 2 -- Logic Implementation & Simulation
Switching & LogicDesign Project
Overview Logic Implementation
Translation of Controller to VHDL Translation of Dataflow to BDF
Simulation Controller Dataflow Controller/Dataflow together
Rule 3 of Design
• All designs must have a controller! •And it must be a non-trivial controller (3 or more states).
No excepts permitted.
Translation of Controller to VHDL State Assignments
Compact NFLIP-FLOP=Log10NumState/Log102 One-Hot NFLIP-FLOP= NumStates
Add comments w/ Title, Group, Date, & Description
Use enumerated and state names (see handout)
Use CASE statement with embedded IF statements
Use Moore Outputs
Translation of Controller to VHDL Use a single process design Place Wait-UNTIL or IF statement
with clock at top of process WAIT UNTIL (clk’event AND clk = ‘1’); IF(clk’event AND clk = ‘1’) THEN ….
END IF;
Warning! Every IF statement must have an ELSE
statement even if there are ELSIF statements.
It is better to specify controller outputs using the conditional assignment statement, then a CASE statement in a process.
Do not write statements that lead to implied latches. That is, make sure that values for all outputs are specified at all times so VHDL does not assume that the present output is the previous output.
Warning! Remember that the VHDL programs the
logic gates in the MAX part that is running in parallel or concurrent.
All signals that are read in a process have to be listed in the sensitivity list, except for the "clock"-process, that is used for implementing registers. In this case, the inputs for the registers should be omitted.
Use parentheses in complex expressions in order to avoid ambiguities.
Warning! Use one processes for a state machine. Put outputs in conditional assignment
statements. All synchronous components must use
the same global clock. No ripple clocks allowed.
Every VHDL module must have a header specifying title, designers, date, and short description.
Warning! Don’t assign initial values to
signals and variables. All warnings are bad and good
designs have no warnings present.
Add comments--Title: Blackjack Controller--Designer: Dr. James Grover--Date: April 2006--Description: Controller for Blackjack game. This design --example was based on C.R. Clare's design in Designing Logic --Systems Using State Machines (McGraw Hill, 1972). The blackjack --machine plays the dealer's hand, using typical dealer strategies --to decide whether to draw another card (hit) or stand after --each round.----The example contains the following logic designs:-- 1. A State Machine that controls the game logic which include:-- (a) checking the status of the card reader.-- (c) making the decision of what action to take for a hit, -- stand or bust. An example is to draw a card if the -- hit signal is true.-- (b) making the decision of when to use the value 1 or 11 -- for an ace card.
. . . .-- adds the value of the drawn card.-- 3. A Binary-to-BCD converter for converting the 5-bit -- binary score and converts it to 2-digit BCD for the -- digital display.
State as Enumerated Types
ARCHITECTURE Behavioral OF Controller ISTYPE STATE_TYPE IS (sClear,sShowHit,…)SIGNAL State : STATE_TYPE;SIGNAL Ace, NextAce : BIT;
BEGIN
Use Case statements with If Statements
FSMLOGIC:PROCESS (Reset,CardIn,IsAce,Ace,CardOut,Hit,Bust,State)BEGINWAIT UNTIL (CLK’EVENT AND CLK = ‘1’);CASE State IS
WHEN sClear => --Reset StateNextAce <= '0';IF Reset = '1' THEN
State <= sClear;ELSE
State <= sShowHit;END IF;
. . . . .END CASE;END PROCESS FSMLOGIC;
Moore Outputs
OUTPUT02:WITH State SELECT
Sel <= "11" WHEN AddCard,"10" WHEN Add10,"01" WHEN Sub10,"00" WHEN OTHERS;
Dataflow With Title
Random Logic
ENTITY Bin2BCD IS PORT ( Tally : IN INTEGER Range 0 to 31; MSD,LSD : OUT BIT_VECTOR(3 DOWNTO 0));END Bin2BCD;
Random Logic
ARCHITECTURE behavioral OF Bin2BCD ISBEGINCombo01:WITH Tally SELECT
LSD <= "0000" WHEN 0,"0001" WHEN 1,"0010" WHEN 2,"0011" WHEN 3,. . . . ."0001" WHEN 31;
. . . . . .END Behavioral;
Registers and Adder
Tally
Combinational Logic & Display
Tally
Dataflow/Controller
Cascade Counters Use Cnt Enable nor Clk Enable Use common clock Use SCLR (synchronous clear)
Cooking Timer Consider
LPM_COUNTER LPM_DECODE LPM_MUX Hex7Seg Random Logic
UART (Rx) LPM_SHIFTREG LPM_COUNTER LPM_XOR (for parity if included) Random Logic
RC Servo and Stepper Motor LPM_COUNTER LPM_COMPARE LPM_CONSTANT LPM_FF for register Random Logic LPM_ADD_SUB for RC Servo
3-Man Rush LPM_COUNTER (binary or modulo
counter) LPM_SHIFTREG for PRSG (shift
register) LPM_CLSHIFT (barrel shifter) Random Logic Hex7Seg
Thermometer LPM_REG to hold data between
Reads Configure counter as decade or
BCD counters BCD
Simulation Simulate scenario that leads to
success Simulate scenario that leads to
fault condition (non success) Simulate scenario suggested by
laboratory assistant or instructor Simulate and verify simulation
Problems in the past Timer without state diagram Digit select on timer display
stopped in some states Did not use three folder/project
design One folder & project for controller One folder & project for dataflow One folder & project for dataflow &
controller combination
Problems in the past Did not include LPMs in project Each counter with different modulo
requires new LPM_COUNTER not just new instance of LPM_COUNTER.
Not using common clock causes ripple counter glitches in logic
Implementation Weeks