Operand Addressing and Operand Addressing and Instruction RepresentationInstruction Representation

Chapter 6Chapter 6

0, 1, 2, or 3 Address Designs0, 1, 2, or 3 Address Designs

Many processors do not allow an arbitrary Many processors do not allow an arbitrary number of operands because…number of operands because…

1) Variable length instructions require 1) Variable length instructions require more fetching and decoding, which is more fetching and decoding, which is inefficient compared to fixed length ones.inefficient compared to fixed length ones.

2) Fetching an arbitrary number of 2) Fetching an arbitrary number of operands takes time, causing the operands takes time, causing the processor to run slower.processor to run slower.

Zero Operands Per InstructionZero Operands Per Instruction

Also known as a Also known as a stack architecturestack architecture

Operands must be Operands must be implicitimplicit

Operands are fetched Operands are fetched from the top of the from the top of the stack and the result is stack and the result is placed back on the placed back on the stack.stack.

Ex: To add 7 to a Ex: To add 7 to a variable X…variable X…

push Xpush X

push 7push 7

addadd

pop Xpop X

One Operand per InstructionOne Operand per Instruction

Relies on an implicit operand – the Relies on an implicit operand – the accumulatoraccumulator

The accumulators value is extracted, The accumulators value is extracted, manipulated and restored.manipulated and restored.

Ex: Ex:

add Xadd X

Is applied asIs applied as

accumulator <- accumulator + Xaccumulator <- accumulator + X

1-Address Design Limitations1-Address Design Limitations

Works well for arithmetic and logical Works well for arithmetic and logical operations but can not copy memory operations but can not copy memory easily.easily.

Requires loading memory into the Requires loading memory into the accumulator and restoring it elsewhere.accumulator and restoring it elsewhere.

Especially slow at moving graphics objects Especially slow at moving graphics objects in display memory.in display memory.

2-Address Architecture2-Address Architecture

Overcomes limitations Overcomes limitations of 1-address of 1-address architecturesarchitectures

Operations can be Operations can be applied to a specified applied to a specified value instead of the value instead of the accumulatoraccumulator

To move memory:To move memory:move Q, Rmove Q, R

Copies data from Q to RCopies data from Q to R

To add:To add:add X, Yadd X, Y

Adds X and Y and Adds X and Y and stores the sum in Ystores the sum in Y

Y <- X + YY <- X + Y

3-Address Design3-Address Design

Not necessary but Not necessary but useful for processors useful for processors with multiple general-with multiple general-purpose registerspurpose registers

Third operand is used Third operand is used as a destinationas a destination

Ex:Ex:

add X, Y, Zadd X, Y, Z

Adds X and Y and Adds X and Y and stores the sum in Zstores the sum in Z

Z <- X + YZ <- X + Y

Operand Sources and Immediate Operand Sources and Immediate ValuesValues

Operands that specify a Operands that specify a source can be:source can be:

1) a signed constant1) a signed constant

2) an unsigned 2) an unsigned constantconstant

3) the contents of a 3) the contents of a registerregister

4) the value in a 4) the value in a memory locationmemory location

Operands that specify a Operands that specify a destination can be:destination can be:

1) a single register1) a single register

2) a pair of 2) a pair of contiguous registerscontiguous registers

3) a memory location3) a memory location

The Von Neumann BottleneckThe Von Neumann Bottleneck

Conventional computers Conventional computers use the Von Neumann use the Von Neumann architecture which stores architecture which stores both programs and data both programs and data in memoryin memory

Instructions stored in Instructions stored in memory means at least memory means at least one memory reference is one memory reference is needed per instructionneeded per instruction

Operands specifying Operands specifying locations in memory locations in memory require additional tripsrequire additional trips

Explicit and Implicit Operand Explicit and Implicit Operand EncodingEncoding

A string of bits is insufficient to represent A string of bits is insufficient to represent an operand as an instruction.an operand as an instruction.

The processor needs to know what the The processor needs to know what the bits representbits represent

There are two methods for specifying the There are two methods for specifying the interpretation of operandsinterpretation of operands

1) Implicit operand encoding1) Implicit operand encoding

2) Explicit operand encoding2) Explicit operand encoding

Implicit Operand EncodingImplicit Operand Encoding

The processor uses multiple opcodes for a The processor uses multiple opcodes for a given operation.given operation.

Each opcode corresponds to a particular Each opcode corresponds to a particular set of operandsset of operands

The list of opcodes may grow very largeThe list of opcodes may grow very large

Example:

opcode operands meaning--------------------------------------------------------------Add register r1, r2 r1<- r1+r2Add imm signed r1, imm r1<- r1+immAdd imm unsigned r1, Uimm r1<- r1+UimmAdd memory r1, mem r1<- r1+mem

Explicit Operand EncodingExplicit Operand Encoding

Associates the type of information with each Associates the type of information with each operandoperand

Operands That Combine Multiple Operands That Combine Multiple ValuesValues

Some processors can compute an Some processors can compute an operand value by extracting and operand value by extracting and combining values from multiple sourcescombining values from multiple sources

The register-offset approach requires each The register-offset approach requires each operand to specify a type, register, and operand to specify a type, register, and offset from that registeroffset from that register

Register-offset ExampleRegister-offset Example

The processor adds the contents of the offset The processor adds the contents of the offset field to the contents of the specified register to field to the contents of the specified register to obtain a value that is then used as the operandobtain a value that is then used as the operand

Ex: the first operand consists of the current Ex: the first operand consists of the current contents of register 2 minus the constant 17contents of register 2 minus the constant 17

Tradeoffs in The Choice of Tradeoffs in The Choice of OperandsOperands

There is no best operand design choice. There is no best operand design choice. Each has been used in practice.Each has been used in practice.

Each choice has a tradeoff between:Each choice has a tradeoff between:

1) ease of programming1) ease of programming

2) size of the code2) size of the code

3) speed of processing3) speed of processing

4) size of the hardware4) size of the hardware

Ease of ProgrammingEase of Programming

Complex forms of operands make programming Complex forms of operands make programming easiereasier

Allowing an operand to specify a register plus an Allowing an operand to specify a register plus an offset makes data aggregate references offset makes data aggregate references straightforwardstraightforward

A 3-address approach that provides an explicit A 3-address approach that provides an explicit target means the programmer does not have to target means the programmer does not have to write separate instructions to get the data to its write separate instructions to get the data to its final destinationfinal destination

Fewer InstructionsFewer Instructions

Allowing an operand to specify both a Allowing an operand to specify both a register and an offset results in fewer register and an offset results in fewer instructions.instructions.

Increasing the number of addresses per Increasing the number of addresses per instruction also lowers the number of instruction also lowers the number of instructionsinstructions

Fewer instructions makes each instruction Fewer instructions makes each instruction largerlarger

Smaller InstructionsSmaller Instructions

Limiting the number of operands, the set Limiting the number of operands, the set of operand types, or the maximum size of of operand types, or the maximum size of an operand keeps instructions small.an operand keeps instructions small.

Some of the smallest and least powerful Some of the smallest and least powerful processors limit operands to registers processors limit operands to registers (except for load and store operations)(except for load and store operations)

Increases the number of instructions Increases the number of instructions neededneeded

Larger Range of Immediate ValuesLarger Range of Immediate Values

The size of a field in the operand The size of a field in the operand determines the numeric range of determines the numeric range of immediate valesimmediate vales

Increasing the size allows larger values Increasing the size allows larger values but results in larger instructionsbut results in larger instructions

Faster Operand Fetch and DecodeFaster Operand Fetch and Decode

Limiting the number of operands and the Limiting the number of operands and the possible types of each operand allows possible types of each operand allows hardware to operate fasterhardware to operate faster

To maximize speed, avoid register-offset To maximize speed, avoid register-offset designs because hardware can fetch an designs because hardware can fetch an operand from a register much faster than it operand from a register much faster than it can compute the value from a register plus can compute the value from a register plus an offsetan offset

Decreased Hardware SizeDecreased Hardware Size

Decoding complex forms of operands Decoding complex forms of operands requires more hardware in a limited spacerequires more hardware in a limited space

Limiting the types and complexity of Limiting the types and complexity of operands reduces the size of the circuitry operands reduces the size of the circuitry requiredrequired

Decreased instruction size means Decreased instruction size means increased number of instructions and increased number of instructions and larger programslarger programs

Values in Memory and Indirect Values in Memory and Indirect ReferenceReference

Processors include at least one instruction Processors include at least one instruction whose operand is interpreted as a memory whose operand is interpreted as a memory address, which the processor fetchesaddress, which the processor fetches

Memory lookup helps ease of Memory lookup helps ease of programming but slows down performanceprogramming but slows down performance

Some processors extend memory Some processors extend memory references by permitting various forms of references by permitting various forms of indirectionindirection

Indirection ExamplesIndirection Examples If an operand specifies indirection through register 6, the If an operand specifies indirection through register 6, the

processor…processor…1) Obtains the current value from register 61) Obtains the current value from register 62) interprets it as a memory address and fetches the 2) interprets it as a memory address and fetches the operand from memoryoperand from memory

Indirection can be permitted through a memory address. Indirection can be permitted through a memory address. The operand contains a memory address, M, and specifies The operand contains a memory address, M, and specifies indirect reference. The processor…indirect reference. The processor…1) Obtains the value in the operand itself1) Obtains the value in the operand itself2) interprets it as a memory address and fetches the 2) interprets it as a memory address and fetches the value from memoryvalue from memory3) uses that value as another memory address, and 3) uses that value as another memory address, and fetches the operand from memoryfetches the operand from memory

Operand Addressing ModesOperand Addressing Modes

1)1) Immediate valueImmediate value2)2) Direct register referenceDirect register reference3)3) Indirect through a registerIndirect through a register4)4) Direct memory referenceDirect memory reference5)5) Indirect memory referenceIndirect memory reference