nutaq 4g/5g sdr solutions

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Nutaq 4G/5G SDR Solutions By Tristan Martin [email protected]

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Page 1: Nutaq 4G/5G SDR Solutions

Nutaq 4G/5G SDR Solutions

By Tristan Martin [email protected]

Page 2: Nutaq 4G/5G SDR Solutions

Company Profile

• Corporate headquarter in Quebec, Canada

• 55 employees

• 28 years of existence

• 5 PhDs and over 20 engineers

• Local technical support in China: Beijing (Hirain), Shanghai (CCEO), Chengdu (Yu He)

• Two revenue streams: Software Defined Radios (90%) & Engineering Services (10%)

• More than 15 years of using Xilinx and Matlab for signal processing

•Two divisions: Nutaq Innovation and NuRAN Wireless

Page 3: Nutaq 4G/5G SDR Solutions

Company Profile

Nutaq Innovation

• Flexible, programmable SDR platforms

• For researcher and development

• Open FPGA architecture (Xilinx)

• Matlab/Simulink and Xilinx tools

• “Technology eve” mendate

• Actively developing 4G & 5G

NuRAN Wireless

• Radio Access Network for Remote Locations

• Carrier grade GSM micro-BTS

• 2G BSC, 2G/3G Core Network and billing solution

• 10’000 BTS deployed in the field

• Lowest cost, lowest power consumption on the market

• Official OEM manufacturer of Facebook’s

Open Cellular 2G/4G plateforme

Page 4: Nutaq 4G/5G SDR Solutions

Paving the way to commercial 5G RAN

Nutaq Innovation (2017)

NuRAN Wireless (2021)

Ref: https://www.ericsson.com/networks/offerings/5g-radio

Page 5: Nutaq 4G/5G SDR Solutions

Nutaq Key Products

Wideband RF Digitizer

• SigInt, Spectrum Monitoring, EW, Radar

• 0 to 27 GHz (SDR)

• 500 MSPS (160 MHz IBW)

• 1 to 4 Rx channels per FPGA

TitanMIMO-6

• Phased array, MIMO Communications

• 0 to 6 GHz (SDR)

• 120 MSPS

• 8 TRx channels per FPGA

PicoLTE Network in a Box

• LTE, private network, testing, Highly configurable

•Rel13 Compliant, support NB IoT

• Standard and Non-Standard LTE bands (SDR)

• 2x 15dBM peak

We offer engineering services including application development & product customisation

Page 6: Nutaq 4G/5G SDR Solutions

Software Tool Flow

• Design Flow

Page 7: Nutaq 4G/5G SDR Solutions

TitanMIMO-6S

Very high channel density: 8 Tx and 8 Rx per FPGA (lower cost, less weight, less cables etc…)

• Radio640 • Based on Analog Device AD9361 RF Chip • 70 MHz to 6 GHz • 2x2 MIMO FMC (4x4 Double Stack) • Up to 56MHz OTA RT Bandwidth • Supports TDD and FDD Transmission Modes

Page 8: Nutaq 4G/5G SDR Solutions

Hardware Architecture

• Unique Point-to-Point links (7x 16 Gbps)

Page 9: Nutaq 4G/5G SDR Solutions

TitanMIMO-6S

Page 10: Nutaq 4G/5G SDR Solutions

Flexibility

• Every research project is different: different goals, different requirements, etc..

• Some measurements require:

high fidelity

high throughput

high storage capacity

• Depending on your goal, here are examples of “Signal Paths” that can be implemented

Massive MIMO testbeds

Page 11: Nutaq 4G/5G SDR Solutions

“On-board RAM” signal path

Page 12: Nutaq 4G/5G SDR Solutions

“On-board SSD” Signal Path

Page 13: Nutaq 4G/5G SDR Solutions

“Real-time” signal path

Page 14: Nutaq 4G/5G SDR Solutions

“Central CPU” signal path

Page 15: Nutaq 4G/5G SDR Solutions

“Distributed CPUs” signal path

Page 16: Nutaq 4G/5G SDR Solutions

Massive MIMO Ref Design

Parameter Value Note

Bandwidth 20MHz Occupied BW is 18MHz

Carrier frequency 2.4GHz or 5.5GHz (up to 6GHz)

Sampling rate 30.72MS/s IFFT/FFT sampling rate

FFT size 2048

Number of used subcarriers 1200 Few subcarriers are reserved for DC nulling and guard band

Slot time 0.5ms

Sub-frame time 1ms

Frame time 10ms

Number of user terminals (UTs) 16

Number of BS antennas 128 Scalable up to 256

Page 17: Nutaq 4G/5G SDR Solutions

Massive MIMO Ref Design

Page 18: Nutaq 4G/5G SDR Solutions

Phase/Gain Array Calibration

Status: Tx and Rx Phase/Gain automatic calibration implemented and released in 2016

We use a PN bit sequence (order 23) and apply QPSK modulation to generate a training sequence trough a reference transmitter used to measure the relative gain and phase offset between receive channels. Digital complexes multipliers are used to apply correction factors to each channel Rx channels to compensate for the measured gain and phase offset. The same process is applied to measure and compensate the relative gain and phase offset between transmit channels, using a reference receiver.

Page 19: Nutaq 4G/5G SDR Solutions

Calibration Design

• Calibration Steps: RX Calibration

RX Acquisition RX Calibration Factors Computation Setting Correction Factors on FPGA

Page 20: Nutaq 4G/5G SDR Solutions

Calibration Design

• Calibration Steps: TX Calibration

TX Acquisition TX Calibration Factors Computation Setting Correction Factors on FPGA

Page 21: Nutaq 4G/5G SDR Solutions

Phase/Gain Array Calibration

Before Rx calibration: phase and gain offsets can be observed

Page 22: Nutaq 4G/5G SDR Solutions

Phase/Gain Array Calibration

After Rx calibration: Phase within +/- 0.5 degrees, gain within 1%

Page 23: Nutaq 4G/5G SDR Solutions

Massive MIMO uplink

Multicarrier Massive MIMO uplink model implemented in 4 User Terminals (consisting of Zynq processor board and Nutaq radios) and 16x16 TitanMIMO BTS.

Page 24: Nutaq 4G/5G SDR Solutions

Massive MIMO uplink

The constellation shown below using ZF detection technique on 4 User Terminals simultaneously (multiuser MIMO).

4x UE Constellation at 5.05 GHz 4x UE Constellation at 2.45 GHz

Page 25: Nutaq 4G/5G SDR Solutions

Reciprocity Calibration

In modern communication systems, pilot symbols are transmitted from every antenna of a base station (BS) in the downlink channel and received at the terminal side, then sent back to the BS with channel state information (CSI) to calculate pre-coding coefficients. In Massive MIMO system, such a procedure would significantly degenerate the spectral efficiency due to the amount of feedback information and terminal processing power required from the large number of BS antennas. Instead, a more common approach is to compute proper pre-coding coefficients based on uplink CSI based on the reciprocity of the channel when the BS is operating in TDD mode. In wireless systems, we generally assume that the propagation channel is reciprocal. But the different transceiver radio frequency (RF) chains are usually not. Hence, we need to estimate the different frequency responses between the uplink and downlink hardware chains. Such a process is called reciprocity calibration. Status: reciprocity calibration method based on LS method and Argo method implemented in Matlab. LS method will be released as part of Ref Design in 2017

Page 26: Nutaq 4G/5G SDR Solutions

Massive MIMO downlink

Massive MIMO downlink implemented in Matlab code. Hardware integration is on-going. Over-the-Air results will be available in coming weeks…

Status: Will be released as part of Massive MIMO Ref Design in 2017

Page 27: Nutaq 4G/5G SDR Solutions

Clocking Module

• 10 MHz Reference Clock Input • 5V power supply • USB Connector

Status: Available since 2016

Page 28: Nutaq 4G/5G SDR Solutions

Antenna System

• 64-element TDD antenna array system • 64 WDPD.2458.B antennas elements • 2x16 array configuration • Half lambda separation at 2.4 GHz • SSMB to SMA cables •Mechanical design and assembly (plexiglass)

Status: Available in 2017

Page 29: Nutaq 4G/5G SDR Solutions

Development of new BBU

Development of new BBU to replace Kermode Octal V6

AMC

Xilinx Virtex UltraScale+

VU13P

Footprint B2104

416 I/O

76 GTY @ 32.75Gb/s

High-Pin-

Count FMC 1

DDR-3

MicroBlaze code

128 MB

High-Pin-

Count FMC 2

DDR4 SODIMMFlash memory

64 MB

Port 0-3MGT (x4)

Port 4-7MGT (x4)

Port 15GPIO (x2) or LVDS (x1)

Port 17-20GPIO (x8) or LVDS (x4)

FCLKA

IPMI (I2C)

TCLKA, TCLKC(input only)

RTM

RTM 0-3MGT (x4)

RTM 4-7MGT (x4)

RTM 8-11MGT (x4)

RTM 12-15MGT (x4)

MGT (x4)

RTM 20-23MGT (x4)

RTM 24-27MGT (x4)

RTM 28-31MGT (x4)

JTAG

LA[00-33] P-N (full)

HA[00-23] P-N (full)

HB[00-21] P-N (full)

CLK0_M2C, CLK1_M2C

10 GTY 10Gb/s

2 GTY CLK

Module

management

controller (MMC)

I2C

Switch

Carrier I2C

devices

I2C

Ma

ste

r

Ma

na

ge

me

nt I/O

s

RTM

JTAG

priority

switch

Mestor interface

JTAG interfaces (FPGA/IPMI)

User I/Os: 14 LVDS pairs

FPGA UART interface

Us

er I/O

s

UA

RT

IPM

I

JT

AGJTAG

chain

TCLKB, TCLKD(bidir)

UA

RT

FM

C2_

CL

K2

FM

C2_

CL

K3

FMC2_CLK2_BIDIR

FMC2_CLK3_BIDIR

TCLKA

TCLKC

FMC1_CLK2_BIDIR

FMC1_CLK3_BIDIR

TCLKA

TCLKC

FMC1_CLK2

FMC1_CLK3

LA[00-33] P-N (full)

HA[00-23] P-N (full)

HB[00-21] P-N (full)

CLK0_M2C, CLK1_M2C

10 GTY 10Gb/s

2 GTY CLK

100

MHz

RTM 16-19

Port 8-11MGT (x4)

Status: Design Stage. Expected release 2018