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ITU G.729 Voice Encoder November 29, 2011 Final Presentation

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Page 1: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

ITU G.729 Voice Encoder

November 29, 2011

Final Presentation

Page 2: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Team MembersTroy HuguetComputer EngineerPost-Route Testing

Parker JacobsComputer EngineerPost-Route Testing

Michael McCoyComputer Engineer

Microblaze Programmer

Cooper McClainComputer Engineer

Top Level Development

Nicholas RobinsonComputer Engineer

Top Level Development

Page 3: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Outline

• Background• Problem• Solution• System Overview • Constraints

o Technical o Practical

• Design Decisions• Testing• State of Project• Current Plans

Page 4: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Background

• G.729 protocol provides a highly intelligible voice codec with low bandwidth requirements.

 • NASA is currently searching for a hardware based (FPGA)

alternative to their current DSP-based G.729 system.

Page 5: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Problem - Power Consumption

• Mathematical complexity of G.729 algorithm

• CPU system requires multiple clock cycles per instruction

• High frequency CPU requirements in order to meet timing goals

• More clock cycles = more power

Page 6: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Solution - ITU G.729 FPGA Encoder

• FPGA implementation of ITU G.729 Encoder Algorithm

• Multiple math functions in a single clock cycle

• Reduction in frequency

Page 7: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

System Overview

Page 8: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Name Description

Time The encoder must completely process a single frame in less than 10 ms.

Power The encoder must consume less than 1.8W during activity.

Input The encoder must be able to interpret three 80x16-bit frames of sampled input

Output The output of the FGPA encoder must provide a bit-exact representation of the ITU C model.

Size The synthesized project must fit onto one Xilinx Virtex-5 FPGA

Technical Constraints

Page 9: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Practical Constraints

Category Name Description

Sustainability Readability The RTL code must be structured around a set of linting rules.

Sustainability Modularity The encoder must be modular in design for maintenance and optimization

Page 10: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Readability

• Code must be structured around linting rules • Linting Rules:

o Proper formatting of white spaceo Line lengtho Indentationso Bracing styles

• Why is this important?

Page 11: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Modularity

• Maintenanceo System debugging can be done on smaller amounts of

code  

o Allows for simple integration into top level • Distribution

o Different modules can be assigned to individual group members

Page 12: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Design Modifications

• New Top Level Testbencho Originally only tested the newest integrated submodule o Regressively test all integrated submodules

 • Extension of the memory

o Originally 11 bits (2048 locations)o Now 12 bits (4096 locations)

Page 13: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Top Level Testing

  • Verify the output of the Top Level

• Behavioral simulation is very fast but does not consider timing delays

• Need to be able to verify timing for constraint purposes 

Page 14: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Current State of Project

• RTL gives correct output for 100+ iterations • Issues

o Timing issues showing up in reportso Issues with clocking the encoder

 • Microblaze to Encoder Interface

Page 15: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

RTL Progress

• Encoder is fully integrated   • 100+ iterations of Encoder gives correct output out of 128

 • Encoder has errors beyond this point to be fixed

Page 16: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Timing Issues

• The target frequency of 50 MHz has not been met • Analysis of critical paths within the design is being done to

eliminate timing delays and achieve the target frequency • Isolation of sub modules in the top level is the current

approach with the anticipation of eliminating false paths

Page 17: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Microblaze Encoder Interface Progress

• Test Interfaceo Tests that the Interface module can send

and receive data to an instantiated module

• Clocking the Encodero Figure out what speed the complete encoder will run at by

adjusting the clock of the microblaze  • Finishing the Encoder

o Instantiate smaller pieces of the encoder and run them on the board to verify their output

Page 18: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Size Verification

• Total Slice LUTs: 69,120

•  Approximately 76% of the board

•  G.729: 43,157 LUTs

•  Microblaze: 9,752 LUTs

Page 19: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Current Plan

• Finish debugging of top level  • Identify critical paths by running synthesis on smaller

segments of encoder  • Find frequency at which encoder runs on FPGA

Page 20: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

References [1] T.Morris, “Field Programable Gate Array (FPGA) Based Speech Encoding,” unpublished

[2] ITU. (2007, January). ITU-T Recommendation of G.729 [Online].Available:http://www.itu.int/rec/dologin_pub.asp?lang=e&id=T-REC-G.729-200701-I!!SOFT-ZST-E&type=items

Page 21: November 29, 2011 Final Presentation. Team Members Troy Huguet Computer Engineer Post-Route Testing Parker Jacobs Computer Engineer Post-Route Testing

Questions?