Appl. Phys. A 71, 681–688 (2000) / Digital Object Identifier (DOI) 10.1007/s003390000450 Applied Physics AMaterialsScience & Processing

Novel template-based semiconductor nanostructures andtheir applicationsB. Das1, S.P. McGinnis2

1 Department of Computer Science and Electrical Engineering, West Virginia University, Morgantown, WV 26506-6109, USA(Fax: +1-304/293-8602, E-mail: das@csee.wvu.edu)2 Advanced Nano Devices, LC, 114 Morgan Drive, Morgantown, WV 26505, USA(Fax: +1-304/293-8602, E-mail: nanodev@aol.com)

Received: 16 November 1999/Accepted: 24 November 1999/Published online: 13 September 2000 – Springer-Verlag 2000

Abstract. In this paper we present a novel template-basedtechnology for the fabrication of large, periodic arrays ofsemiconductor nanostructures that is inexpensive, reliable,suitable for the fabrication of a variety of semiconductors,and is compatible with the standard CMOS process. The tech-nique uses material growth on a preformed template formedby electrochemical etching (anodization) of a thin film ofaluminum deposited on an arbitrary substrate. The templatecontains a periodic array of pores in which the nanostruc-ture materials are synthesized. The nanostructure size andperiodicity can be controlled by controlling the anodizationconditions. We are currently using this fabrication techniqueto develop a variety of optoelectronic devices, brief descrip-tions of which are also presented.

PACS: 07.07.Df; 81.05.Zx; 85.30.Vw

The development of low-dimensional semiconductor nanos-tructures has been the focus of research and development overthe past 25 years due to the enhancement in electronic and op-tical properties which occurs when electrons are strongly con-fined in one, two, or three dimensions. The commercial valueof this class of technology can be seen in the widespread useof semiconductor lasers and high electron mobility transistorsbased on quantum confinement in one dimension (quantumwells). However, it has been theoretically [1–3], and exper-imentally [4–7], demonstrated that semiconductor quantumwires and quantum dots, where electrons are confined in twoand three dimensions respectively, can provide significant fur-ther enhancement of device performance. In addition, theselow-dimensional structures emit and absorb light in an ex-tremely narrow spectral range which can be controlled by theshape, size, composition, and doping of the nanostructure [8].These effects have recently been exploited to fabricate pre-liminary quantum dot lasers [9–11].

While the potential of semiconductor nanostructures isclear, their applications have been limited by the lack ofa fabrication process suited to economical volume produc-tion. The initial method of nanostructure fabrication used

electron-beam lithography to define the structures on a mo-lecular beam epitaxy (MBE)-grown film which were thenetched using reactive ion etching (RIE) [2]. However, due tothe serial nature of e-beam lithography, this method is notsuitable for the fabrication of large arrays of nanostructuresneeded for most practical applications. In addition, this tech-nique has been shown to cause process-related damage whichcan significantly degrade device performance [12]. This hasled to the development of a number of ‘nanogrowth’ tech-niques where the semiconductor material is synthesized in thesize and shape of a quantum wire or a dot. Strain-inducedepitaxial growth [13], and chemical synthesis in glass di-electric matrices [14] can produce large arrays of semicon-ductor nanostructures in the required size range (1–100 nm),although these techniques lack the desired control over devicesize and array periodicity [15]. Capped colloidal nanostruc-tures have been fabricated with great success for experimen-tal investigations of basic electronic and optical processesin nanostructures [16]; however, since the resulting quan-tum dots are suspended in a liquid solution, their practicalapplications are uncertain due to packaging and reliabilityproblems. Therefore, there is a need for a process to eco-nomically fabricate large periodic arrays of semiconductornanostructures that will allow (a) the size and compositionof the nanostructures to be varied, (b) encapsulation of thesemiconductor nanostructures in a rugged host material, (c)flexibility to use a variety of substrate materials, and prefer-ably, (d) compatibility with standard silicon CMOS fabrica-tion techniques.

We have developed such a technology for the electro-chemical fabrication of large, periodic arrays of semicon-ductor nanostructures. The technique uses material growthon a preformed template formed by electrochemical etching(anodization) of a thin film of aluminum deposited on an ar-bitrary substrate. The template contains a periodic array ofpores in which the nanostructure materials are synthesized.The nanostructure size and periodicity can be controlled bycontrolling the anodization conditions. The technique is in-expensive, reliable, suitable for the fabrication of a varietyof semiconductors, and compatible with the standard CMOSprocess. We are currently using this fabrication technique to

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develop a variety of different optoelectronic devices. The ob-jective of this paper is to present a detailed description of thefabrication technique, as well as a brief report on the devicesthat are currently under development.

1 The fabrication technique

The nanostructure devices are fabricated by (a) first creatingan alumina template containing a periodic array of pores ona desired substrate, and (b) then depositing the desired semi-conductor material in the pores. Since alumina (Al2O3) iselectrically insulating (1018 Ω-cm resistivity), optically trans-parent over a wide energy band, and chemically robust, it is anideal embedding material for optical and electronic devices.

1.1 Template fabrication

When aluminum is anodized in a suitable oxidizing acid,a two-dimensional hexagonal lacework of quasi-periodicAl2O3 cells with uniform tubular pores is formed, a schematicof which is shown in Fig. 1. The structure was first character-ized by Keller, Hunter, and Robinson [17] as a close-packedarray of columnar hexagonal cells each containing a cen-tral pore normal to the substrate surface. The pore diameterand the cell wall thickness depend on the anodization condi-tions such as type and pH of the anodizing acid, temperature,anodizing current density, and substrate conditions. Thesevalues can be precisely controlled to form pore diameters be-tween 4 and 100 nm, with cell wall thicknesses between 4 andseveral 100 nm [18–21]. Due to the excellent periodicity ofthese pores, and the ability to precisely control the pore diam-eters, such anodized alumina films can act as ideal templatesfor the fabrication of periodic semiconductor nanostructurearrays. In recent years, researchers have also reported self-organized pore growth leading to a nearly perfect, denselypacked hexagonal pore structure for a narrow set of pro-cessing parameters [22–24]. A systematic investigation byJessensky et al. suggests that the cause of this self-orderingbehavior is mechanical stress which leads to a repulsive in-teraction between neighboring pores [22]. This phenomenon

Fig. 1. Periodic hexagonal lacework of alumina cells formed by anodizationof aluminum

has the potential for further improvement of the pore peri-odicity and size control, resulting in more uniform arrays ofsemiconductor nanostructures.

Anodization is performed in an inexpensive apparatus(Fig. 2a) where the aluminum layer is used as the anode,and a platinum electrode is used as a cathode. Anodizationcan be performed under constant-current or constant-voltageconditions; in this report we will restrict to constant-currentanodizations for the sake of simplicity. Although the poreformation mechanism during anodization is not yet fully un-derstood, it is believed to take place in the following steps.During the first 3–5 s of anodization, a thin non-porous filmof alumina (Al2O3) called the barrier layer, is formed on topof the aluminum film. As anodization is continued, an ar-ray of pores develop on the barrier layer, whose diametersincrease until reaching a final dimension determined by theanodization conditions. Once the final diameter is reached,the diameter of the pores does not increase any further, andas the anodization is continued, the pore depths increase ata rate proportional to the anodization current. A convenientway to monitor the anodization process is to observe thevoltage–time characteristics measured between the anode andthe cathode. Since the potential across the device is propor-tional to the device resistance, it increases during the first3–5 s when the high-resistance barrier layer is formed. Next,as the pores start to develop, the potential decreases until thefinal pore diameter is reached, after which the potential re-mains constant as the pores propagate. The pore formationmechanism in aluminum and a typical voltage–time charac-teristic is shown in Fig. 2b.

Fig. 2. a Schematic diagram of a typical anodization apparatus.b Pore for-mation mechanism in aluminum substrates and corresponding voltage–timecharacteristics

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The anodization of aluminum is a well-established in-dustrial process, and due to their special structural features,anodic alumina films have been long used in industry forchromatic and anti-corrosion coatings [25]. However, the alu-minum anodization until now has been limited to aluminumsubstrates, which are not appropriate for electronic or pho-tonic device applications. We have extended this technique tothe anodization of aluminum thin films deposited on a var-iety of planar substrates, with an emphasis on silicon andglass. This approach provides the advantages of (i) a high-purity aluminum film, (ii) integration with silicon electronicdevices, (iii) better process control, and (iv) as described be-low, the ability to control thelength as well as the diameter ofthe semiconductor nanostructures. The fabrication techniqueis also compatible with silicon CMOS processing technol-ogy. As an example for silicon substrates, the silicon waferis first cleaned using the SummaClean technique, and the na-tive oxide layer is stripped using an HF dip. Next a thick layerof aluminum is thermally evaporated on the back side of thesilicon wafer and annealed to provide a good ohmic contactfor anodization. A thin film of aluminum is then deposited onthe top of the substrate using thermal evaporation and a low-temperature annealing step is performed to ensure good adhe-sion of the layer to the substrate. The top aluminum layer isthen anodized at a constant current in sulfuric acid to form theuniform tubular pores. The acid solution is circulated usinga Masterflex peristalsis pump and chilled using a Julabo F10chiller to prevent heat buildup at the aluminum/electrolyte in-terface. The anodization process is monitored by recordingthe potential as a function of time, as described earlier.

The fabrication parameters and the data for a typical tem-plate fabrication process are shown below. The substrate usedwas a p-type silicon wafer with 0.3Ω-cm resistivity. A backcontact was formed on the wafer by depositing a 1-µm-thicklayer of aluminum and then annealing it at 450C. Next,a 0.5-µm-thick layer of aluminum was deposited on top ofthe wafer by thermal evaporation. The substrate was then an-nealed at 400C for 30 min to provide good adhesion of thealuminum to the substrate. The top aluminum layer was thenanodized in 15% sulfuric acid solution for 1 min at a currentdensity of 30 mA/cm2.

Figure 3 shows the voltage–time characteristic observedfor the Al/silicon system during anodization. As expected,the potential increases initially during barrier layer forma-tion, then decreases during pore widening, and then finallylevels off at the onset of pore propagation. An interestingfeature in Fig. 3 is the complex potential profile observedat the end of the anodization period. When bulk aluminumis anodized, the voltage–time characteristic remains constantonce the final pore size is attained (Fig. 2b). However, whenthin films of aluminum are anodized, the pores eventuallyreach the substrate, which is reflected in the voltage–timecharacteristics by a sharp rise in the voltage. The data inFig. 3 allows precise determination of the pore propagationrate from the known values of aluminum layer thickness andpore-propagation time. The experimentally determined pore-propagation rates for the Al/silicon system at different cur-rent densities are shown in Fig. 3, which increases linearlywith current density as expected. The anodization rates inFig. 3 can be used to precisely control the depths of the tem-plate pores, which is one of the advantages of using aluminumthin films. The transmission electron microscope (TEM) mi-

Fig. 3. Anodization of aluminum thin films deposited on silicon. Thepotential–time characteristic observed during constant-current anodization,and experiemntally determined pore formation rate as a function of theanodization current density

Fig. 4. TEM picture of the periodic array of pores formed on thealuminum/silicon system. The average pore diameter shown in theinset is13 nm

crograph of a typical alumina template on silicon is shown inFig. 4, with the inset showing the structures at a higher magni-fication. The average pore diameter in Fig. 4 is 13 nm, whichalso shows excellent pore periodicity.

1.2 Semiconductor nanostructure synthesis

The semiconductor nanostructures are synthesized by selec-tive electro-deposition of the desired semiconductor materialinside the template pores from an appropriate chemical so-lution. A number of other techniques have also been investi-gated for material synthesis, however, this electro-depositionmethod provides the best selectivity and control over mate-rial growth. By using this technique, we have successfullyfabricated nanostructure arrays of CdS and ZnS inside the

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template pores [27]. As an example, for the synthesis of CdS,a solution of dimethylsulphoxide (DMSO) with dissolvedCdCl2 and elemental sulfur is used. After the material is syn-thesized, it is encapsulated in aluminum hydroxide by a hy-drolyzation step. Recently, another research group has useda similar technique to synthesize CdS, CdSe, CdSxSe1−x ,CdSxSe1−x , CdxZn1−xS, and GaAs quantum wires on alu-mina templates using aluminum substrates [26]. Quantitativeelectron microscopy of the materials indicates correct stoi-chiometry, and X-ray diffraction analysis indicates that thistechnique forms single-crystal material, with crystal orien-tation dependent on the nanostructure size. The results pre-sented in [26] are for nanostructures synthesized in templatesformed on bulk aluminum, which is different from the thin-film aluminum template that we have concentrated on. How-ever, the independent verification of this synthesis techniqueby another group gives us confidence in this method and alsoindicates the extension of this technique to more complexternary material systems.

This fabrication technique has several advantages for theproduction of commercial devices. First, it has the demon-strated ability to produce nanostructures with sizes down to4 nm, with good size control (10%), and good periodicity. Inaddition, with the recent discovery of the self-organized poreformation mechanism, it appears that the uniformity and pe-riodicity can be substantially improved. Second, the chemicalsynthesis method described can produce a wide variety of ma-terials, including the ability to form alloys and doped semi-conductors. Finally, the fabrication process is directly com-patible with standard silicon CMOS fabrication techniques.The only technique not commonly used in CMOS fabricationis the electrochemical pore formation and semiconductor syn-thesis steps. However, it should be noted that these proceduresare becoming increasingly common in advanced ULSI pro-cesses to form copper interconnects.

2 Applications

We are currently using the template-based fabrication tech-nology to implement a variety of nanostructure-based de-vices. The following sections provide a brief summary of thedevices under development.

2.1 High-efficiency multijunction nanostructure solar cells

Solar cells based on thin films are promising for large-scale commercial applications due to their low manufacturingcosts [28, 29]. However, a major problem with thin film tech-nology is material non-uniformity associated with the fabrica-tion of large-area films. We are currently using the template-based fabrication technique to develop high-efficiency solarcells based on semiconductor nanostructures that will elim-inate the problem of spatial nonuniformity while retainingthe low-cost advantage of thin film manufacturing. In add-ition, we believe that this technology will provide (i) highefficiency, (ii) low manufacturing cost, and (iii) long-termreliability.

Nanostructure-based PV cells have been previously pro-posed due to their potential to provide a very high energy

conversion efficiency [28]. This large energy conversion ef-ficiency results from the following effects: (a) nanostruc-ture crystallite sizes are comparable to the carrier scatteringlengths, which significantly reduces the carrier scattering rate,thus increasing the carrier collection efficiency; and (b) thestrong absorption coefficient of nanostructures due to the in-creased density of states. In addition, by varying the size ofthe nanostructures, the band gap can be tuned to absorb ina particular photon energy range, thus providing good matchto the solar spectrum [28]. However, to achieve these ad-vantages for non-cryogenic temperatures, it is necessary tofabricate periodic arrays of individual nanostructures witha uniform size below 20 nm.

Using the template-based nanostructure fabrication tech-nique, we are currently developing the technology for solarcells which are expected to have high efficiency and eliminatethe material non-uniformity problem encountered in large PVstructures. This technology is also ideally suited for the for-mation of multijunction structures which will further increasethe photo-conversion efficiency [29]. The multijunction pho-tovoltaic cells can be formed by stacked layers of nanostruc-ture arrays, by using either (a) the same semiconductor ma-terial with varying dimensions, or, (b) fixed-size nanostruc-tures of different semiconductor materials. Figure 5a showsa photovoltaic cell with stacked arrays of nanostructure PNjunctions. The multijunction feature in this cell is achieved byusing band-gap tuning through nanostucture size control. Thediameter of the nanostructure PN junctions in each layer issmaller than that of those in the layer below it. The nanos-tructures with smaller dimensions will have larger energyband gaps and will be able to absorb light with shorter wave-lengths. This ability to absorb light over a wide wavelengthrange makes significant contributions towards increased cellefficiency. Figure 5b shows a PV cell that uses multiple layersof PN junctions of the same dimensions, but of different ma-terial systems. The band gap of material used in each layer ishigher than that of the layer below it, thus allowing this cell toabsorb light over a wide wavelength range.

The nanostructure-based PV cells shown in Fig. 5a,b areexpected to show very high conversion efficiency for the rea-sons described above. In addition, the structure of these cellsalso eliminates the large-area spatial nonuniformity that isassociated with most thin film technologies, since in thesecells spatial uniformity is required only over the diameter ofa nanostructure (a few nm). It may also be emphasized herethat since this electrochemical fabrication technology uses thesame techniques as the commercial anodization of aluminumfor corrosion resistance, this fabrication process can be scaledup to produce arrays of any arbitrary size.

Fig. 5a,b. Schematic cross sections of semiconductor nanostructure mul-tijunctionphotovoltaic cells with varyinga nanostructure size, andbnanostructure material composition

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Fig. 6. Diagram showing the process flow for fabricating semiconductor nanostructure-based multijunction photovoltaic cells

The outline of the fabrication technique for nanostructure-based solar cells is shown in Fig. 6. First, the bottom electrodefor the solar cell is deposited on the desired substrate. Next,a thin layer of aluminum is deposited by thermal evapora-tion on top of the bottom electrode. The thickness of thealuminum film is typically about 10 nm for quantum dots,and 100 nm− 1000 nm for quantum wires. The aluminumlayer is next anodized in sulfuric acid using the appropri-ate current density. The anodization process is monitored byobserving the voltage–time characteristics, and is performeduntil the pores reach all the way down to the bottom elec-trode, as signaled by the change in the voltage characteris-tics. At this point, the aluminum is converted into transparentAl2O3 with a periodic array of pores of the chosen dimen-sion. Next, the appropriate N-semiconductor material is de-posited inside the pores by electrochemical deposition froma suitable chemical bath. The thickness of the N-layer is con-trolled by controlling the deposition current which is stoppedwhen the desired thickness is reached. The N-semiconductorchemical is then slowly removed, and the P-semiconductorchemical is slowly introduced using the additional inlet tube.When the P-chemical reaches stability, the deposition currentis turned on and the P-semiconductor material is deposited.A slight over-deposition is performed to create the mushroompattern to facilitate improved top contacts. The transparenttop electrode is next deposited which completes the fabri-

cation of the single-junction cell. To create stacked layers,a second layer of aluminum is deposited on the top electrodeand the anodization and electro-deposition processes are re-peated. After the required number of stacked layers are fabri-cated, the system is then encapsulated for protection from theenvironment.

2.2 Sensors for monitoring fossil-fuel emissions

Monitoring of fossil-fuel emissions is important to minimizeenvironmental pollution, as well as to ensure efficient oper-ation of fossil-fuel plants. The most appropriate techniqueto measure emission gases is the optical in situ technique,where the radiation from a light source is passed throughthe combustion gas in the duct, and the light is absorbedby different gas species at their characteristic frequencies(Fig. 7a); the concentration of a particular gas species is de-termined from the amount of light absorbed at its charac-teristic frequency. Although several types of detectors areavailable for the optical detection technique, none of themhas the selectivity to distinguish between the different emis-sion gases. As a result, the existing commercial systems useholographic gratings and large photodiode arrays to providegas selectivity, which makes such systems extremely ex-pensive. A single detection system that can simultaneously

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Fig. 7. a Optical method for detecting combustiongas concentrations.b Top view of the multiple-species gas detector. Nanostructures of differ-ent dimensions are used to detect different gasspecies.c Cross-sectional view of the multiple-species gas detector. The nanostructure dimensiondetermines the particular light energy it will ab-sorb and the specific gas species it will be sensi-tive to

measure multiple gas species thus will be of great valueto the fossil-fuel community. We are currently using thetemplate-based nanostructure fabrication technique to de-velop an advanced UV sensor system for the in situ de-tection of multiple gas species, including NOx and SO2,that will be inexpensive, reliable, and accurate. In addition,the detector will have the ability for monolithic integra-tion with silicon signal-processing devices which will furtherimprove detector performance and reduce detector systemcost.

Semiconductor nanostrutcures are ideal for such selec-tive gas detection since they absorb light in an extremelynarrow spectral range [8]. In addition, by varying the sizeof the nanostructures, the band gap can be tuned to absorbin a particular photon-energy range, thus providing the se-lectivity needed for multiple gas detection. Figure 7b showsa top view of the multi-gas-species optical detector currentlyunder development. Nanostructures of different dimensionsare used to provide the specificity for different gas speciesto be detected. The energy gap of a nanostructure, and hencethe energy of light absorbed by it, is determined by its size.Hence, by controlling the size of a nanostructure, it can betuned to respond to only a specific gas species. The cross sec-tion of the detector for a fixed nanostucture size is shownin Fig. 7c. The semiconductor nanostructure is embedded ina layer of alumina and is contacted by two electrodes fromthe top and the bottom. The signal between the two contactswill provide the concentration of the particular gas speciesthe particular semiconductor nanostructures are sensitive to.Also, since the optical detectors are implemented on siliconsubstrates, it will open up the possibility for monolithic inte-gration with other silicon devices.

2.3 Nanostructure radiation detectors (10 keV−100 keV)

There is a need for detectors for ionizing radiation in the en-ergy range of 10 keV−100 keV for medical and space imag-ing. Radiation imaging in this energy range is primarily ac-complished by scintillation detectors. A scintillation detectorconsists of a scintillator which converts an incident high-energy photon into a number of low-energy visible photons.

These low-energy photons are then converted into an electri-cal signal by devices such as a photo-multiplier tube (PMT)or a semiconductor photodetector. Due to the previous lack ofa coherent theory of scintillation in solids, the past discoveryof new materials has been characterized as an ad hoc experi-mental approach which did not allow for the development ofan optimum material [30]. This state of affairs can be changedby applying the recent increased theoretical understanding ofthe scintillation process in semiconductors [30], with the abil-ity of nanotechnology to alter the structural, electrical, andoptical properties of semiconductors [8].

In the energy range of 10–100 keV, the primary absorp-tion process is the photoelectric effect with an increasingcontribution from Compton scattering at higher photon ener-gies for lower atomic number materials. In the photoelectriceffect, a high-energy photon interacts with a deep-shell elec-tron causing the photo-electrons to be ejected and createsa vacancy (hole) in that shell. The photo-electron then ac-quires a kinetic energy equal to the difference between theincident photon energy and the original binding energy ofthe photo-electron. The relaxation of the high-energy photo-electron and the deep-shell hole results in the creation ofa large number of secondary electron–hole pairs, and the re-combination of these thermalized electron–hole pairs resultsin the emission of visible light. Since the absorption andrelaxation processes occur on a time scale of ps, the per-formance of the scintillator is primarily determined by theelectron–hole pair recombination process [30]. Semiconduc-tor nanostructures have been shown to have very high carrierrecombination speed and efficiency due to quantum confine-ment, and is an ideal material system for the implementa-tion of high-performance scintillators. The improvements inscintillator performance expected from using semiconductornanostructures are briefly described below.

2.3.1 Scintillator efficiency. The scintillator efficiency is pri-marily determined by the efficiency of the electron–hole pairrecombination process. In semiconductor nanostructures, dueto increased overlap between the electron and hole wavefunc-tions, the oscillator strength shows a large increase [31]. Thisincreased oscillator strength results in an increased lumines-cent recombination efficiency.

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2.3.2 Response time. The energy of the incident high-energyradiation is determined by counting the number of visiblephotons emitted during the scintillation process. However,this requires that there be a temporal separation betweenthe luminescence of each incident high-energy photon. Themagnitude of this separation is determined by the responsetime of the scintillator – the time between the arrival ofthe incident high-energy photon, and the emission of thelast visible photon. If this time is large, and the lumines-cence of two incident photons overlap, the determination ofthe incident-photon energy will be inaccurate. Semiconduc-tor nanostructures show very fast response times, and are thusexpected to provide more accurate determination of the radi-ation energy.

2.3.3 Development. We are currently developing high-per-formance radiation detectors in the energy range of 10 keV−100 keV using the template-based semiconductor nanostruc-tures. We are performing theoretical as well as experimen-tal evaluations towards the design of an optimum scintillatorsystem. On the theoretical side, we are developing a de-tailed model of the scintillation response (emission wave-length, emission intensity, and response speed) of the nanos-tructure array as a function of incident-photon energy, tem-perature, and nanostructure characteristics (size and chem-ical composition). We are limiting the chemical compositionof the nanostructures to three basic II-V materials that havebeen previously demonstrated as scintillators: ZnS:Ag (Ag-doped ZnS), CdS:Te, and ZnSe:Te [30], and the ternary andquartenary alloys of these materials (for example ZnSSe orCdZnSSe). A main problem of using semiconductor nanos-tructures for scintillation is their low stopping power due tothe inherent small thickness of nanostructures, and the factthat only a percentage of the material is composed of thesemiconductor material where scintillation takes place. Pre-liminary calculations indicate that the thickness of scintillatormaterial needed to stop 1/e of the incident photon flux isapproximately 50µm, which can be implemented using 25stacked layers of nanostructures, each about 2µm thick. Fig-ure 8 shows a schematic cross section of the scintillator thatis currently under development. In the experimental side, weare currently evaluating photodetection systems for processcompatibility. We are using a micro-channel plate on whichthe nanostructure material is being fabricated. There are quitea few technical limitations still to overcome. At the comple-tion of the evaluation, the results will be compared with the

Fig. 8. A diagram of the multi-layer semiconductor nanostructure-basedscintillator as fabricated on a multi-channel plate. The drawing is not toscale

theoretical calculations which will be used to design the op-timum scintillator configuration.

2.4 Electro-optic flat panel displays

There is a great demand for flat panel displays (FPD) that takeup a small physical volume, provide high performance, andcan easily be manufactured to provide a low cost of owner-ship to the end user. Currently, the FPD market is dominatedby liquid crystal displays (LCD) and its variants which canprovide high resolution with small physical sizes. However,the complex manufacturing process for LCDs results in highcosts of displays, as well as limits the maximum physical sizeof the display area. We are currently investigating the use ofthe template-based semiconductor nanostructures to imple-ment flat panel displays that will reduce system cost as well aseliminate the size constraint associated with LCDs. The basicconcepts in these displays is to use the electro-optic effect ofsemiconductor nanostructures to provide the required contrastand eliminate the use of liquid crystals.

One of the most promising properties of semiconduc-tor nanostructures is the strong electro-optic effect observedin such materials. This means that the transmissivity ofthe material can be altered over several orders of magni-tude by the application of an external electric field. Thestrong electro-optic effect in semiconductor nanostructuresis due to quantum-confined Stark effect (QCSE), which isa well-known phenomenon observed in semiconductor low-dimensional structures, where excitonic effects dominateoptical properties [5]. In such systems, when an electric fieldis applied parallel to the direction of quantum confinement,a redshift is observed in the absorption spectra together withan increase in the absorption coefficient. Since QCSE is quan-tum mechanical in origin, the optical property modulationcaused by it is extremely fast, and a number of high-speedoptoelectronic devices have been proposed based on this ef-fect [5]. An important consequence of the QCSE is that anoptical beam with an energy near the exciton absorption peakcan be modulated by the application of an external electricfield. For efficient modulation, the size of the nanostructuremust be slightly larger than the bulk exciton Bohr radius, andthe band gap of the material must be approximately the sameas the incident photon energy.

The flat panel display that we are currently developinghas similar structure to an LCD display, except that semicon-ductor nanostructures are used to provide the optical contrast

Fig. 9. The top and cross-sectional views of the nanostructure electro-opticdisplay currently under development

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instead of liquid crystals. Two perpendicular indium tin oxide(ITO) electrode arrays, one on the top surface and one onthe bottom surface of the active electro-optic material willbe used for addressing the pixels, as schematically shown inFig. 9. The pixel will be addressed (and therefore transparent)when there is no potential difference between the top (con-trol) and bottom (scanning) electrodes. By scanning througheach bottom electrode, every pixel in the array can be individ-ually addressed. Since a pixel will be non-transparent unlessspecifically addressed, the scanning of the electrodes is notexpected to degrade image quality. It will also be possible totake advantage of the established active matrix LCD technol-ogy to improve display performance.

3 Summary and conclusions

We have presented a novel technology for the fabrication ofsemiconductor nanostructure arrays by electrochemical syn-thesis on an alumina template. The technology is inexpensive,reliable, suitable for the fabrication of a variety of semicon-ductors, and compatible with the standard CMOS process.We are currently using this fabrication technique to developa variety of different optoelectronic devices. The multijunc-tion solar cells currently under development are expectedto show high energy conversion efficiency due to enhancedabsorption and carrier collection efficiency of the nanostruc-tures. In addition, these solar cells will eliminate the spatialnon-uniformity problems that exist in most thin-film solarcells. We are also using the template-based nanostructurefabrication method to develop an advanced UV sensor sys-tem for in situ detection of fossil-fuel emissions. The de-tector, which will be inexpensive and sensitive to multiplegas species, will help reduce environmental pollution as wellas increase efficiency of fossil-fuel combustion plants. Thenanostructure-based radiation detectors currently under de-velopment will use the ultrafast response time and high re-combination efficiency of semiconductor nanostructures toincrease detector efficiency and speed. The detectors havepotential applications in medical field in reducing the radi-ation dose for imaging, and in high-resolution imaging ofspace. The template-based nanostructures are also investi-gated to implement low-cost flat panel displays. The displayswill use the large electro-optic effect observed in semicon-ductor nanostructures and will eliminate the size restrictionimposed by the current manufacturing limitations of liquidcrystal displays. In addition, due to the flexibility in thechoice of substrate for the template-based fabrication tech-nique, it will be possible to implement the displays on an ar-bitrary substrate, with the potential for mechanically flexibledisplays.

Acknowledgements. This project was partially supported by the NationalScience Foundation through grant no. 9521729 and by Federal EnergyTechnology Center through subcontract no. DE-AC26-99-FT40463, whichare gratefully acknowledged by the authors.

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