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“NoC Simulators”

Prepared by:Eng. Hossam Fadeel

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What is a Simulator?• Simulation:

– It is the discipline of designing a model of an actual or theoretical physical system, executing the model on a digital computer, and analyzing the execution output.

– The simulation allows researchers to explore the design space as well as to evaluate the performance and efficiency of novel microarchitecture features.

• Simulator:– It is a piece of software to model devices (or components) to predict outputs

and performance metrics on a given input. (Wikipedia)

• Simulators can be classified into many different categories:– Scope: micro-architecture vs. full-system simulators. – Detail: functional vs. timing (or performance) simulators. – Input (sometimes called Workload): trace-driven (or event-driven) vs. cycle accurate

simulators.

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Benefits of Simulators• Simulators are very useful for the following purposes:

– Evaluating different hardware designs without building costly physical hardware systems.

– Enabling the opportunities to access non-existing components or systems– Obtaining detailed performance metrics: A single execution of simulators can

often generate A large set of performance data.– Debugging: debugging on real hardware typically require re-booting and re-

running the code (or the design) to reproduce the problems. In contrast, some simulators have A fully controlled environment and allow software developers to run code backward once an error is detected.

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Cycle-accurate vs. Event-driven simulation

• Cycle-accurate simulation:– Simulates a microarchitecture on a cycle-by-cycle basis.

• Often used where time precisions are very important.– Incremented in fixed steps.

• After each increment we check to see which events happened at the current time point.– Cycle and bit accurate simulation is necessary when the actual router’s RTL description needs to

be evaluated and verified.

• Event-driven simulation: – Systems consisting of several tens or hundreds of modules, Cycle-accurate simulation leads to

excessive simulation times.– It is a modelling paradigm in which flow of control within the system is driven by events rather

than sequence.• events aren't guaranteed to occur at regular intervals.

– This approach uses a list of events that occur at various time, and handles them in order of increasing time.

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Why NoC Simulation?• Design decisions on NoC architectures are typically made on the basis of

simulation before resorting to emulation or implementation since it is cheap and flexible.

• To make a right decision on the network architecture, a simulation tool should enable:1. Faster exploration of the architectural design space;2. Assessment of design quality regarding performance, cost, power and reliability etc.;3. Extensive evaluation of various regular traffic patterns and application-oriented

traffic.

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Main characteristics of NoC• Topology: Arrangement of the Network Elements.• Switching: The way the data is transferred from the input port to the

output port.• Routing: Determine message path.• Flow Control: Determine allocation of the channels.• Buffering: The way the packets are stored when they cannot be

processed.• Arbitration: Plans the use of channels and buffers.

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Dealing with Simulators

Study of NoCs Characteristics and

Parameters

Study of NoCs Simulators Parameters and

Capabilities

Choose a NoC Simulator

Implementation

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NoC Evaluation methods• NoC Evaluation is an important step to classify the proposed architecture

among the others*. • To compare and contrast different NoC architectures, a standard set of

performance metrics can be used:– Latency – Throughput – Area– Power

* “A Survey of Network-On-Chip Tools” Ahmed Ben Achballah, et al. National Institute of Applied Sciences and Technology, Dept. of Electrical Engineering. Centre Urbain Nord, BP 676- 1080 Tunis Cedex, Tunisia.

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NoC Simulators ComparisonSimulator Framework Availability Parallelism Topologies Open Source Heterogeneous

SupportSynchronous

/ Asynchronous

SICOSYS C++ + - Limited + - Synchronous

Noxim SystemC + - Mesh + - Synchronous

BookSim C++ + - Many + - Synchronous

NNSE SystemC + - Mesh/Torus + - Synchronous

Nirgam SystemC + - All + - Synchronous

gpNoCsim Java + - All + - Both

Parm NoC OMNeT++ - + All - - Synchronous

HNOCS OMNeT++ + + All + + Both

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BookSim• cycle-accurate simulator.• Supports a wide range of topologies such as mesh, torus and flattened

butterfly networks• Provides diverse routing algorithms and includes numerous options for

customizing the network's router microarchitecture.• Most of the simulator's components are designed to be modular so tasks

such as adding a new routing algorithm, topology, or router microarchitecture should not require a complete redesign of the code.

• Implemented in C++.• the configuration file contains basic information about the topology,

routing algorithm, flow control, and traffic.• Packet size defaults to a single flit.

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BookSimConfiguration parameters

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NNSENostrum Network-on-Chip Simulation Environment

• Enables to analyze the performance impact of NoC configuration parameters– Configure a network with respect to topology, flow control and routing algorithm etc.;– Configure various regular and application specific traffic patterns;– Evaluate the network with the traffic patterns in terms of latency and throughput.

• The tool realizes only a limited set of configurations, which are as follows:– Topology: 2D mesh and 2D torus.– Flow control: Wormhole routing and deflection routing.

• For wormhole routing, one can choose virtual channel (VC) parameters like the number and depth of VCs. • For deflection routing (hot potato), one can specify a deflection policy.

Deflection routing is a routing strategy for networks based on packet switching which can reduce the need of buffering packets

Royal Institute of Technology 

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Network configuration tree Network evaluation flow

NNSENostrum Network-on-Chip Simulation Environment

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Wormsim Simulator• a cycle accurate simulator for Networks-on-Chip• It can be used to simulate a wide range of NoC architectures (e.g. NoCs with different topologies and

different routing algorithms, etc.), using user controllable performance parameters (e.g. channel buffer size, routing engine delay, crossbar arbitration delay, etc.).

• It has built-in traffic generator allow users to simulate the system under several popular traffic patterns, such as uniform traffic pattern, hot spot traffic pattern, transpose traffic pattern, etc.

• It provides an efficient way to allow user specify arbitrary traffic condition for the NoC under simulation.

– user has the control over the packet generating rate at individual IP node, the size of the packet and its distribution, etc.

• Worm_sim uses a simple command line interface to setup different parameters for systems under simulation.

• Worm_sim was developed and tested mainly in GNU/Linux.

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Noxim• It is developed using SystemC.• It has a command line interface for defining several parameters of a NoC.• The user can customize the network size, buffer size, packet size

distribution, routing algorithm, selection strategy, packet injection rate, traffic time distribution, traffic pattern, hot-spot traffic distribution.

• It allows NoC evaluation in terms of throughput, delay and power consumption. – This information is delivered to the user both in terms of average and per-

communication results.

• The user is allowed to collect different evaluation metrics including the total number of received packets/flits, global average throughput, max/min global delay, total energy consumption, per-communications delay/throughput/energy etc.

University of Catania (Italy)

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Heterogeneous NoCs (HNoCS)• HNOCS is an open-source implementation of a NoC simulation framework using

OMNeT++. • As an event driven simulation engine OMNeT++ provides C++ APIs to a reach set of

services that can be used to model, configure, describe the topology, collect simulation data and perform analysis.

• Support heterogeneous NoCs with variable link capacities and number of VCs per each unidirectional port.

• Supports parallelism and arbitrary topologies.

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SICOSYS• It is a general-purpose interconnection network simulator for multiprocessor systems

that allows the modeling a wide variety of message routers in a precise way.• Results are very close to those obtained by using hardware simulators but at lower

computational cost.• implementation is in C++ language.• The portability is very high and practically it can be executed in any UNIX platform

with a C++ standard compiler.

Universidad de Cantabria, Spain

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TOPAZ• TOPAZ is a general-purpose interconnection network simulator that allows

the modeling a wide variety of message routers with different tradeoffs between speed and precision.

• TOPAZ comes from SICOSYS simulator, which was originally conceived to obtain results are very close to those obtained by using HDL description of networks components by hardware simulators but at lower computational cost.

• implementation is in C++ language.• The simulator has support for parallel execution using standard POSIX

threads.• used in any UNIX platform with a C++ standard compiler.

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TOPAZCOMPONENTS SUPPLIED WITH TOPAZ

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NIRGAM*• It is a systemC based discrete event, cycle accurate simulator.• It provides substantial support to experiment with NoC design in terms of routing

algorithms and applications on various topologies.• Current Capabilities:

1. Topology: 2-D Mesh,2-D Torus2. Switching Mechanism: Wormhole3. Routing Algorithms: Deterministic XY, Adaptive Odd-Even(OE), and Source Routing4. Applications: Source (sender), Sink (reciever) and Traffic Generator: Constant Bit Rate, Bursty, and

Trace-based5. Plug-in support for applications and routers

• Configurable NoC parameters:– Topology size (m x n), Clock frequency, Buffer depth, Flit size, and Virtual channels

*NIRGAM is a collaborative research between Electronic Systems Design group, School of Electronics and Computer Science, University of Southampton UK and Department of Computer Science and Engineering, Malaviya National Institute of Technology, Jaipur India.

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NIRGAM• It generates gnuplot graphs and matlab script that can be run to generate graphs in

matlab.• It records the following performance metrics for each simulation:

– Average latency per packet (in clock cycles) for each channel– Average latency per flit (in clock cycles) for each channel– Average throughput (in Gbps) for each channel

• Adding New Router

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General Purpose Simulator forNetwork-on-Chip

• an open-source, component based network simulation environment that is developed entirely in Java.

• gpNoCsim provides the designers with the flexibility of incorporating different network and traffic configurations.

• Network configuration has been considered as the conglomeration of topologies, switching techniques, and routing algorithms.

• Reconfigurable topologies allow comparison between different architectures: Mesh, Torus, Butterfly Fat Tree.

Booksim Vs. TOPAZ

Booksim• Developed by Concurrent VLSI

Architecture group at Stanford University.

• Supports broad range of network architectures

• Cycle-accurate• implementation is in C++.• very simple to use.• Most of research use it for

evaluation.• Functionality continuously extended.• Very good Support by its designer.

TOPAZ• Actively in use by galerna

project from the University of Cantabria, Spain.

• The infrastructure inherited from SICOSYS.

• Cycle-accurate• obtain results are very close to HDL

description of networks components by hardware simulators at lower computational cost.

• Very well Documented.• Support 2-D and 3-D NoCs.

Booksim Vs. TOPAZ

Booksim TOPAZ• Most routers support to work with 3-

D NoCs.• Support multi-threaded to be

executed on multi-core systems.• Can be easily employed to extract

power and energy.• Integrates with General Execution-

driven Multiprocessor Simulator GEMS/GEM5.

http://networkonchip.wordpress.com

• Booksim Based reseach:– DART’s simulation results uses

Booksim as a reference.– Project “Floorplanning and

performance evaluation for on-die communication fabrics".

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Thank You