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NIRMA University of Science & Technology,

NIRMA University

Institute Of Technology, Ahmedabad

M.C.A. Semester I

3CA1152 Fundamentals of Computer Organization

LABORATORY MANUAL

INDEX

Sr. No.

Title

Page

Date

Sign

Grade

1

Study of AND,OR and NOT gates.

2

Study of NAND,NOR and EX-OR gates.

3

Simplify Any Expression and Make truth table for it and verify.

4

Using NAND gate Design AND,OR & NOT gate. Using NOR gate Design AND,OR & NOT gate.

5

Study of Decoder.

6

Study of Multiplexer.

7

Study of Half adder and Full adder.

8

Study of Half Subtractor and Full Subtractor.

9

Study of R-S , D Filp Flop

10

Study of JK , JK M/S and T-Flip Flop.

11 *

Study of Asynchronous Binary Counter

12 *

Study of synchronous Binary Counter

13 *

Study of BCD Counter

14 *

Study of Shift Register.

15 *

Study of Memory Organization

16 *

Study of Multiprocessor

17 *

Study of LogiSim Simulator.

(Logisim is an educational tool for designing and simulating digital logic circuits.)

*Indicates optional practicals

Roll No.:

Date:

Exp. No.:

Title : Study of AND, OR and NOT gates.

________________________________________________________________________

AIM : [1] To verify truth tables of basic gates.

EQUIPMENTS:

[1] Logic trainer

[2] IC 7400

[3] IC7402

[4] IC7408

[5] IC7432

[6] IC7486

[7] Connecting wires

THEORY:

A gate is a logic circuit that has one or more inputs and one or more outputs. The output of the gate will depend upon the set of input conditions. The digital signal has two distinct states LOW (0) and HIGH (1). Using gates we can implement variety of logic circuit that performs a particular task. For an example we can implement various arithmetic, logical and control units depending upon our requirements. Various types of gates are described below.

[1] NOT Gate: This gate has one input and one output. This gate inverts input at the output.

When input is LOW output is HIGH and vice versa.

BOOLEAN EXPRESSION:

Y = A'

TRUTH TABLE:

A

Y

0

1

1

0

[2] AND Gate: This gate has two or more inputs and one output. Output of AND gate will go HIGH when all inputs are HIGH , otherwise output will remain LOW.

BOOLEAN EXPRESSION:

Y = A * B

TRUTH TABLE :

A

B

Y

0

0

0

0

1

0

1

0

0

1

1

1

[3] OR Gate: This gate has two or more inputs and one output. Output of OR gate will go

HIGH when any of the input is HIGH, output is LOW when all inputs are LOW.

BOOLEAN EXPRESSION:

Y = A+ B

TRUTH TABLE:

A

B

Y

0

0

0

0

1

1

1

0

1

1

1

1

PROCEDURE:

[1] Select appropriate IC for each logic gate.

[2] Get the pin diagram from data book and make the connections according to the requirements.

[3] Make sure the connections of Vcc and ground are at their respective pins.

[4] Switch on the power and apply sequence of inputs and observe outputs.

CONCLUSION:

Roll No.:

Date:

Exp. No.:

Title : Study of NAND, NOR and XOR Gates.

________________________________________________________________________

(1) XOR Gate: This gate has two or more inputs and one output. Output will go HIGH when all inputs are not of the same logic level (i.e. all inputs are not LOW or not HIGH at a time).

BOOLEAN EXPRESSION:

Y = AB' + A'B = A + B

TRUTH TABLE:

A

B

Y

0

0

0

0

1

1

1

0

1

1

1

0

(2) NAND Gate: If we put one inverter at the output of AND logic gate will be NAND gate.

BOOLEAN EXPRESSION:

Y = ( A * B )'

TRUTH TABLE:

A

B

Y

0

0

1

0

1

1

1

0

1

1

1

0

(3) NOR Gate:If we put one inverter at the output of OR gate resulting logic gate will be NOR gate.

BOOLEAN EXPRESSION:

Y = ( A + B )'

TRUTH TABLE:

A

B

Y

0

0

1

0

1

0

1

0

0

1

1

0

PROCEDURE:

[5] Select appropriate IC for each logic gate.

[6] Get the pin diagram from data book and make the connections according to the requirements.

[7] Make sure the connections of Vcc and ground are at their respective pins.

[8] Switch on the power and apply sequence of inputs and observe outputs.

CONCLUSION:

Roll No.:

Date:

Exp. No.:

Title : Simplify any expression, make truth table for it and verify.

________________________________________________________________________

AIM : Design and realization of Binary to Gray code converter.

EQUIPMENTS:

[1] Logic trainer

[2] LEDs

[3] Digital IC 7486

[4] Connecting wires

THEORY :

Computers and other digital circuits are required to handle data, which may be numeral, alphabet or special character. Since digital circuit in binary fashion, the numerals, alphabets and other special characters are required to be converted into binary format. There are various possible ways of doing this, which is called encoding. Some commonly used binary codes are BCD, Excess-3, Gray, etc..

Many physical systems provide continuous data at their output. This data must be converted in to digital form before they are applied to a digital system. Continuous analog information is converted to digital form by means of analog to digital converter. Here it is useful to use the reflected (or gray) code to represent digital data converted from analog data. The advantage of reflected code over pure binary number is that the reflected code changes only by one bit as it proceeds from one number to the next.

PROCEDURE :

[1] Write down the code conversion table. Simplify Boolean function for each bit using K- map.

[2] Select appropriate ICs to realize the simplified Boolean function.

[3] Switch ON the power supply.

[4] Apply appropriate set of inputs and observe the output.

OBSERVATION :

DEC.

BINARY

GRAY

BINARY

NO.

B3

B2

B1

B0

G1

G0

G1

G0

B3

B2

B1

B0

0.

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

CONCLUSION:

Roll No.:

Date:

Exp. No.:

Title : Using NAND gate, design AND, OR NOT gates. Using NOR gate, design AND, OR, NOT gates.

________________________________________________________________________

Aim: Using NAND gate, design AND, OR NOT gates. Using NOR gate, design AND, OR, NOT gates.

1. NOT GATE

A gate is a logic circuit that has one or more inputs and one or more outputs. The output of the gate will depend upon the set of input conditions. The digital signal has two distinct states LOW (0) and HIGH (1). Using gates we can implement variety of logic circuit that performs a particular task. For an example we can implement various arithmetic, logical and control units depending upon our requirements. Various types of gates are described below.

[1] NOT Gate: This gate has one input and one output. This gate inverts input at the output. When input is LOW output is HIGH and vice versa.

BOOLEAN EXPRESSION:

Y = A'

A

Y

0

1

1

0

2. AND GATE

This gate has two or more inputs and one output. Output of AND gate will go HIGH when all inputs are HIGH , otherwise output will remain LOW.

BOOLEAN EXPRESSION:

Y = A * B

A

B

Y

0

0

0

0

1

0

1

0

0

1

1

1

3. OR GATE

This gate has two or more inputs and one output. Output of OR gate will go HIGH when any of the input is HIGH, output is LOW when all inputs are LOW.

BOOLEAN EXPRESSION:

Y = A+ B

A

B

Y

0

0

0

0

1

1

1

0

1

1

1

1

PROCEDURE:

1. Select appropriate IC for each logic gate.

2. Get the pin diagram from data book and make the connections according to the requirements.

3. Design the diagrams for the circuitry of connection as per NAND and NOR truth tables for getting AND, OR and NOT logic.

4. Make sure the connections of Vcc and ground are at their respective pins.

5. Switch on the power and apply sequence of inputs and observe outputs.

CONCLUSION:

Roll No.:

Date:

Exp. No.:

Title : Study of Decoder

________________________________________________________________________

Aim: Implementation of the Decoder.

EQUIPMENTS:

1. Logic trainer

2. Connecting wires

3. Required ICs

Discrete quantities of information are represented in digital systems with binary codes. A binary code of n bits is capable of representing up to 2n distinct elements of the coded information. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. If the n bit decoded information has unused or dont care combinations, the decoder will have less than 2n outputs.

The decoders are called n to m line decoders where m ( 2n. We design a 3 to 8 decoder here.

INPUT

OUTPUT

X

Y

Z

O0

O1

O2

O3

O4

O5

O6

O7

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

0

1

1

0

0

0

1

0

0

0

0

1

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

0

0

1

0

0

1

1

0

0

0

0

0

0

0

1

0

1

1

1

0

0

0

0

0

0

0

1

BOOLEAN EXPRESSION

O0 = XYZ

O1 = XYZ

O2 = XYZ

O3 = XYZ

O4 = XYZ

O5 = XYZ

O6 = XYZ

O7 = XYZ

PROCEDURE:

1. Select appropriate IC for each logic gate.

2. Get the pin diagram from data book and make the connections according to the requirements.

3. Make the connections as per the Boolean Expression listed above.

4. Make sure the connections of Vcc and ground are at their respective pins.

5. Switch on the power and apply sequence of inputs and observe outputs.

CONCLUSION:

Roll No.:

Date:

Exp. No.:

Title : Study of Multiplexer

________________________________________________________________________

Aim: Study of Multiplexer and realization of Boolean function using it.

EQUIPMENTS:

[1] Trainer Board

[2] IC 74151

[3] IC 7404

[4] Connecting wires

THEORY :

Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. Multiplexer is a combinational circuit that selects binary information from one of the many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally for 2n input lines whose bit combinations determine the input line to be selected.

PROCEDURE :

[1] First write down the Boolean function of interest in minterm form.

[2] Design it using multiplexer of appropriate size.

[3] Connect the circuit.

[4] Observe the output levels and note down the logic level in table.

OBSERVATION :

Y (A, B, C, D ) = ( (

)

MINTERMS

A

B

C

D

Y

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CONCLUSION:

Roll No.:

Date:

Exp. No.:

Title : Study of Half and Full Adder.

________________________________________________________________________

Aim: Study of Half and Full Adder.

EQUIPMENTS:

[1] Logic trainer

[2] IC 7408

[3] IC 7432

[4] IC 7486

[5] Connecting wires

THEORY:

Digital computers perform variety of information processing task. Among the basic functions encountered are the various types of arithmetic operations. Here we will see how these operations can be performed using digital hardware.

(1) Half Adder: This adder adds only two bits and carry from the previous stage will not be added. The output of the adder is SUM and CARRY. Truth table of half adder is given below.

TRUTH TABLE :

A

B

S

Co

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

Expression For Sum And Carry Out:

S = A'B + AB' = A + B and Co = AB

(2) Full adder: This adder adds two bits and carry from the previous stage. The outputs of the adder are SUM and CARRY. Truth table and simplified expression for sum and carry are given below.

TRUTH TABLE :

A

B

Ci

S

Co

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

EXPRESSION FOR SUM AND CARRY OUT :

S = A'B'Ci + A'BCi' + AB'Ci' + ABCi = A B C and Co = AB + BCi + ACi

PROCEDURE :

[1] From the Boolean expression draw the logic diagram using suitable gates.

[2] Select suitable ICs to implement the Boolean functions

[3] Connect circuit and switch on the power supply.

[4] Apply set of inputs and observe output and note down the logic state in table.

CONCLUSION:

Roll No.:

Date:

Exp. No.:

Title : Study of Half and Full Subtractor.

________________________________________________________________________

Aim: Study of Half and Full Subtractor.

EQUIPMENTS:

[6] Logic trainer

[7] IC 7408

[8] IC 7432

[9] IC 7486

[10] Connecting wires

THEORY:

Digital computers perform variety of information processing task. Among the basic functions encountered are the various types of arithmetic operations. Here we will see how these operations can be performed using digital hardware.

(1) Half subtractor: This subtractor subtracts one bit from another but ignores any borrow from the previous stage. The outputs of the half adder are DIFFERENCE and BORROW. Truth table and expression for difference and borrow are given below.

TRUTH TABLE:

A

B

D

Bo

0

0

0

0

0

1

1

1

1

0

1

0

1

1

0

0

EXPRESSION FOR DIFFERENCE AND BORROW OUT:

D = A'B + AB' = A + B and Bo = A'B

(2) Full subtractor: This subtractor subtracts binary digits along with borrow from the previous stage. The outputs of the subtractor are difference and borrow out.

TRUTH TABLE :

A

B

Bi

D

Bo

0

0

0

0

0

0

0

1

1

1

0

1

0

1

1

0

1

1

0

1

1

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

1

1

1

1

EXPRESSION FOR DIFFERENCE AND BORROW OUT :

D = A'B'Bi + A'BBi' + AB'Bi' + ABBi = A B C and Bo = A'B + A'Bi + BBi

PROCEDURE :

[5] From the Boolean expression draw the logic diagram using suitable gates.

[6] Select suitable ICs to implement the Boolean functions

[7] Connect circuit and switch on the power supply.

[8] Apply set of inputs and observe output and note down the logic state in table.

CONCLUSION:

Roll No.:

Date:

Exp. No.:

Title : Study of RS and D Flip Flop.

________________________________________________________________________

AIM : To verify characteristic tables of RS and D flip-flops.

EQUIPMENTS:

[1] Logic trainer Board

[2] IC 7400

[3] IC74112

[4] Connecting wires

THEORY :

Logic circuits are classified into two groups namely combinational and sequential. a combinational circuit consists of logic gates whose output at any time is determined directly from the present combination of inputs without regard to previous inputs. Sequential circuits involve timing and memory devices. The external inputs along with state of memory elements determine the binary value at the output terminals of the sequential circuit. Thus a sequential circuit is specified by a time sequence of inputs, outputs and internal states.

R-S FLIP-FLOP: It has two inputs R ( Reset ) & S ( Set ). The two outputs are Q & Q'. The two outputs are always complimentary. The truth table is as below.

S

R

Q ( t )

Q ( t + 1 )

0

0

0

0

0

0

1

1

0

1

0

0

0

1

1

0

1

0

0

1

1

0

1

1

1

1

0

*

1

1

1

*

Q( t ) = Present Output, Q( t + 1 ) = Next output, * = Invalid condition.

D FLIP-FLOP : D flip-flop transfers its input data to the output when clock will hit to the flip flop. This flip-flop is use to latch data and hold it till next clock comes. It is used in implementation of shift registers and counters. The truth table is as below.

D

Q ( t )

Q ( t + 1 )

0

0

0

0

1

0

1

0

1

1

1

1

PROCEDURE :

[1] Select appropriate IC for each logic gate.

[2] Get the pin diagram from the data book and do the connections accordingly.

[3] Switch on the power supply.

[4] Verify the truth table.

CONCLUSION:

Roll No.:

Date:

Exp. No.:

Title : Study of JK, JK M/S and T Flip Flop.

________________________________________________________________________

AIM : Study of JK, JK M/S and T Flip Flop.

EQUIPMENTS:

[5] Logic trainer Board

[6] IC 7400

[7] IC74112

[8] Connecting wires

THEORY :

Logic circuits are classified into two groups namely combinational and sequential. a combinational circuit consists of logic gates whose output at any time is determined directly from the present combination of inputs without regard to previous inputs. Sequential circuits involve timing and memory devices. The external inputs along with state of memory elements determine the binary value at the output terminals of the sequential circuit. Thus a sequential circuit is specified by a time sequence of inputs, outputs and internal states.

J-K FLIP- FLOP : J-K flip-flop is refinement of the R-S flip-flop in that the indeterminate state of R-S type is defined in the J-K flip-flop. Inputs J & K behave like S & R of R-S flip-flop. When inputs are applied to both J & K simultaneously, the flip flop switches to its complement state, i.e., if Q = 0 it switches to Q = 0, and vice versa. The truth table is as below.

J

K

Q ( t )

Q ( t + 1 )

0

0

0

0

0

0

1

1

0

1

0

0

0

1

1

0

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

0

T FLIP- FLOP : The T flip-flop is single input version of the J-K flip flop. The T flip-flop is obtained from J-K type if both the inputs are tied together. The designation T comes from the ability of the flip-flop to toggle the current state. Regardless of the present state of the flip-flop, it assumes the complement state when the clock pulse occurs while input T is at logic 1. The truth table is as below.

T

Q ( t )

Q ( t + 1 )

0

0

0

0

1

1

1

0

1

1

1

0

PROCEDURE :

[5] Select appropriate IC for each logic gate.

[6] Get the pin diagram from the data book and do the connections accordingly.

[7] Switch on the power supply.

[8] Verify the truth table.

CONCLUSION:

Roll No.:

Date:

Exp. No.:

Title : Study of Binary Counter and Shift Register.

________________________________________________________________________

AIM : Study of Binary Counter and Shift Register.

(a) Design and realize modulo 16 binary synchronous counter using J-K flip-flops.

EQUIPMENTS :

[1] Logic trainer Board

[2] IC74112

[3] IC7432

[4] IC7408

[5] IC7400

[6] Connecting wires

THEORY :

A sequential circuit that goes through a prescribed sequence of states on application of input pulses is called a counter. The input pulses may be count pulses, may be clock pulses or they may originate from an external source and may occur at prescribed intervals of time or at random. In a counter , the sequence of states may follow a binary count or any other sequence of states. Such counters are used for counting the number of occurrence of an event and are useful for generating timing sequence to control operations in a digital system.

The number of distinct states through which counter passes before it starts its count sequence again, is known as modulus of the counter. A counter that follows binary sequences called binary counter. An N-bit binary counter consists of N-flip flops and can count from 0 to (2n 1 ) Mainly digital counters are of two types:

SYNCHRONOUS COUNTER : In this same clock pulse is applied to all the flip-flops.

RIPPLE COUNTER : In this type of counter clock pulse is applied only to the first flip-flop and the ripples at the output of flip-flops serve as clock to the next flip-flops.

PROCEDURE :

[1] Select the desired value of N, i.e. modulo N-counter.

[2] Estimate minimum no. of JK flip-flops required to implement the counter.

[3] Draw the state diagram and state table.

[4] Derive input function expression for input of various flip-flops.

[5] Draw the logic diagram for the counter.

[6] Connect the circuit according to the logic diagram using various digital ICs.

[7] Switch on the power apply clock pulse, observe and note down the output sequence.

OBSERVATION : N = _______

COUNT

Q8

Q4

Q2

Q1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CONCLUSION:

(b) Study of Universal Shift Register

EQUIPMENTS:

[1] Logic trainer

[2] IC 74194

[3] Connecting wires

[4] CRO

THEORY :

A flip flop can store one bit of datum. It is also referred as a 1-bit register. An array of flip flop is required to store binary information and the number of flip flops required is equal to the number of bits in the binary word and is referred as a register. Registers find applications in a variety of digital systems including microprocessors.

A typical example of a shift register at work is found within a calculator. As we enter each digit on the keypad, the number shifts to the left on the display. In other words, each cell is a temporary memory and thus holds the number on the display even after the release of the key. It also shifts the number to the left each time a next key is pressed. This memory and shifting characteristic make the shift register extremely valuable in most digital electronic systems. We can classify the registers according to the way data they take from and the data they deliver to the external circuits.

[1] Serial in serial out registers (SISO) : Here data is taken serially one bit at a time and data is placed serially on the external line.

[2] Serial in parallel out registers (SIPO) : In this type of registers the data is accepted serially and data is placed simultaneously on the external bus.

[3] Parallel in serial out registers (PISO) : The data is loaded simultaneously and data is taken from the register one by one bit at time.

[4] Parallel in parallel out registers (PIPO) : The data is loaded simultaneously and is taken out simultaneously from the shift register.

Registers can be further classified according to the data shifting direction, they may be shift left registers or shift right registers.

UNIVERSAL SHIFT REGISTER (IC 74194) :

This bi-directional shift register is designed to incorporate virtually all of the features a system designer may want. It has four distinct modes of operation, namely (1) Parallel load, (2) Shift right, (3) Shift left, (4) Inhibit clock (do nothing).

MODE CONFIGURATION TABLE :

S1

S0

MODE

0

0

Inhibit Position

0

1

Shift Right

1

0

Shift Left

1

1

Parallel Load

PROCEDURE :

[1] Select appropriate for the shift register.

[2] Connect 0 & +5 volt D.C. supply to the IC.

[3] Select particular mode with proper logic level at S1 and S0.

[4] Apply clock pulse and sequence of input bits and observe the output sequence.

[5] Prepare the timing diagram and operation table for all possible modes.

CONCLUSION:

Roll No.:

Date:

Exp. No.:

Title : Study of BCD Counter.

________________________________________________________________________

AIM : Study of BCD Counter.

EQUIPMENTS:

[1] Logic trainer Board

[2] IC 74112

[3] IC7432

[4] IC7408

[5] IC7400

[6] Connecting wires

THEORY :

Ripple counter is also known as divide by N counter or asynchronous counter. In this counter same clock pulse is not applied to all flip-flops hence this counter is known as asynchronous counter. Since ripples at the output of one flip-flops trigger the next flip-flop, it is known as ripple counter. Every stage of this counter divides its input frequency by two in the output hence is known as divide by N counter.

PROCEDURE :

[1] Select the desired value of N, i.e. modulo N-counter.

[2] Estimate minimum no. of JK flip-flops required to implement the counter.

[3] Draw the state diagram and state table.

[4] Derive Boolean function expression for CLR input of various flip-flops.

[5] Draw the logic diagram for the counter.

[6] Connect the circuit according to the logic diagram using various digital ICs.

[7] Switch on the power apply clock pulse, observe and note down the output sequence.

OBSERVATION :

N = _________

COUNT

Q8

Q4

Q2

Q1

0

1

2

3

4

5

6

7

8

9

10

CONCLUSION:

25