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FreeScale Company Profile

Freescale is creating a smarter, better connected world. Already, there are more than 17 billion Freescale semiconductors at work all over the planet. You’ll find them embedded all around you: in automobiles, computer networks, communications infrastructure, office buildings, factories, industrial equipment, tools, mobile phones, home appliances and consumer products that touch every aspect of your daily life. We see a world where intelligence and connectivity are embedded everywhere. That’s the vision of more than 24,000 Freescale employees.

Freescale Semiconductor is a global leader in the design and manufacture of embedded semiconductors for the automotive, consumer, industrial, networking and wireless markets. The company is based in Austin, Texas, and has design, research and development, manufacturing or sales operations in more than 30 countries.

Freescale Semiconductor, Inc. is a global leader in the design and manufacture of embedded semiconductors for the automotive, consumer, industrial, networking and wireless markets. The privately-held company is based in Austin, Texas, and has design, research and development, manufacturing or sales operations in more than 30 countries. Freescale is one of the world's largest semiconductor companies with 2006 sales of $6.4 billion (USD).

Pervasive Innovation

Freescale may be one of the largest companies that people touch every day, but have never heard of. It has shipped more than 17 billion semiconductors, which can be found in everyday name brands:

Motorola cell phones Sony electronics Whirlpool appliances Logitech keyboards and mice Lifefitness cardiovascular and strength training equipment Cisco routers Bose Acoustic Wave radios Trane heating and cooling equipment Mercedes, BMW, Ford, Hyundai and General Motors vehicles

Freescale is a leader in many markets it serves:

No. 1 in automotive semiconductors — Gartner No. 1 in communications processors — Gartner No. 2 in overall microcontrollers — Gartner No. 2 in digital signal processors — Forward Concepts No. 4 in wireless handset radio frequency microprocessors — iSuppli

Freescale has design, research and development (R&D), manufacturing or sales operations in more than 30 countries. We have seven wholly-owned wafer fabs, two assembly and test sites and a 300-millimeter pilot line and R&D center in Crolles, France, jointly owned with STMicroelectronics and NXP, a newly independent semiconductor company (founded by Philips). Freescale invests $1 billion annually in R&D and has 5,500 patent families.

A New Life

After more than 50 years as part of Motorola, Freescale started a new life as a stand-alone company in July 2004. Since then, under the leadership of Chairman and CEO Michel Mayer, the company has focused on improving financial performance, reenergizing the culture and building a global brand.

with regards

saket123

FREESCALE PAPER ON 28th FEBRUARY

1. Y=A.C+B.C(bar) the gate implementation was given.How can this circuit is implemented by latch?

Ans:- Simple, this is simple 2:1MUX Where A,B are inputsAnd C is select pin or clock.

In Latch if clock is low its maintain output as its previous stage means no change.So if connect output Y to A. then this is implemented by latch.

2. Set up time, hold time se related 1 question.

3. Set up time, hold time was given and some delay in b/wMax freq.=1/(transition delay+setup time) No hold time.

4. NAND circuit was implemented by MOS……Response was asked?

5. Power dissipation=V^2*f*C(load cap)

6. Delay =(1/W by L ratio)*Vth*C(load)

7. Two buffer ckt were given what is the difference b/w them?

8. CMOS inverter main yadi PMOS and NMOS ko interchange ker de to bo buffer bun jata hai.

9. Three ckts of inverter was give in which they asked about power dissipation……with ON time was 40% while off time 60%.A. Simple CMOS inverter. B. Res was connected to VDD and PMOSC. NMOS Connected to VDD and res.So less on ckt was PMOS BECOZ ON TIME WAS 40% SO less power diss compare to C. While in A no res so very less power dissipation.

FREESCALE PAPER ON 17th AUGUST

hi i am rakesh jha one of the student of nit jal.freescale came in my institute and finally 2 are sellected

paper totally based on digital switching theory and mos operation n/w and elex.

q1.there are xor ckt and and give the wave of i/p with delay find out the delay.plz concentrate some delay in ms some in ns .

q2.thevenine ckt(n/W) find voc and Req.

q3.two question from clock skew.(concept of hold time ,setuup time and cq)

q4.find out the output impendence of ckt(gm1 and gm2 are in series with resistance r1 and r2.

q5.find the truth table of combination ckt of pmos and nmos.

q6.sequence dector of 1010101

q7.if clock is given i/p is is given in form of 1 0 10 then find waveform of o/p

i give one suggestion only study digital and concept of wave drawing.

in interview mainly ask mos concept.

FREESCALE Placement Paper on 7thAug2008

The paper was of 90 minutes and had 15 questions each of 10marks.

Q1- Design a black box with three ports A,B,C using 5 resistors of 1 ohm each such that RAB=1.5 ohm, RAC=3.5 ohm and RBC=3 ohm.

Q2-It was a basic thevenin circuit with three parallel branches containing a current source of 2A current, a resistor of 1 ohm and a battery source of 1V.We were asked to calculate the current in the resistor.

Q3-Design a mod-5 counter using JK flip flops with minimum circuitry?

A counter which is reset at the fifth clock pulse is called Mod 5 counter or Divide by 5 counter. The

circuit diagram of Mod 5 counter is shown in the figure. This counter contains three JKMS flip-flop.

Logic Diagram:

Truth table:

Clock Qc QB QA

Reset 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 0 0 0

6 0 0 1

A 3 bit binary counter is normally counting from 000 to 111. The actual output of a 3 bit binary

counter at the fifth clock pulse is 101.

A two input NAND gate is used to make a Mod 5 counter.

The outputs of the first and third flip flops (QA and QC) are connected to the input of the give

NAND gate, and its output is connected to the RESET terminal of the counter,

Hence the counter is reset at the fifth clock pulse, which produces the output QC,QB,QA as 000. It is

called divide by 5th counter or mod 5 counter.

Q4-Sythesize the function Y= (AB+CD)E using CMOS?

Q7-A problem of finding the max frequency with 3 different parts. Each having a different clock skew.

Q8-A problem to calculate the propagation delay in a combinational circuit.

Q9-A tricky problem on Zener diode with an RC circuit...Had to sketch the voltage waveform across the resistor……

Q10-Data is coming at a rate of 600mhz and is transmitted at 150mhz.Calculate the size of the FIFO required to avoid the overflow if 200 data bits are coming at a time and no data is received until the previous data is completely transmitted?

Q11-A microprocessor has an instruction pattern such that the first 3 instructions take 1 clock cycle each, the fourth one takes 2 and the fifth one takes 3 clock cycles. If 1 clock cycle=10ns. Find the MIPS (million instructions per second) of the microprocessor?

Q12-A problem on dynamic power dissipation based on the input & output waveforms of a sequential circuit.

Q13-Input & output waveforms for a circuit were given. Had to design the circuit to satisfy the conditions.

Q14-A very easy opamp based problem to calculate the transfer function of the circuit.

Q15-A unusual problem again on power dissipation. Given the power dissipated in each stage of the amplifier blocks..

SOLUTIONS Ans-1:From port A connect two 1 ohm resistors in parallel to point D(say). from point D connect a resistor to port B. And from D connect two restors in series to port C. Ans-2: i=1A Ans-3: Used 3 JK flip-flops with just one additional gate. Ans-4: Used 16 transistors. Ans-10: I got 150 bits. Ans-11: 63.5 MIPS

THIS IS MAY B USEFULL FOR THOSE R SERIOUSLY PREPARE FOR FREESCALE FIST INTRODUCTION OF COMPANY--IT IS BASICALLY MANUFATURE AND DESINING COMPANY OF SEMICONDUCTOR CHIP AND STARTED 1N YEAR NEARLY 1968 US BASED COMPANY....IT IS DIFFERENT FROM MOTOROLA ...BEFORE PPT I THOUGHT THAT IS A PART OF MOTOROLA......BUT EVERY GUISE THOUGHT IT IS MOLOROLA BUT NOT...MOTOROLA IS BIG COUSTOMER OF FREESCALE..OK IT HAVING 3 ROUND

1-TECH WRITTEN ROUND 2-TECH INTERVIEW

3-HR..

TECH WRITTEN------- DURATION 1.30 HR...AND 15 QUESTION EACH HAS 10 MARKS I THINK CUTUP WAS 50.MARKS... PURLY BADES ON DIGITAL ELECTRONICS SOME OF QUESTION I COLLECTED..

1) DESIGN OF MODE -5 COUNTER 2)SERIAL IN SERIAL OUT 1101....SHOW D CKT 3)ONE QUESTION BASED ON J K F/F 4)PROBLEM RELATED TO SETUP AND HOLD TIME 5)IMLEMENT (AB+CD)E WITH CMOS BASED ON NETWOR CKT

1) A BOX GIVEN ,,,IN BOX ONE INPUT A AND TWO OUTPUT B AND C....... WITH HTE USE OF SIX 1OHM RESISTER ,,,WE HVE TO SHOW THE EQIVALENT RESISTANCE BETWEEN A-B 1.2 OHM,,,,B-C-2 OHM,,,, A-C--2.2 OHM,,, 20 ONE QUESTION BASED ON TRANSIENT THEORM OF NETWORK... BASED ON COMMUNICATION BIT N=12,,1/TS=300K,,,FIND THE BANDWITH??? BASED ON ANALOG... OPEMP DB

GAIN PROBLEM TECNICAL INTERVIEW..... BASED ON WRITTEN...AND FOCUSED THE PART WHER U DIDN'T PERFORM WELL.... HR ROUND... THEY ALREADY DECEIDED ACCORDING TO TECH WRITTEN AND INTERVIEW .

1. the 2's complement number of 110010 isans; none of those

2.Truth table of a logic functionans: displays all its input output possibilities

3.The process of varying one signal according to the pattern provided by another signal isans:modulation

4.The octal equivalant of hexa number 123 isans:443

Determine how many times the given loop is executed

5.m=3 while (m<18) do {m=m+2;m=m-1}ans:15

6.m=1;a=30;while (m<>1) do {m=m+1;a=a-1;}

7.m=1;a=30;while (e*m-5<a) do {m=m+1;a=a-2}ans:9in questions 8 to 12 find the values of a and b at the end of the execution of the programsegment

8.a=2;b=1;x=1;while(x<=4)do {a=a+b;x=x+1}ans:(5,1)

9.a=1;b=2;x=1

while (x<=5)do {b=a+b;x=x+1;}ans:(1,6)

10.a=0;b=0;x=1;while (x<=4){a=a+x;b=b-x;x=x+1;}ans:(10,-10)

11.The complexity of bublle sort is0(a),then k equalsans:2

12.In BCD,the decimal number 516 isans:10101110

13. RS 232 is standards forans:physical layer

14. which of the following is not true of a DBMSans:maintain integrity

15.the method of access used for obtaining a record from a tape isans:sequential

16.Whichof the following is an universal gateans:nor

17.an ASCII text file containing 500 characters will have size approximatelyans:500bytes

18.which of the following is a vectorans;force

19.The lowest attainable temperatureans 0k

20.viscosity is most similar toans:friciton

21.The elapsed time between the submission of the job and getting the output isans:seek time

22.the earliest calculating device still in use isans: abacus

23.Qunatities used to bring fields to standards sixe areans:pixels

24.the base of a number system is called asans:radix

25.An 8kb computer will base addresses -----ans:8191

26.Arranging data in a specific form is calledans: sorting

27.A translator which reads an entire programme written in a high level language and convertsit into machine language code isans: interpreter

28.a data hierarchy in assending order isans:bit-byte -field-record-file-database

29.a computer generated output that lets programmer follow the executionof the program line by line is

30.data items grouped togother for storage form a

31. the most dangerous aspect of computer virusesis their ability toans: change system memory

32.a distributed data processing configuration in which all activities must pass through ancentrally located computer is called aans: ring network

33.communication circuite that transmit data inboth directions but not at the same timeare operating in

34.which of the following is not an application softwareans:unix

35.For which of the folowing computer application is real time processing not essential

36.a data structure with one to many relationship is aans:tree

37. which of the following hardware components is most important to operation of a databasemanagement systemans:high speed,large capacity disk

38. computer viruses can spread from one system to another by means ofans:all the above

39. afront end processor is ususally used inans: multi processing

40.a radioactive material of mass 16 grms in 10 years due to radiation. how many years will ittake for the material to attain a mass f1 gmans:30

41.a block of ice floats on water in a beaker, as the ice melts,the water level in the beaker willans:remain same

42.if va,vn,vs are velocities of sound in air,water, and steel then,ans:vs>vn>va

43.in usual computer arthemetic, the value of the integer expression22/5*2+8*2/6ans:10

44.an acronym for the organisation that publishes programming langauge standards isans:ANSI

1. Y=A.C+B.C(bar) the gate implementation was given.How can this circuit is implemented by latch?

Ans:- Simple, this is simple 2:1MUX Where A,B are inputsAnd C is select pin or clock.

In Latch if clock is low its maintain output as its previous stage means no change.So if connect output Y to A. then this is implemented by latch.

2. Set up time, hold time se related 1 question.

3. Set up time, hold time was given and some delay in b/wMax freq.=1/(transition delay+setup time) No hold time.

4. NAND circuit was implemented by MOS……Response was asked?

5. Power dissipation=V^2*f*C(load cap)

6. Delay =(1/W by L ratio)*Vth*C(load)

7. Two buffer ckt were given what is the difference b/w them?

8. CMOS inverter main yadi PMOS and NMOS ko interchange ker de to bo buffer bun jata hai.

9. Three ckts of inverter was give in which they asked about power dissipation……with ON time was 40% while off time 60%.A. Simple CMOS inverter. B. Res was connected to VDD and PMOSC. NMOS Connected to VDD and res.So less on ckt was PMOS BECOZ ON TIME WAS 40% SO less power diss compare to C. While in A no res so very less power dissipation.

Test Paper :3 Paper Type : Technical - Other Test Date : 7 August 2008 Posted By : Sruthi

FREESCALE PAPER ON 7TH AUGUST,2008






Q5-A general aptitude question with two parts each of 5marks. (a) Related to some matrix…(Could not answer that) (b) Was an easy probability based problem..

Q6-A problem on generating a C-code..Din’t attempt it.









Q15-A unusual problem again on power dissipation. Given the power dissipated in each

stage of the amplifier blocks..


FREESCALE PAPER ON 7TH AUGUST,2008


















1. Plz,Plz,Plz…..Clear the concepts of set up and hold time terms of digital electronics(3 to 4

questions on this topic alone). Most of the available books contain only their definition and

brief introduction but try to go to as much detail as you can.

2. One question on labeling the various ports of NMOS, PMOS or CMOS whose structure will be

given there.

3. 1 question on Sequential machine diagram.

4. Question on designing gates using NMOS or CMOS.

5. Question on input and output waveform of NMOS or CMOS circuit.

6. 1 or 2 questions may be asked sometimes from 8085 microprocessor.

7. Ring Counter Question

8. Question on sequence generator.

9. An opamp with input resistance will be given and you will have to find the output of that circuit.

So in the end you must be clear with the concept of digital electronics at least.

Interview:

In interview they will ask questions from digital electronics

1.what is set up time?

2.what is hold time?

3.Do latches have set up and hold time?

And questions from VLSI and semiconductors also.

HR interview will just be a formality if you clear technical round.


















Paper: FreeScalePlacement Paper 7th AUG 2008(Aptitude)

Q1- Design a black box with three ports A,B,C using 5 resistors of 1 ohm each such that

RAB=1.5 ohm, RAC=3.5 ohm and RBC=3 ohm.

Q2-It was a basic thevenin circuit with three parallel branches containing a current source of 2A

current, a resistor of 1 ohm and a battery source of 1V.We were asked to calculate the current in

the resistor.



Q5-A general aptitude question with two parts each of 5marks.

(a) Related to some matrixâ€¦(Could not answer that)

(b) Was an easy probability based problem..

Q6-A problem on generating a C-code..Dinâ€™t attempt it.

Q7-A problem of finding the max frequency with 3 different parts. Each having a different clock

skew.


Q9-A tricky problem on Zener diode with an RC circuit...Had to sketch the voltage waveform

across the resistorâ€¦â€¦

Q10-Data is coming at a rate of 600mhz and is transmitted at 150mhz.Calculate the size of the

FIFO required to avoid the overflow if 200 data bits are coming at a time and no data is received

until the previous data is completely transmitted?

Q11-A microprocessor has an instruction pattern such that the first 3 instructions take 1 clock

cycle each, the fourth one takes 2 and the fifth one takes 3 clock cycles. If 1 clock cycle=10ns.

Find the MIPS (million instructions per second) of the microprocessor?

Q12-A problem on dynamic power dissipation based on the input & output waveforms of a

sequential circuit.

Q13-Input & output waveforms for a circuit were given. Had to design the circuit to satisfy the

conditions.


Q15-A unusual problem again on power dissipation. Given the power dissipated in each stage of

the amplifier blocks..

Tell me about your Projects and give a general resume walk through.

First, I was called by the Team manager and was asked basic questions on Analog Blocks' functionality like ADC, DAC and LDO.

After that they called me for F2F interview in which they asked me basics of MOS operation, interviewer had

drawn some circuits like Level-Shifter and asked me to find what makes the circuitry cause leakage or not

working.Interview QuestionsProtocol of Low Power design

Correction in the circuit drawn.

How would you weight Boeing 747?

What is the difference between combinational and sequential logic?

Why does any chip/IC heat up?

Digital Design Questions like Set up and hold time calculation and Freq calculation , Async FIFO Design are asked from every interview person.System verilog Testbench structure are also asked and play vital role in hiring an employee

max freq of operation of a Digital ckt if set up and hold time are know to you.

Clock Domain crossing related questions

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