n5416a automated usb 2.0 pre-compliance test...

N5416A N5416A Automated USB 2.0Automated USB 2.0PrePre--Compliance Test SolutionsCompliance Test Solutions

Today’s Schedule

USB 2.0 Overview

USB 2.0 Compliance Testing

Examples of Compliance Tests


Demo of the Agilent Solution

Q&A

USB 2.0 Overview

Created by Compaq, Hewlett-Packard, Intel, Lucent, Microsoft,

The USB-IF(www.usb.org) governs the specification and use of USB, and resolves

USB Integrators’ Forum

Lucent, Microsoft, NEC and Philips

use of USB, and resolves any issues that arise

USB 2.0 Overview

USB Peripherals can be Host, Device or Hub The USB-IF combined all USB 1.1 and 2.0 speed

buses into the USB 2.0 specificationUSB 2.0 consists of 3 modes--

Data Rates

Data Rates Rise TimesLow-speed (LS) 1.5 Mb/s 75ns – 300nsFull-speed (FS) 12 Mb/s 4ns – 20ns

High-speed (HS) 480 Mb/s 500ps

USB 2.0 now offer Host/DeviceDual Role PeripheralsThis capability is referred as OTG

USB 2.0 Overview

Cables can be up to 5m long; hubs up to 5

Physical Characteristics

levels deep

Downstream data flows from PC to peripherals

Upstream data flows from peripherals to PC

USB Cable+ Shield

D+VBUS

D-Ground

Upstream data flows from peripherals to PC

USB 2.0 Overview

Signal Level TransferFull/Low Speed

3.3V, 12/1.5Mbps High Speed

400mV, 480Mbps

Signal Levels

400mV, 480Mbps

Required bandwidthBW = 0.35/Tr= ~1 GHz(Tr = ~400 ps)

Path Impedances

Characteristic measurements during mechanical test (High/Full speed cables

Characteristic ImpedanceDifferential 90 15%

USB 2.0 Overview

Differential 90 15%Common Mode 30 30%

Cable Attenuation 5.8dB @ 400MHz

Propagation Delay 26ns

D+/D- Propagation Skew 100ps

Full Speed and Low Speed modes are determined by the location of the Rpuresistor (on D+ or D-).

USB 2.0 OverviewTransmission Modes

The bus starts in full speed mode using the Rpu resistor

After Chirp Handshake, if high speed mode is available, the Rpuresistor is disconnected and bus changes to high speed mode.

Packet 1 Packet 2 Packet 3

USB 2.0 OverviewFull Speed Packet Makeup

frameSYNC SYNC SYNCPID(SOF) Frame No. CRC PID(IN) ENDP CRCADDR PID(NAK)EOP EOPEOP

Signal Amplitude400mV

SYNC:32(Minimum 12) bit

USB 2.0 OverviewHigh Speed Packet Makeup

SYNC PID(IN) ENDP CRCADDR EOP

32(Minimum 12) bit

Idle : SE0

EOP re-definition:NRZ 01111111 w/o bit stuffing(SOF EOP is 40 bit)

USB 2.0 Overview



Today’s Schedule



Conclusion

Q&A

Involves a set of test procedures (available from www.usb.org) performed in a specific order

The USB 2.0 HS test procedure


The USB 2.0 HS test procedure (v1.0) has been available since December 2001

The USB-IF performs the official compliance testing

Interoperability TestUSB 2.0 Compliance Testing

Electrical Tests

Full/Low speed signal quality

In-rush current

Droop/Drop

FS/LSHS


Droop/Drop

Backdrive voltage

High speed test

HS

OTG Specific Tests

Required Test Software

INTELHS Electrical Test Tool


In order to place your USB 2.0 Device in Test Modes you will need Intel HS Electrical Test Tool installed on a Windows based PC.Full Speed Tests requires Loop Descriptor ModeHigh Speed Test requires HS Test Packets Mode

Full/Low Speed Tests

Signal qualityIn-rush currentDroop/Drop

Backdrive voltage


Droop/Drop Backdrive voltage

Full/Low Speed Signal QualityUSB 2.0 Compliance Testing

USB Test Process1. Connect Probe to Test Fixture2. Connect device to Test Fixture3. Place Device in Loop Descriptor test Mode 3. Select Proper Test in N5416A Script4. Run Test

DEVICE Upstream

Host / System

Hub

Upstream

USBSystem

(PC)Oscilloscope

HUBHUB


AdjacentDevice

In FS tests, connect D+ of theadjacent device to scope ch 3

Devices

HUBHUB

HUB

HUB DUT

SQiDD5m cable

Connect D- to ch 1 Connect D+ to ch 2

Full/Low Downstream SetupUSB 2.0 Compliance Testing

Upstream Trigger Setup

The logic trigger occurs when the EOP is reached


EOP is reached and the Adjacent device is idle (Trigger Setup is done automatically)

Measurement Data

AutomatedMeasurement Setup & Result


Signal eye:*** eye failure! (14 data points violate eye) ****** waiver granted. ***

EOP width: 170.2029ns EOP width passes

Full Speed Test Results ExampleUSB 2.0 Compliance Testing

EOP width: 170.2029ns EOP width passes

Consecutive jitter range: -1703.52ps to 2268.87ps

RMS jitter 576.53ps

Paired KJ jitter range: -584.58ps to 0.00ps,

*** jitter failure ****** waiver granted ***

Understanding Full Speed Test ResultsMeasurement Items:

D+ greenD- bluecommon mode voltage purple


mode voltage purplecrossover location crossover location yellowyellow

diamonddiamondeye diagram ref.eye diagram ref. yellowyellow

circlecircleeye violation red dots

Types of Devices Tested

Bus powered devicesSelf-powered devices

Device Inrush Current TestUSB 2.0 Compliance Testing

GND

Vbus attach

>120µf <10µf

Bus or self-powered USB devices Protects upstream devices from damage

Device Inrush Current TestUSB 2.0 Compliance Testing

devices from damage 50.0 µC limit

Required TestsOverall result: fail!Inrush at 5.000V: 503C*** inrush failure! *** (at 5.000V, maximum compliant

inrush is 50C)

The HUB/Host Test: When a adjacent device is connected, the VBUS droop voltage must be within 330mV

HOST/HUB Droop/DropUSB 2.0 Compliance Testing

DEVICE Backdrive Voltage

Voltage measured on D+, D-, and VBUS upon power-up

After enumeration, USB plug is disconnected and voltage


Voltages must not exceed 0.4 V under any of these conditions

Both measured with 15 kΩΩΩΩresistor to ground

is disconnected and voltage is measured on D+, D-, and VBUS

Required Test EquipmentUSB 2.0 Compliance High Speed Testing

Scope BW >=2GHz

High Speed Signal QualityTime Domain Reflectometry( TDR )Reciever Sensitivity and SquelchJ and K Voltage

High Speed TestUSB 2.0 Compliance Testing

CHIRPPacket ParametersSuspend/Resume

HS Electrical Test Tools

The test mode can be any of the following:

Test JTest K


Test KTest _SE0_NAKTest PacketTest Force Enable

HS Signal Integrity

Test packet output by HS Electrical Test Tool

The signal is isolated


The signal is isolated from the host by the HS Test Fixture

Waveform is measured through a 90 ohm differential termination

9090ΩΩΩΩΩΩΩΩHS HS

RelayRelayHS HS

RelayRelayDeviceDevice

Differential ProbeDifferential Probe

Measuring High Speed Signal Quality

Test packet output


HS Signal Quality Test Results

Required TestsOverall result: pass! Signal eye:eye passesEOP width: 7.98 bits


EOP width: 7.98 bitsEOP width passesReceivers: reliable operation on tier 6receivers passMeasured signaling rate: 480.0641MHzsignal rate passes

Device HS Signal Quality USB 2.0 Compliance Testing

EL_2 Data rate specification (480 Mb/s0.05%)

EL_4 TP3 eye pattern requirement

EL_5 TP2 eye pattern requirement(device with captive cable)

(device with captive cable)

EL_6 10-90% differential rise/fall times(longer than 500ps)

EL_7 Monotonic data transitions for high speed drivers in the eye pattern template

HS Packet Parameters

The device is controlled by the Electrical Test Tool on the PC

The reply packet from the device


The reply packet from the deviceis received and evaluated for:

Sync EOP Spacing between packets

Sync Field : 32 bit EOP : 8 bit

HS Packet ParametersUSB 2.0 DEVICE Compliance Testing

CHIRP, SUSPEND/RESUME/RESET TimingUSB 2.0 DEVICE Compliance Testing

DeviceDevice

9090ΩΩΩΩΩΩΩΩ

USB Test FixtureUSB Test FixtureProbeProbe

ProbeProbe

CHIRP Test

Reset durationCHIRP K DurationHS termination

assertion Device’s Chip

USB 2.0 DEVICE Compliance Testing

assertion

CHIRP K(1ms <-> 7ms)

Device turns onHS termination

Device’s ChipLatency(2.5us <-> 3ms)

Chirp KJKJKJ(500us)

CHIRP TestUSB 2.0 DEVICE Compliance Testing

Device’s Chip Latency(2.5us <-> 3ms)

Enable High Speed Termination After Chirp KJKJKJ (within 500us)

Suspend TimingUSB 2.0 DEVICE Compliance Testing

Suspend : 3.000ms <-> 3.125msD+ Voltage > 2.7V

Resume TimingUSB 2.0 DEVICE Compliance Testing

Resume : < 2 bit time

Reset Timing

DeviceCHIRP K


Reset : 3.1ms <-> 6ms

Reset TimingUSB 2.0 DEVICE Compliance Testing

Reset from Suspend : 2.5us <-> 3.000ms

High Speed Receiver Sensitivity

Pulse GeneratorPulse Generator

Automated control


HS RelayHS RelayHS RelayHS Relay

DeviceDeviceDeviceDeviceSMASMA

In SE0_NAK test mode, pulse generator outputs IN token; device must not respond to tokens <100mV and must respond to tokens >150mV


Data generatorPacket

Device responsePacket



Note: A waiver may be granted if the receiver does not indicate squelch at


indicate squelch at +/-50mV of 150mV differential amplitude

Time Domain Reflectometry

TDRConfirm the signal is less than 10mV

Use TDR to measure impedance


HS RelayHS Relay

DEVICEDEVICESMA

measure impedance of connector, circuit board, and active termination

TDR Test Results

Differential impedance

Termination impedanceUSB Connector

80 ZHSTERM 100

70 ZHSTHRU 110


D+ odd impedanceD- odd impedance

Thruimpedance

USB 2.0 Overview



Today’s Schedule



Conclusion

Q&A

The effects of source and termination impedances

ZS Z0

A(w H(w) T(w)

Test Example 1: ImpedancesExamples of Compliance Tests

ZS Z0

ZLR2(w)H(w)R1(w)

Unregulated output impedance of a driver could cause significant overshoot or undershoot

Test Example 2: Full Speed

*** Overall result: fail! ***Signal eye:

*** eye failure! *** (33 data points violate eye)


USB OTG Compliance TestingGet Completely Automated Certification

of USB OTG PeripheralsN5416A Software provides Automated control of:N5417A USB OTG Test Fixture to sequence testsE3631A Power Supply34401A Voltmeter.

Equipment list for complete Automation:Agilent Oscilloscope with >=2GHz BWN5416A USB Compliance software2 High Impedance Passive Probes82357B USB->GPIB Adapter or equiv.Agilent E3631A Powersupply or equiv.Agilent 34401A Multimeter or equiv.GPIB Cable 10833B or equiv.

Test Example 2: A Detailed Look

Coupling between D+ and D-


Cautions with USB 2.0 Measurements

Hub quality can affect full/low speed upstreammeasurements For identical measurements to those in compliance tests, use Intel’s CHUB


For high speed signal quality measurements, take care in handling low level signals. Be careful of:

Adjusting the offset and performing calibrationEffects of fixturing impedance on signal qualityThe bandwidth of the probe

USB 2.0 Overview



Today’s Schedule



Conclusion

Q&A

Today’s Schedule

USB 2.0 Overview





Conclusion

Q&A

Summary

Compliance testing is a requirement

Compliance testing involves framework layer evaluation and physical layer evaluation

Conclusion

In physical layer evaluation, signal quality is influenced by components, circuit layout, and driver circuitry

An easy-to-use oscilloscope is an important factor in efficiently performing compliance testing

Reference Material

Universal Serial Bus Specification Rev 2.0 (USB-IF)

USB-IF Signal Integrity Test Description (USB-IF)

USB Design by Example

Conclusion

USB Design by Example (John Hyde, John Wiley & Sons INC)

Universal Serial Bus System Architecture(Don Anderson, MINDSHARE INC)

USB 2.0 High Speed Electrical Test Procedure v1.0

Recommanded USB 2.0 Test ConfigurationsDSO90254A Agilent 2.5GHz Oscilloscope (or DSO80204A/B or 54852A)N5416A USB 2.0 Compliance test Application

High Speed Tests:5 Self Powered High Speed USB Hubs + 5m USB CablesE2649B USB 2.0 HS Test Fixtures1130A 1.5GHz Differential Probe +E2678A Socket-in Probe Head81134A Pulse Pattern Generator (optional for Squelch Test)

OTG Tests:N5417A USB 2.0 OTG Automated Test Fixture82357A/B USB to GPIB Interface (Optional)34401A Voltmeter (Optional)

34401A Voltmeter (Optional)E3631A Power Supply (Optional)10833B GPIB Cable (Optional)

Low/Full Speed Tests:1 Self Powered FULL Speed USB Hub4 Self Powered High Speed USB Hubs + 5m USB CablesE2646A LS/FS USB Test Fixture3 High Impedance Passive Probes or 3 Single Ended Active Probes

USB Powered Devices/HUBInrush Current -> N2774A Current Probe +N2775A Probe PSU

Today’s Schedule

USB 2.0 Overview





Conclusion

Q&A

n5416a automated usb 2.0 pre-compliance test...

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