Multistage Opamp Presentation[1]

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<p>High Speed Op-amp Design: Compensation and Topologies for Two and Three Stage DesignsR. Jacob Baker and Vishal Saxena Department of Electrical and Computer Engineering Boise State University 1910 University Dr., MEC 108 Boise, ID 83725 jbaker@boisestate.edu and vishalsaxena@ieee.org</p> <p>Abstract : As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high gain by vertically stacking (i.e. cascoding) transistors becomes less useful in sub-100nm processes. Horizontal cascading (multistage) must be used in order to realize op-amps in low supply voltage processes. This seminar discusses new design techniques for the realization of multi-stage op-amps. Both single- and fully-differential op-amps are presented where low power, small VDD, and high speed are important. The proposed, and experimentally verified, opamps exhibit significant improvements in speed over the traditional op-amp designs while at the same time having smaller layout area.Baker/Saxena</p> <p>OutlineIntroduction Two-stage Op-amp Compensation Multi-stage Op-amp Design Multi-stage Fully-Differential Op-amps Conclusion</p> <p>Baker/Saxena</p> <p>Op-amps and CMOS ScalingThe Operational Amplifier (op-amp) is a fundamental building block in Mixed Signal design.Employed profusely in data converters, filters, sensors, drivers etc.</p> <p>Continued scaling in CMOS technology has been challenging the established paradigms for op-amp design. With downscaling in channel length (L)Transition frequency increases (more speed). Open-loop gain reduces (lower gains). Supply voltage is scaled down (lower headroom) [1].</p> <p>Baker/Saxena</p> <p>CMOS Scaling Trends</p> <p>VDD is scaling down but VTHN is almost constant.Design headroom is shrinking faster.</p> <p>Transistor open-loop gain is dropping (~10s in nano-CMOS)Results in lower op-amp open-loop gain. But we need gain!</p> <p>Random offsets due to device mismatches.[3], [4].Baker/Saxena</p> <p>Integration of Analog into Nano-CMOS?Design low-VDD op-amps.Replace vertical stacking (cascoding) by horizontal cascading of gain stages (see the next slide).</p> <p>Explore more effective op-amp compensation techniques. Offset tolerant designs. Also minimize power and layout area to keep up with the digital trend. Better power supply noise rejection (PSRR).</p> <p>Baker/Saxena</p> <p>Cascoding vs Cascading in Op-ampsA Telescopic Two-stage Op-amp A Cascade of low-VDD Amplifier Blocks.(Compensation not shown here)</p> <p>VDD</p> <p>VDD</p> <p>VDD</p> <p>VDD</p> <p>VDD</p> <p>VDD VDD</p> <p>2 1</p> <p>n-1</p> <p>vm</p> <p>vp</p> <p>n</p> <p>vout CL</p> <p>Vbiasn</p> <p>Vbiasn</p> <p>Vbiasn</p> <p>Stage 1</p> <p>Stage 2</p> <p>Stage (n-1)</p> <p>Stage n</p> <p>VDDmin&gt;4Vovn+Vovp+VTHP with wide-swing biasing. [1]</p> <p>VDDmin=2Vovn+Vovp+VTHP.</p> <p>Even if we employ wide-swing biasing for low-voltage designs, three- or higher stage op-amps will be indispensable in realizing large open-loop DC gain.Baker/Saxena</p> <p>TWO-STAGE OP-AMP COMPENSATION</p> <p>Baker/Saxena</p> <p>Direct (or Miller) CompensationCompensation capacitor (Cc) between the output of the gain stages causes pole-splitting and achieves dominant pole compensation. An RHP zero exists atCL30pF 100/2 100/2 M8B</p> <p>VDDM3</p> <p>VDD VDDM4 1 750 M7 220/2</p> <p>vm</p> <p>M1</p> <p>M2</p> <p>vpiC ff</p> <p>iC fb</p> <p>vout</p> <p>CC</p> <p>10pF 2</p> <p>M6TL M6BL</p> <p>Vbias3Vbias4M6TR M6BR M8T</p> <p>Due to feed-forward component of the compensation current (iC).</p> <p>The second pole is located at The unity-gain frequency is</p> <p>Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.</p> <p>x10</p> <p>All the op-amps presented have been designed in AMI C5N 0.5m CMOS process with scale=0.3 m and Lmin=2. The op-amps drive a 30pF off-chip load offered by the test-setup. Baker/Saxena</p> <p>Drawbacks of Direct (Miller) CompensationThe RHP zero decreases phase marginRequires large CC for compensation (10pF here for a 30pF load!).CL30pF 100/2 100/2 M8B</p> <p>VDDM3</p> <p>VDD VDDM4 1 M7 220/2</p> <p>vm</p> <p>M1</p> <p>M2</p> <p>vp</p> <p>CC10pF 2</p> <p>vout</p> <p>M6TL M6BL</p> <p>Vbias3M6TR M8T</p> <p>Slow-speed for a given load, CL. Poor PSRRSupply noise feeds to the output through CC.</p> <p>Vbias4M6BR</p> <p>Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.</p> <p>Large layout size.x10</p> <p>Baker/Saxena</p> <p>Indirect CompensationVDDM3</p> <p>VDDM4</p> <p>VDD VDDM9 1 M7 220/2</p> <p>The RHP zero can be eliminated by blocking the feed-forward compensation current component by usingvout CL30pF</p> <p>vm vp</p> <p>M1</p> <p>M2</p> <p>ic MCGA</p> <p>Cc</p> <p>2</p> <p>M6TL M6BL</p> <p>Vbias3M6TR M10T M10B M8T M8B</p> <p>100/2 100/2</p> <p>Vbias4M6BR</p> <p>A common gate stage, A voltage buffer, Common gate embedded in the cascode diff-amp, or A current mirror buffer.</p> <p>Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.</p> <p>x10</p> <p>An indirect-compensated op-amp using a common-gate stage.</p> <p>Now, the compensation current is fedback from the output to node-1 indirectly through a low-Z node-A. Since node-1 is not loaded by CC, this results in higher unity-gain frequency (fun).</p> <p>Baker/Saxena</p> <p>Indirect Compensation in a Cascoded Op-ampVDDM4T M3T M3B A M4B</p> <p>VDD</p> <p>ic</p> <p>VDDM7 110/2</p> <p>Vbias2</p> <p>1</p> <p>vm</p> <p>M1</p> <p>M2</p> <p>vp</p> <p>CC1.5pF</p> <p>vout2</p> <p>CC CL30pF</p> <p>voutCL</p> <p>vm</p> <p>vp</p> <p>M6TL M6BL</p> <p>Vbias3M6TR M8T M8B</p> <p>50/2 50/2</p> <p>Vbias4M6BR</p> <p>Unlabeled NMOS are 10/2. Unlabeled PMOS are 44/2.</p> <p>Indirect-compensation using cascoded current mirror load.</p> <p>Indirect-compensation using cascoded diff-pair.</p> <p>Employing the common gate device embedded in the cascode structure for indirect compensation avoids a separate buffer stage.Lower power consumption. Also voltage buffer reduces the swing which is avoided here.Baker/Saxena</p> <p>Analytical Modeling of Indirect Compensation</p> <p>The compensation current (iC) is indirectly fed-back to node-1.Block Diagram</p> <p>vout ic 1 sCc + Rc</p> <p>RC is the resistance attached to node-A.</p> <p>Small signal analytical model</p> <p>Baker/Saxena</p> <p>Derivation of the Small-Signal ModelResistance roc is assumed to be large.</p> <p>The small-signal model for a common gate indirect compensated opamp topology is approximated to the simplified model seen in the last slide.</p> <p>gmc&gt;&gt;roc-1, RA-1, CC&gt;&gt;CABaker/Saxena</p> <p>Analytical Results for Indirect Compensationj</p> <p> un</p> <p>p3</p> <p>p2</p> <p>z1Pole-zero plot</p> <p>p1LHP zero</p> <p>Pole p2 is much farther away from fun.Can use smaller gm2=&gt;less power!</p> <p>LHP zero improves phase margin. Much faster op-amp with lower power and smaller CC. Better slew rate as CC is smaller.</p> <p>Baker/Saxena</p> <p>Indirect Compensation Using Split-Length DevicesAs VDD scales down, cascoding is becoming tough. Then how to realize indirect compensation as we have no low-Z node available? Solution: Employ split-length devices to create a low-Z node.Creates a pseudo-cascode stack but its really a single device.</p> <p>In the NMOS case, the lower device is always in triode hence node-A is a low-Z node. Similarly for the PMOS, node-A is low-Z.</p> <p>NMOS</p> <p>PMOS</p> <p>Split-length 44/4(=22/2) PMOS layout</p> <p>Baker/Saxena</p> <p>Split-Length Current Mirror Load (SLCL) Op-ampVDDM3T A M3B M4B 1 M7T 220/2 M7B</p> <p>VDD VDDM4T</p> <p>ic220/2</p> <p>vm</p> <p>M1</p> <p>M2</p> <p>vp</p> <p>CC2pF</p> <p>vout2</p> <p>CL30pF</p> <p>M6TL M6BL</p> <p>Vbias3M6TR M8T M8B</p> <p>50/2 50/2</p> <p>Frequency Response</p> <p>Vbias4M6BR</p> <p>Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.</p> <p>ts</p> <p>The current mirror load devices are split-length to create low-Z node-A. Here, fun=20MHz, PM=75 and ts=60ns.Baker/Saxena</p> <p>Small step-input settling in follower configuration</p> <p>SLCL Op-amp Analysis1 gmp 1 gmp 1 gmpg m1 v gmp s</p> <p>gm1v s 2</p> <p>+</p> <p>-</p> <p>A</p> <p>A</p> <p>Cc1</p> <p>Cc</p> <p>id2 vs 2</p> <p>id1vs 2</p> <p>vout2</p> <p>1</p> <p>id1vs 2</p> <p>vout2</p> <p>CL</p> <p>CL</p> <p>v=0 (a)</p> <p>(b)</p> <p>1</p> <p>rop + </p> <p>A</p> <p>Cc</p> <p>2</p> <p>+gm1v s 2</p> <p>+ vsgA R1 C1 gmpvsgA1 gmp</p> <p>v1 1</p> <p>1 gmp</p> <p>CA gm2v1</p> <p>R2</p> <p>vout C2 -</p> <p>gm 1 v gmp s</p> <p>2</p> <p>+g m1v s</p> <p>Cc ic gm2v1 R21 gmp</p> <p>+ vout C2 -</p> <p>Here fz1=3.77funLHP zero appears at a higher frequency than fun.</p> <p>v1 R1 C1 ic vout 1 1 + sCc gmp</p> <p>Baker/Saxena</p> <p>Split-Length Diff-Pair (SLDP) Op-ampVDDM3 1</p> <p>VDD VDDM4 M7 110/2 M2T</p> <p>vm</p> <p>M1T 20/2 20/2 M1B A</p> <p>20/2</p> <p>vp</p> <p>ic2pF</p> <p>voutCC2</p> <p>20/2 M2B</p> <p>CL30pF</p> <p>M6TL M6BL</p> <p>Vbias3Vbias4M6TR M6BR M8T M8B</p> <p>50/2 50/2</p> <p>Frequency Response</p> <p>Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.</p> <p>The diff-pair devices are split-length to create low-Z node-A. Here, fun=35MHz, PM=62, ts=75ns. Better PSRR due to isolation of node-A from the supply rails.Baker/Saxena</p> <p>Small step-input settling in follower configuration</p> <p>SLDP Op-amp Analysisvout vs 21 gmn 1 gmnvs 2</p> <p>voutvs 2gmn v s 1 gmn 4</p> <p>id 2 = </p> <p>CcA</p> <p>ron + vgs1 gmnvgs1 vs 2</p> <p>1</p> <p>2</p> <p>+1 gmn</p> <p>+1 gmn</p> <p>vA CA -</p> <p>gmn v s 4</p> <p>R1</p> <p>C1</p> <p>gm2v1</p> <p>R2</p> <p>vout C2 -</p> <p>Here fz1=0.94fun,LHP zero appears slightly before fun and flattens the magnitude response. This may degrade the phase margin.</p> <p>1</p> <p>2</p> <p>+gmn v s 2</p> <p>Cc ic gm2v1vout</p> <p>+ vout C2 -</p> <p>v1 R1 C1 ic 1 1 + sCc gmn</p> <p>R2</p> <p>1 gmn</p> <p>Baker/Saxena</p> <p>Not as good as SLCL, but is of great utility in multi-stage op-amp design due to higher PSRR.</p> <p>Test Chip 1: Two-stage Op-amps</p> <p>Miller</p> <p>3-Stage Indirect</p> <p>SLCL Indirect</p> <p>SLDP Indirect</p> <p>Miller with Rz</p> <p>AMI C5N 0.5m CMOS, 1.5mmX1.5mm die size.Baker/Saxena</p> <p>Test Results and Performance ComparisonPerformance comparison of the op-amps for CL=30pF.</p> <p>Miller with Rz (ts=250ns)</p> <p>SLCL Indirect (ts=60ns)</p> <p>10X gain bandwidth (fun). 4X faster settling time. 55% smaller layout area. 40% less power consumption.</p> <p>SLDP Indirect (ts=75ns)Baker/Saxena</p> <p>MULTI-STAGE OP-AMP DESIGN</p> <p>Baker/Saxena</p> <p>Three-Stage Op-ampsHigher gain can be achieved by cascading three gain stages.~100dB in 0.5m CMOS</p> <p>Results in at least a third order system3 poles and two zeros. RHP zero(s) degrade the phase margin.</p> <p>j</p> <p>Hard to compensate and stabilize. Large power consumption compared to the two-stage op-amps.</p> <p> un</p> <p>Pole-zero plot</p> <p>Baker/Saxena</p> <p>Biasing of Multi-Stage Op-ampsDiff-amps should be employed in inner gain stages to properly bias second and third gain stagesCurrent in third stage is precisely set. Robust against large offsets. Boosts the CMRR of the opamp (needed).</p> <p>Robust Biasing</p> <p>Common source second stage should be avoided.Will work in feedback configuration but will have offsets in nano-CMOS processes.</p> <p>Fallible BiasingBaker/Saxena</p> <p>Conventional Three-Stage TopologiesNested Miller Compensation (NMC) [6]</p> <p>Requires p3=2p2=4un for stability (Butterworth response)Huge power consumption</p> <p>RHP zero appears before the LHP zero and degrades the phase margin. Second stage is non-invertingImplemented using a current mirror. Excess forward path delay (not modeled or discussed in the literature).</p> <p>Baker/Saxena</p> <p>Conventional Three-Stage Topologies contd.Nested Gm-C Compensation (NGCC) [7]</p> <p>Employs feed-forward gms to eliminate zeros.gmf1=gm1 and gmf2=gm2</p> <p>Class AB output stage. Hard to implement gmf1 which tracks gm1 for large signal swings.Also wasteful of power.</p> <p>gmf2 is a power device and will not always be equal to gm2.Compensation breaks down.</p> <p>Still consumes large power.</p> <p>Baker/Saxena</p> <p>Conventional Three-Stage Topologies contd.Transconductance with Capacitive Feedback Compensation (TCFC) [14]</p> <p>Four poles and double LHP zerosOne LHP zero z1 cancels the pole p3. Other LHP zero z2 enhances phase margin.</p> <p>VDDVB1</p> <p>VDD</p> <p>VDD</p> <p>VDDgm2/2 VB7</p> <p>VDD</p> <p>VDD</p> <p>1</p> <p>gmf CC1</p> <p>Set p2=2un for PM=60. Relatively low power. Still design criterions are complex. Complicated bias circuit.More power.vout</p> <p>vm gm1</p> <p>vp VB2 VB3 VB4 1:2 VB5 VB6 gmt2</p> <p>CC23</p> <p>Excess forward path delay.</p> <p>gm3</p> <p>Baker/Saxena</p> <p>Three-Stage Topologies: Latest in the literatureReverse Nested Miller with Voltage Buffer and Resistance (RNMC-VBR) [8]</p> <p>Employs reverse nesting of compensation capacitorsSince output is only loaded by only CC2, results in potentially higher fun. Third stage is always non-inverting.VDD VDD VDD VDD VDD VDD</p> <p>RC1 vm gm120uA</p> <p>Cc13</p> <p>vp</p> <p>vout CL</p> <p>Cc2 gmVB</p> <p>2</p> <p>gm3 gm2 gmf</p> <p>1</p> <p>Uses pole-zero cancellation to realize higher phase margins. Excess forward path delay. Biasing not robust against process variations. How do you control the current in the output buffer?</p> <p>Baker/Saxena</p> <p>Three-Stage Topologies: Latest in the literature contd.Active Feedback Frequency Compensation (AFFC) [9]High-Gain Block (HGB) Input Block vs -A1 +A21</p> <p>Cm vout3</p> <p>Reversed nested with elimination of RHP zero.High gain block (HGB) realizes gain by cascading stages. High speed block (HSB) implements compensation at high frequencies.</p> <p>2</p> <p>-A3</p> <p>-gmf Ca +gma High-Speed Block (HSB)</p> <p>Complex design criterions. Excess forward path delay. Again, uses a non-inverting gain stage. Employs a complicated bias circuit.More power consumption.</p> <p>Baker/Saxena</p> <p>Three-Stage Topologies: Latest in the literature contd.Various topologies have been recently reported by combining the earlier techniques.RNMC feed-forward with nulling resistor (RNMCFNR) [17]. Reverse active feedback frequency compensation (RAFFC) [17].</p> <p>Further improvements are required inEliminating excess forward path delay arising due to the compulsory noninverting stages. Robust biasing against random offsets in nano-CMOS. Further reduction in power and circuit complexity. Better PSRR.</p> <p>Baker/Saxena</p> <p>Indirect Compensation in Three-Stage Op-ampsIndirectly feedback the compensation currents ic1 and ic2.Reversed NestedThus named RNIC.</p> <p>Employ diff-amp stages for robust biasing and higher CMRR. Use SLDP for higher PSRR. Minimum forward path delay. No compulsion on the polarity of gain stages.Can realize any permutation of stage polarities by just changing the sign of the fed-back compensation current using fbr and fbl nodes.</p> <p>VDD</p> <p>VDD</p> <p>VDD</p> <p>VDD VDD</p> <p>-ve 1 ic1 fbl Cc1 ic2 Vbiasn</p> <p>2</p> <p>vm</p> <p>fbl</p> <p>+ve fbr</p> <p>vp</p> <p>vout3 fbr Cc2 CL</p> <p>Low-voltage design. Note Class A (well modify after theory is discussed).Baker/Saxena</p> <p>Indirect Compensation in Three-Stage Op-amps contd.VDD VDD VDD VDD VDD -ve 1 ic1 fbl Cc1 ic2 Vbiasn 2</p> <p>vm</p> <p>fbl</p> <p>+ve fbr</p> <p>vp</p> <p>vout3 fbr Cc2 CL</p> <p>Note the red arrows showing the node movements and the signs of the compensation currents.fbr and fbl are the low-Z nodes used for indirect compensation (have resistances Rc1 and Rc2 attached to them).</p> <p>The CCs are connected across two-nodes which move in opposite direction for overall negative feedback the compensation loops. Note feedback and forward delays!Baker/Saxena</p> <p>Analysis of the Indirect Compensated 3-Stage Op-ampPlug in the indirect compensation model developed for the two-stage opamps.i c1 v2 1 sCc1 + Rc 1</p> <p>ic 2 </p> <p>vout 1 sCc 2 + Rc 2</p> <p>Two LHP zerosBaker/Saxena</p> <p>Four non-dominant poles.</p> <p>Pole-zero CancellationPoles p4,5 are parasitic conjugated poles located far away in frequency.Appear due to the loading of the nodes fbr and fbl.</p> <p>The small signal transfer function can be written as</p> <p>The quadratic expression in the denominator describing the po...</p>