High Speed Op-amp Design: Compensation and Topologies for Two and Three Stage DesignsR. Jacob Baker and Vishal Saxena Department of Electrical and Computer Engineering Boise State University 1910 University Dr., MEC 108 Boise, ID 83725 jbaker@boisestate.edu and vishalsaxena@ieee.org

Abstract : As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high gain by vertically stacking (i.e. cascoding) transistors becomes less useful in sub-100nm processes. Horizontal cascading (multistage) must be used in order to realize op-amps in low supply voltage processes. This seminar discusses new design techniques for the realization of multi-stage op-amps. Both single- and fully-differential op-amps are presented where low power, small VDD, and high speed are important. The proposed, and experimentally verified, opamps exhibit significant improvements in speed over the traditional op-amp designs while at the same time having smaller layout area.Baker/Saxena

OutlineIntroduction Two-stage Op-amp Compensation Multi-stage Op-amp Design Multi-stage Fully-Differential Op-amps Conclusion

Baker/Saxena

Op-amps and CMOS ScalingThe Operational Amplifier (op-amp) is a fundamental building block in Mixed Signal design.Employed profusely in data converters, filters, sensors, drivers etc.

Continued scaling in CMOS technology has been challenging the established paradigms for op-amp design. With downscaling in channel length (L)Transition frequency increases (more speed). Open-loop gain reduces (lower gains). Supply voltage is scaled down (lower headroom) [1].

Baker/Saxena

CMOS Scaling Trends

VDD is scaling down but VTHN is almost constant.Design headroom is shrinking faster.

Transistor open-loop gain is dropping (~10s in nano-CMOS)Results in lower op-amp open-loop gain. But we need gain!

Random offsets due to device mismatches.[3], [4].Baker/Saxena

Integration of Analog into Nano-CMOS?Design low-VDD op-amps.Replace vertical stacking (cascoding) by horizontal cascading of gain stages (see the next slide).

Explore more effective op-amp compensation techniques. Offset tolerant designs. Also minimize power and layout area to keep up with the digital trend. Better power supply noise rejection (PSRR).

Baker/Saxena

Cascoding vs Cascading in Op-ampsA Telescopic Two-stage Op-amp A Cascade of low-VDD Amplifier Blocks.(Compensation not shown here)

VDD

VDD

VDD

VDD

VDD

VDD VDD

2 1

n-1

vm

vp

n

vout CL

Vbiasn

Vbiasn

Vbiasn

Stage 1

Stage 2

Stage (n-1)

Stage n

VDDmin>4Vovn+Vovp+VTHP with wide-swing biasing. [1]

VDDmin=2Vovn+Vovp+VTHP.

Even if we employ wide-swing biasing for low-voltage designs, three- or higher stage op-amps will be indispensable in realizing large open-loop DC gain.Baker/Saxena

TWO-STAGE OP-AMP COMPENSATION

Baker/Saxena

Direct (or Miller) CompensationCompensation capacitor (Cc) between the output of the gain stages causes pole-splitting and achieves dominant pole compensation. An RHP zero exists atCL30pF 100/2 100/2 M8B

VDDM3

VDD VDDM4 1 750 M7 220/2

vm

M1

M2

vpiC ff

iC fb

vout

CC

10pF 2

M6TL M6BL

Vbias3Vbias4M6TR M6BR M8T

Due to feed-forward component of the compensation current (iC).

The second pole is located at The unity-gain frequency is

Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

x10

All the op-amps presented have been designed in AMI C5N 0.5m CMOS process with scale=0.3 m and Lmin=2. The op-amps drive a 30pF off-chip load offered by the test-setup. Baker/Saxena

Drawbacks of Direct (Miller) CompensationThe RHP zero decreases phase marginRequires large CC for compensation (10pF here for a 30pF load!).CL30pF 100/2 100/2 M8B

VDDM3

VDD VDDM4 1 M7 220/2

vm

M1

M2

vp

CC10pF 2

vout

M6TL M6BL

Vbias3M6TR M8T

Slow-speed for a given load, CL. Poor PSRRSupply noise feeds to the output through CC.

Vbias4M6BR

Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

Large layout size.x10

Baker/Saxena

Indirect CompensationVDDM3

VDDM4

VDD VDDM9 1 M7 220/2

The RHP zero can be eliminated by blocking the feed-forward compensation current component by usingvout CL30pF

vm vp

M1

M2

ic MCGA

Cc

2

M6TL M6BL

Vbias3M6TR M10T M10B M8T M8B

100/2 100/2

Vbias4M6BR

A common gate stage, A voltage buffer, Common gate embedded in the cascode diff-amp, or A current mirror buffer.

Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

x10

An indirect-compensated op-amp using a common-gate stage.

Now, the compensation current is fedback from the output to node-1 indirectly through a low-Z node-A. Since node-1 is not loaded by CC, this results in higher unity-gain frequency (fun).

Baker/Saxena

Indirect Compensation in a Cascoded Op-ampVDDM4T M3T M3B A M4B

VDD

ic

VDDM7 110/2

Vbias2

1

vm

M1

M2

vp

CC1.5pF

vout2

CC CL30pF

voutCL

vm

vp

M6TL M6BL

Vbias3M6TR M8T M8B

50/2 50/2

Vbias4M6BR

Unlabeled NMOS are 10/2. Unlabeled PMOS are 44/2.

Indirect-compensation using cascoded current mirror load.

Indirect-compensation using cascoded diff-pair.

Employing the common gate device embedded in the cascode structure for indirect compensation avoids a separate buffer stage.Lower power consumption. Also voltage buffer reduces the swing which is avoided here.Baker/Saxena

Analytical Modeling of Indirect Compensation

The compensation current (iC) is indirectly fed-back to node-1.Block Diagram

vout ic 1 sCc + Rc

RC is the resistance attached to node-A.

Small signal analytical model

Baker/Saxena

Derivation of the Small-Signal ModelResistance roc is assumed to be large.

The small-signal model for a common gate indirect compensated opamp topology is approximated to the simplified model seen in the last slide.

gmc>>roc-1, RA-1, CC>>CABaker/Saxena

Analytical Results for Indirect Compensationj

un

p3

p2

z1Pole-zero plot

p1LHP zero

Pole p2 is much farther away from fun.Can use smaller gm2=>less power!

LHP zero improves phase margin. Much faster op-amp with lower power and smaller CC. Better slew rate as CC is smaller.

Baker/Saxena

Indirect Compensation Using Split-Length DevicesAs VDD scales down, cascoding is becoming tough. Then how to realize indirect compensation as we have no low-Z node available? Solution: Employ split-length devices to create a low-Z node.Creates a pseudo-cascode stack but its really a single device.

In the NMOS case, the lower device is always in triode hence node-A is a low-Z node. Similarly for the PMOS, node-A is low-Z.

NMOS

PMOS

Split-length 44/4(=22/2) PMOS layout

Baker/Saxena

Split-Length Current Mirror Load (SLCL) Op-ampVDDM3T A M3B M4B 1 M7T 220/2 M7B

VDD VDDM4T

ic220/2

vm

M1

M2

vp

CC2pF

vout2

CL30pF

M6TL M6BL

Vbias3M6TR M8T M8B

50/2 50/2

Frequency Response

Vbias4M6BR

Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

ts

The current mirror load devices are split-length to create low-Z node-A. Here, fun=20MHz, PM=75 and ts=60ns.Baker/Saxena

Small step-input settling in follower configuration

SLCL Op-amp Analysis1 gmp 1 gmp 1 gmpg m1 v gmp s

gm1v s 2

+

-

A

A

Cc1

Cc

id2 vs 2

id1vs 2

vout2

1

id1vs 2

vout2

CL

CL

v=0 (a)

(b)

1

rop +

A

Cc

2

+gm1v s 2

+ vsgA R1 C1 gmpvsgA1 gmp

v1 1

1 gmp

CA gm2v1

R2

vout C2 -

gm 1 v gmp s

2

+g m1v s

Cc ic gm2v1 R21 gmp

+ vout C2 -

Here fz1=3.77funLHP zero appears at a higher frequency than fun.

v1 R1 C1 ic vout 1 1 + sCc gmp

Baker/Saxena

Split-Length Diff-Pair (SLDP) Op-ampVDDM3 1

VDD VDDM4 M7 110/2 M2T

vm

M1T 20/2 20/2 M1B A

20/2

vp

ic2pF

voutCC2

20/2 M2B

CL30pF

M6TL M6BL

Vbias3Vbias4M6TR M6BR M8T M8B

50/2 50/2

Frequency Response

Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

The diff-pair devices are split-length to create low-Z node-A. Here, fun=35MHz, PM=62, ts=75ns. Better PSRR due to isolation of node-A from the supply rails.Baker/Saxena

Small step-input settling in follower configuration

SLDP Op-amp Analysisvout vs 21 gmn 1 gmnvs 2

voutvs 2gmn v s 1 gmn 4

id 2 =

CcA

ron + vgs1 gmnvgs1 vs 2

1

2

+1 gmn

+1 gmn

vA CA -

gmn v s 4

R1

C1

gm2v1

R2

vout C2 -

Here fz1=0.94fun,LHP zero appears slightly before fun and flattens the magnitude response. This may degrade the phase margin.

1

2

+gmn v s 2

Cc ic gm2v1vout

+ vout C2 -

v1 R1 C1 ic 1 1 + sCc gmn

R2

1 gmn

Baker/Saxena

Not as good as SLCL, but is of great utility in multi-stage op-amp design due to higher PSRR.

Test Chip 1: Two-stage Op-amps

Miller

3-Stage Indirect

SLCL Indirect

SLDP Indirect

Miller with Rz

AMI C5N 0.5m CMOS, 1.5mmX1.5mm die size.Baker/Saxena

Test Results and Performance ComparisonPerformance comparison of the op-amps for CL=30pF.

Miller with Rz (ts=250ns)

SLCL Indirect (ts=60ns)

10X gain bandwidth (fun). 4X faster settling time. 55% smaller layout area. 40% less power consumption.

SLDP Indirect (ts=75ns)Baker/Saxena

MULTI-STAGE OP-AMP DESIGN

Baker/Saxena

Three-Stage Op-ampsHigher gain can be achieved by cascading three gain stages.~100dB in 0.5m CMOS

Results in at least a third order system3 poles and two zeros. RHP zero(s) degrade the phase margin.

j

Hard to compensate and stabilize. Large power consumption compared to the two-stage op-amps.

un

Pole-zero plot

Baker/Saxena

Biasing of Multi-Stage Op-ampsDiff-amps should be employed in inner gain stages to properly bias second and third gain stagesCurrent in third stage is precisely set. Robust against large offsets. Boosts the CMRR of the opamp (needed).

Robust Biasing

Common source second stage should be avoided.Will work in feedback configuration but will have offsets in nano-CMOS processes.

Fallible BiasingBaker/Saxena

Conventional Three-Stage TopologiesNested Miller Compensation (NMC) [6]

Requires p3=2p2=4un for stability (Butterworth response)Huge power consumption

RHP zero appears before the LHP zero and degrades the phase margin. Second stage is non-invertingImplemented using a current mirror. Excess forward path delay (not modeled or discussed in the literature).

Baker/Saxena

Conventional Three-Stage Topologies contd.Nested Gm-C Compensation (NGCC) [7]

Employs feed-forward gms to eliminate zeros.gmf1=gm1 and gmf2=gm2

Class AB output stage. Hard to implement gmf1 which tracks gm1 for large signal swings.Also wasteful of power.

gmf2 is a power device and will not always be equal to gm2.Compensation breaks down.

Still consumes large power.

Baker/Saxena

Conventional Three-Stage Topologies contd.Transconductance with Capacitive Feedback Compensation (TCFC) [14]

Four poles and double LHP zerosOne LHP zero z1 cancels the pole p3. Other LHP zero z2 enhances phase margin.

VDDVB1

VDD

VDD

VDDgm2/2 VB7

VDD

VDD

1

gmf CC1

Set p2=2un for PM=60. Relatively low power. Still design criterions are complex. Complicated bias circuit.More power.vout

vm gm1

vp VB2 VB3 VB4 1:2 VB5 VB6 gmt2

CC23

Excess forward path delay.

gm3

Baker/Saxena

Three-Stage Topologies: Latest in the literatureReverse Nested Miller with Voltage Buffer and Resistance (RNMC-VBR) [8]

Employs reverse nesting of compensation capacitorsSince output is only loaded by only CC2, results in potentially higher fun. Third stage is always non-inverting.VDD VDD VDD VDD VDD VDD

RC1 vm gm120uA

Cc13

vp

vout CL

Cc2 gmVB

2

gm3 gm2 gmf

1

Uses pole-zero cancellation to realize higher phase margins. Excess forward path delay. Biasing not robust against process variations. How do you control the current in the output buffer?

Baker/Saxena

Three-Stage Topologies: Latest in the literature contd.Active Feedback Frequency Compensation (AFFC) [9]High-Gain Block (HGB) Input Block vs -A1 +A21

Cm vout3

Reversed nested with elimination of RHP zero.High gain block (HGB) realizes gain by cascading stages. High speed block (HSB) implements compensation at high frequencies.

2

-A3

-gmf Ca +gma High-Speed Block (HSB)

Complex design criterions. Excess forward path delay. Again, uses a non-inverting gain stage. Employs a complicated bias circuit.More power consumption.

Baker/Saxena

Three-Stage Topologies: Latest in the literature contd.Various topologies have been recently reported by combining the earlier techniques.RNMC feed-forward with nulling resistor (RNMCFNR) [17]. Reverse active feedback frequency compensation (RAFFC) [17].

Further improvements are required inEliminating excess forward path delay arising due to the compulsory noninverting stages. Robust biasing against random offsets in nano-CMOS. Further reduction in power and circuit complexity. Better PSRR.

Baker/Saxena

Indirect Compensation in Three-Stage Op-ampsIndirectly feedback the compensation currents ic1 and ic2.Reversed NestedThus named RNIC.

Employ diff-amp stages for robust biasing and higher CMRR. Use SLDP for higher PSRR. Minimum forward path delay. No compulsion on the polarity of gain stages.Can realize any permutation of stage polarities by just changing the sign of the fed-back compensation current using fbr and fbl nodes.

VDD

VDD

VDD

VDD VDD

-ve 1 ic1 fbl Cc1 ic2 Vbiasn

2

vm

fbl

+ve fbr

vp

vout3 fbr Cc2 CL

Low-voltage design. Note Class A (well modify after theory is discussed).Baker/Saxena

Indirect Compensation in Three-Stage Op-amps contd.VDD VDD VDD VDD VDD -ve 1 ic1 fbl Cc1 ic2 Vbiasn 2

vm

fbl

+ve fbr

vp

vout3 fbr Cc2 CL

Note the red arrows showing the node movements and the signs of the compensation currents.fbr and fbl are the low-Z nodes used for indirect compensation (have resistances Rc1 and Rc2 attached to them).

The CCs are connected across two-nodes which move in opposite direction for overall negative feedback the compensation loops. Note feedback and forward delays!Baker/Saxena

Analysis of the Indirect Compensated 3-Stage Op-ampPlug in the indirect compensation model developed for the two-stage opamps.i c1 v2 1 sCc1 + Rc 1

ic 2

vout 1 sCc 2 + Rc 2

Two LHP zerosBaker/Saxena

Four non-dominant poles.

Pole-zero CancellationPoles p4,5 are parasitic conjugated poles located far away in frequency.Appear due to the loading of the nodes fbr and fbl.

The small signal transfer function can be written as

The quadratic expression in the denominator describing the poles p2 and p3 can be canceled by the numerator which describes the LHP zeros.Results in LHP zeros z1 and z2 canceling the poles p2 and p3 resp.

The resulting expression looks like a single pole system for low frequencies. Phase margin close to 90.

Baker/Saxena

Pole-zero Cancellation contd.j

Place pole-zero doublets (p2-z1 and p3z2) out of fun for clean transients.i.e. fp2, fp3 > fun.

Best possible pole-zero arrangement for low power design. Results into design equations independent of parasitics (C3CL here). Rc1 and Rc2 are realized by adding poly Rs in series with CC1 and CC2.Also Rc1, Rc2Rc0, the impedance attached to the low-Z nodes fbr/fbl.

un

Design Equations

Robust against even 50% process variations in Rs and Cs as long as the pole-zero doublets stay out of fun.Baker/Saxena

Pole-zero cancelled Class-A Op-amp

A Here, the poly resistors are estimated as Low power, simple, robust and manufacturable topology*.The presented three-stage op-amps have been designed with transient and SR performances to be comparable to their two-stage counterparts.Baker/Saxena

Pole-zero cancelled Class-AB Op-amp 1

A dual-gain path, low-power Class-AB op-amp topology (RNIC-1). The design equation for Rc1 is modified as

Baker/Saxena

Pole-zero cancelled Class-AB Op-amp 2VDD M4 M5 VDD VDD M8 Vbiasp VDD M9 VDD M10 M2T 220/2 66/2 M5 fbl R1c 66/2 M6 Cc1 2 Vbiasn M3R M7L M7R Vpcas VncasMFCN MFCP

VDD

M1T

1 20/2 fbl 20/2 20/2 fbr 20/2

vmM1B

vpM2B

11/2

fbr

R2c

Cc2

vout3 100/2 CL 30pF

10/2

4.08K 2p M11

7.65K 1p

Vbiasn M3L

Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

A single-gain path, Class-AB op-amp topology for good THD performance.Floating current source for biasing the output buffer. Here, Vncas= 2VGS and Vpcas=VDD 2VSG. Note the lack of gratuitous forward delay.Baker/Saxena

Simulation of Three-stage Op-ampsBode Diagram 100 Magnitude (dB) Phase (deg) 50 0 -50 -100 -150 0 -45 -90 -135 -180 -225 102

10

4

10

6

10

8

10

10

Frequency (Hz)

Analytical model of the Class-AB (RNIC-1) topology is simulated in MATLAB. The pole-zero plot illustrates the double pole-zero cancelation (collocation).p4 and p5 are parasitic poles located at frequencies close to that of the fT limited (or mirror) poles.

Here, fun30MHz and PM=90 for CL=30pF.Baker/Saxena

Simulation of Three-stage Op-amps contd.

SPICE simulation of the same Class AB op-amp. CL=30pF: fun=30MHz, PM88, ts=70ns, 0.84mW, SR=20V/s. As fast as a two-stage op-amp with only 20% more power, at 50% VDD and with the same layout area (simpler bias circuit). Operates at VDD as low as 1.25V in a 5V process (25% of VDD). SPICE simulation match with the MATLAB simulationOur theory for three-stage indirect compensation is validated.Baker/Saxena

Chip 2: Low-VDD 3-Stage Op-amps

Best Performance AMI C5N 0.5m CMOS, 1.5mmX1.5mm die size.Baker/Saxena

Performance ComparisonFigures of MeritFoMS=funCL/Power FoML=SR.CL/Power IFoMS=funCL/IDD IFoML=SR.CL/IDD

RNIC op-amp designed for 500pF load for a fair comparison. FoMs>2X than state-ofthe-art at VDD=3V. Comparable performance even at lower VDD=2V. Practical, stable and production worthy.

Baker/Saxena

Performance Comparison contd.60000 50000 40000 30000 20000 10000 0C M C C FN R D FC FC AF F AC C B C F TC FC R DP N M ZC C VB F SM NR R FF N M C C F R NR R AF N IC RA F C R - 2 ( FF N IC Thi C L R N -3 s w P IC (T o R -2A hi s rk ) N IC (T wo -3 hi rk A sw ) (T hi ork s ) w or k) M N N G M C

FOM_S FOM_L IFOM_S IFOM_L

Higher performance figures than state-of-the-art. 10X faster settling. Better phase margins. Layout area same or smaller.

Baker/Saxena

N

Flowchart for RNIC Op-amp DesignStart with the initial specifications on fun, CL, Av, and SR. Split DC gain AOLDC across A1, A2 and A3.

Select the overdrive (% of VDD) which will set VGS, fT and transistor gain gm*ro.

Identify gm1. Can initially set gm2 equal to gm1 or a to lower value.

Select Cc2 = gm1/fun

Select Cc1 and gm3 such that the p2-z1 and p3-z2 doublet locations are outside fun.

Calculate R1c and R2c. Yes

Move the corresponding pi-zj doublet to a lower frequency by changing Cci and Rci. May have to sacrifice fun.

Is either of R1c and R2c negative?

Are the parasitic poles p4,5 degrading PM by closing on fun?

Yes

Increase gm2.

No Simulate the design for frequency response and transient settling. No

No More Speed? No Increase gm1 or decrease Cc2.

Yes

Does the design meet the specifications?

Lower power? No Smaller layout area? No

Yes

Decrease gm3 or gm2. In the worst case scenario decrease gm1.

Yes End

Yes

Reduce Cc1, Cc2 or gm3.

Nothing works! Revisit biasing.

No

Better SR?

Yes

Increase bias current in the first stage (i.e. ISS1) or use smaller CCs

Baker/Saxena

N-Stage Indirect Compensation TheoryThe three-stage indirect compensation theory has been extended to Nstages and the closed form small signal transfer function is obtained.Cc CcCc2

n1

n2

ic

Cc icn2

n1

1

ic

2

ic

1

Baker/Saxena

MULTI-STAGE FULLY-DIFFERENTIAL OP-AMPS

Baker/Saxena

Fully Differential Op-ampsAnalog signal processing uses only fully differential (FD) circuits.Cancels switch non-linearities and even order harmonics. Double the dynamic range.

Needs additional circuitry to maintain the output common-mode level.Common-mode feedback circuit (CMFB) is employed. vop-vom=-A(vinp-vinm)

Baker/Saxena

Three-Stage FD Op-amp Design: ProblemsBlock DiagramVDD VDD

Circuit ImplementationVDD VDD VDD VDD VDD

vom120/2 VCM fbl 20/2 20/2 20/2

vop120/2 fbr 20/2

vom2 Cc1 R1c vp vop1

fbr Vbiasp

fbl

R1c Cc1

vop2 vom1

vm

Vbiasn

VCMFB1

Vbiasn

VDD

First Stage

VDD

Second Stage

vom2110/2 VDD fbl

vop2VDD R2c Cc2 fbr 110/2

vop30K 100f

vom Cc2 R2c50/2

vop50/2

VCM 30K 100f

VCMFB1

100/2

VCM

100/2

vom100/2 Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

100/2

VCMFB3 Output Buffer (Third Stage)

The CMFB loop disturbs the DC biasing of the intermediate gain stages.Degrades the gain, performance and may cause instability.Baker/Saxena

Three-Stage FD Op-amp Design: SolutionsEmploy CMFB1. Individually across all the stages. 2. Only across the last two stages as the biasing of the output buffer need not be precise. 3. Only in the third stage (output buffer). 1.+

Cc2 Cc11p 2p 3p

vp

-A1

-

+A2

-A3

vop

vbiasp

vbiasn

vCM

vm

-A1+

-

1m

+A2

2m

-A3

3m

vom

Cc1 Cc2

2.vp+

Cc2 Cc11p 2p 3p

3.-A3 vop vp+

Cc2 Cc11p 2p 3p

-A1

-

+A2vCMFB

-A1

-

+A2

-A3vCMFB

vop

vCM -A3 -A1+

vCM

vm

-A1+

-

1m

+A2

2m

3m

vom

vm

-

1m

+A2

2m

-A3

3m

vom

Cc1 Cc2

Cc1 Cc2

Baker/Saxena

Three-Stage FD Op-amp DesignBlock DiagramVDD VDD

Circuit ImplementationSecond Gain Stage VDD VDD VDD VDD VDD

vom2 Cc1 R1c

vom1fbl 20/2 VCM fbl 20/2

vop1fbr 20/2 fbr 20/2

R1c Cc1

vop2

vm

20/2 20/2

vp

Vbiasn

Vbiasn

Vbiasn

First Gain Stage VDD VDD Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

vom2110/2 VDD Cc2 R2c fbr

vop2VDD R2c Cc2 fbl 110/2

vom50/2

vop50/2 30K

vop100f

30K

100/2

VCMFB3 Output Buffer (Third Stage)

100/2

vom

Use CMFB only in the output (third) stage. Manufacturable design.Leaves the biasing of second and third stage alone without disturbing them.

Employ diff-amp pairs in the second stage for robust biasing.Baker/Saxena

100f

100/2

VCM

100/2

VCM

VCMFB3

Three-Stage FD Op-amp: Enlarged

30K

Baker/Saxena

30K

100f

100f

Chip 3: Low-VDD FD Op-amps

Best Performance

AMI C5N 0.5m CMOS, 1.5mmX1.5mm die size.Baker/Saxena

Simulation and Performance ComparisonDC behavior Transient response

82dB gain

ts=275ns

>2.5X figure of merit (FoM).Baker/Saxena

Flowchart for Three-Stage FD Op-amp DesignStart with the initial specifications on fun, CL, Av, and SR. Design a singly-ended pole-zero cancelled three-stage op-amp for the given specifications.

Convert the singly-ended op-amp into a fully differential one by mirroring it. Use a pair of diff-pairs for the second stage for robust biasing.

Add a CMFB circuit in the output buffer.

NoUpdate the value of gm3 corresponding to the output buffer and recalculate R1C and R2C.

Simulate the design.

Does the design meet specifications?

Yes End

Baker/Saxena

ConclusionsIndirect compensation leads to significantly faster, lower power op-amps with smaller layout area. Indirect compensation using split-length devices facilitates low-VDD opamp design. Novel pole-zero canceled three-stage RNIC op-amps exhibit substantial improvement over the state-of-the-art. A theory for multi-stage op-amps is presented. New methodologies for designing multi-stage FD op-amps proposed which improve the state-of-the-art. All proposed op-amps are low voltageOpen new avenues for low-VDD mixed signal system design.

Baker/Saxena

Future ScopeMathematical optimization of PZC op-amps. Design of low-VDD systems in nano-CMOS processPipelined and Delta-Sigma data converters, Analog filters, Audio drivers, etc.

Further investigation into indirect-compensated op-amps for n4 stages.

Baker/Saxena

References[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Baker, R.J., CMOS: Circuit Design, Layout, and Simulation, 2nd Ed., Wiley Interscience, 2005. Saxena, V., Indirect Compensation Techniques for Multi-Stage Operational Amplifiers, M.S. Thesis, ECE Dept., Boise State University, Oct 2007. The International Technology Roadmap for Semiconductors (ITRS), 2006 [Online]. Available: http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm Zhao, W., Cao, Yu, "New Generation of Predictive Technology Model for sub-45nm Design Exploration" [Online]. Available: http://www.eas.asu.edu/~ptm/ Slide courtesy: bwrc.eecs.berkeley.edu/People/Faculty/jan/presentations/ASPDACJanuary05.pdf Leung, K.N., Mok, P.K.T., "Analysis of Multistage Amplifier-Frequency Compensation," IEEE Transactions on Circuits and Systems I, Fundamental Theory and Applications, vol. 48, no. 9, Sep 2001. You, F., Embabi, S.H.K., Sanchez-Sinencio, E., "Multistage Amplifier Topologies with Nested Gm-C Compensation," IEEE Journal of Solid State Circuits, vol.32, no.12, Dec 1997. Grasso, A.D., Marano, D., Palumbo, G., Pennisi, S., "Improved Reversed Nested Miller Frequency Compensation Technique with Voltage Buffer and Resistor," IEEE Transactions on Circuits and Systems-II, Express Briefs, vol.54, no.5, May 2007. Lee, H., Mok, P.K.T., "Advances in Active-Feedback Frequency Compensation With Power Optimization and Transient Improvement," IEEE Transactions on Circuits and Systems I, Fundamental Theory and Applications, vol.51, no.9, Sep 2004. Eschauzier, R.G.H., Huijsing, J.H., "A 100-MHz 100-dB operational amplifier with multipath Nested Miller compensation," IEEE Journal of Solid State Circuits, vol. 27, no. 12, pp. 1709-1716, Dec. 1992. Leung, K. N., Mok, P. K. T., "Nested Miller compensation in low-power CMOS design," IEEE Transaction on Circuits and Systems II, Analog and Digital Signal Processing, vol. 48, no. 4, pp. 388-394, Apr. 2001. Leung, K. N., Mok, P. K. T., Ki, W. H., Sin, J. K. O., "Three-stage large capacitive load amplifier with damping factor control frequency compensation," IEEE Journal of Solid State Circuits, vol. 35, no. 2, pp. 221-230, Feb. 2000.

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References contd.[13] [14] [15] [16] [17] [18] Peng, X., Sansen, W., "AC boosting compensation scheme for low-power multistage amplifiers," IEEE Journal of Solid State Circuits, vol. 39, no. 11, pp. 2074-2077, Nov. 2004. Peng, X., Sansen, W., "Transconductances with capacitances feedback compensation for multistage amplifiers," IEEE Journal of Solid State Circuits, vol. 40, no. 7, pp. 1515-1520, July 2005. Ho, K.-P.,Chan, C.-F., Choy, C.-S., Pun, K.-P., "Reverse nested Miller Compensation with voltage buffer and nulling resistor," IEEE Journal of Solid State Circuits, vol. 38, no. 7, pp. 1735-1738, Oct 2003. Fan, X., Mishra, C., Sanchez-Sinencio, "Single Miller capacitor frequency compensation technique for low-power multistage amplifiers," IEEE Journal of Solid State Circuits, vol. 40, no. 3, pp. 584-592, March 2005. Grasso, A.D., Palumbo, G., Pennisi, S., "Advances in Reversed Nested Miller Compensation," IEEE Transactions on Circuits and Systems-I, Regular Papers, vol.54, no.7, July 2007. Shen, Meng-Hung et al., "A 1.2V Fully Differential Amplifier with Buffered Reverse Nested Miller and Feedforward Compensation," IEEE Asian Solid-State Circuits Conference, 2006, p 171-174.

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