Slide 1

IMPLEMENATTION OF MULTI CHANNELUART CONTROLLER BASED ON FIFO TECHNIQUE USING SPARTAN-3E FPGASeminar presented for CPLD AND FPGA ARCHITECTURE COURSEby N.SAI MANI BHARATH, (14481D5516)Ist M.Tech, 2nd Sem (ES) ECE DepartmentGudlavalleru Engineering College

1IntroductionConclusionDisadvantages of single channel UART Structure of Multichannel UARTUART Block DiagramAsynchronous FIFOBaud Rate GeneratorSoftware FlowchartSpartan-3E FPGA ArchitectureAdvantages & ApplicationsConclusion

CONTENTS In the recent years the development in communication systems requires the data transmission to be performed faster and faster. To meet this demand ,a high speed multi channel UART controller based on FIFO (First In First Out) technique can be used. An Asynchronous FIFO is designed with dual port ram array and with read and right pointers. The structure of controller is designed with UART (Universal Asynchronous Receiver Transmitter) and FIFO circuit design, the structure of the controller is scalable and reconfigurable design .INTRODUCTION This controller reduces the synchronization error between the sub systems in a system with other sub systems. Mainly the controller is used to operate or implement the communication system when master equipment and slave equipment are set at different baud rate .The controller is reconfigurable and scalable and it also can be used to reduce time delays between sub-controllers of a complex control system to improve the synchronization of each sub-controller. 4Three disadvantages, which influence its efficiency are Usually, there is only one channel which can only connect to a single peripheral. So the number of chips will increase with peripherals, which may cost a lot of space and resources During interrupt request ,comes a problem that the burden of the processor will become heavier and heavier when the interrupt request occurs more and more frequently, i.e. when there are frequent interrupt requests and only a few characters are transmitted during each interrupt time, the processors implementation efficiency will reduce

Disadvantages of Normal UART

Although certain processors data bus is 32 bit wide or more, the traditional UART Controller transmits only one byte data to the microprocessor with which it connected at a time. In this case,24 bits or more of data bus are wasted

To solve the first problem more UART channels in a single chip are required

Structure of the multi channel UART controllerUART BLOCK DIAGRAM

BAUD RATE GENERATOR The controller also has a block of Baud Rate Generator to engender different Baud Rates to content requirements for different kind of systems. This block is constituted by timers (32/16 bits timers), frequency dividers and a Baud Rate setting register

An asynchronous FIFO refers to a FIFO design where data values are written to a FIFO buffer from one clock domain and the data value are read from the same FIFO buffer from another clock domain, where the two clock domains are asynchronous to each otherAynchronous FIFO (FIRST-IN-FIRST-OUT)In designing of asynchronous FIFO 2 difficult problems cannot be ignored. Judging of FIFO status based on read and write pointerMetastability

Software coding is done in Verilog HDL to design FPGAs hardware architecture, it is easy to create and adjust to satisfy requirements of applications. One UART is used to communicate with PC with other main MCU and there are also four other UARTs used to communicate with sub MCUs.Each channel has two FIFOs, one for receiving data and the other for transmitting data.SOFTWARE STRUCTURESoftware Flow Chart

Xilinx has two main FPGA families: the high-performance Virtex series and the high-volume Spartan series. The Virtex series of FPGAs have integrated features such as wired and wireless infrastructure equipment, advanced medical equipment, test and measurement, and defense systems. The Spartan series targets applications with a low-power footprint, extreme cost sensitivity and high-volume such as displays, set-top boxes, wireless routers and other applications.The Spartan-3Efamily builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell SPARTAN-3E FPGA

Spartan-3E FPGA ArchitectureMulti channel UART providing a high band width solution for communication systems requesting high data rate serial transmission protocolA multi channel UART is more hardware efficient then many individual UART`s implemented individually component reuse between several channels gives scope for hard ware reductionThe main advantage is UART controller is reconfigurable.

ADVANTAGESAPPLICATIONSMulti-channel serial IO boards, Industrial controllers Multi-port RS-232/RS-422/RS-485 cards, Factory automation and process control, Supervisory/maintenance terminals