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TIMx - Timer

Programming MicrocontrollerTIMx - Timer

Autumn term 2012

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TIMx - Timer Typical Timer Features

Four 16 bit Timers, support: Two Input Captures Two Output Compares PWM Out PWM Input One Pulse Mode

Two Clocks: External clocks, Internal Events

Prescaler DMA support

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Input Cap 2

Peripheral Bus

TIMx_ETR

Interrupt - Overflow, OCMP, ICAP

16 BitPrescaler

CK_INT

Overflow

Output Comp. 1

Output Comp. 2

Output Comp. Reg 2

Latch 2 IC1IC2

OC1OC2Control

Registers

Trigger controller

Input Cap 1

16-Bit Counter Register

Output Comp. Reg 1

ITR0

ITR3

Latch 2

Edge Detect

Circuit 2

Edge Detect

Circuit 1

MS_uC / fue1 / V01

STM32F107xx Timer ModulesRM0008 Reference manual

Advanced-control timers: TIM1 & TIM8 16-bit up, down, up/down auto-reloat counter 4 Indepent channels

Input capture, Output compare, PWM & OPM Complementary outputs with programmable dead time

General-purpose timers (TIM2 to TIM5) 16-bit up, down, up/down auto-reloat counter 4 Indepent channels

General-purpose timers (TIM9 to TIM14) 16-bit up, down, up/down auto-reloat counter 2 Indepent channels

Basic Timers (TIM6 & TIM7) 16-bit up, down, up/down auto-reloat counter

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TIM - Timer

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TIM - Timer General-purpose timers main features (1/2)

16-bit up, down, up/down auto reload counter Provide counter values for output compare and input capture

16-bit programmable pre scaler used to divide the counter clock frequency by any factor between 1 and 65’535

Up to 4 independent channels for: Input capture Output compare PWM generation One pulse mode output

Synchronization circuit to control the timer with external signals and to interconnect several timers

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MS_uC / fue1 / V01General-purpose timers main features (2/2)

Interrupt/DMA generation on the following events Update: counter overflow/underflow, counter initialization (by

software or internal/external trigger) Trigger event (counter start, stop, initialization or count by

internal/external trigger) Input capture Output compare

Supports incremental (quadrature) encode and hall-sensor circuitry for positioning purposes

Trigger input for external clock or cycle-by cycle current management

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TIM - Timer

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TIM - Timer TIMx modes of functionality

Input Capture Mode Two input pins, user programmable edge polarity Capture counter values when input edge is detected Generate interrupt when enabled Can measure input pulse width

Output Compare Mode Two output compare pins, one for each compare register Compare Register is compared with counter value Generate output signal/waveform on pin when a match occurred User programmable output signal level

Other Timer Modes Based on the Input Capture and Output Compare logic

One Pulse Mode PWM Output Mode PWM Input Mode

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TIM - Timer TIMx PWM output mode Automatic generation of a Pulse Width Modulated signal

Frequency determined by TIMx_ARR register Duty cycle corresponds to TIMx_CCRx register

Configuration for the PWM output mode OCxM bits in the TIMx_CCMRx register selects the PWM output mode for OCx OCxPE bit in the TIM_CCMRx register enables the corresponding preload

register ARPE bit in the TIMCR1 register enables auto-reload preload register CCxP bit in the TIM_CCER register defines the polarity of the OCx output CCxE bit in the TIM_CCER register enable the OCx output The duty cycle is stored in TIMx_CCR1 register The full period is stored in TIMx_ARR register

TIMx_CCR1 = 0x2ED0TIMx_ARR = 0x34E2

CC1P = 0

OLVL2

0000 0001 0002 34E22ED0 2ED1 … 0000Counter

OC1 CC1P = 0 CC1P = 0

Compare 1 Compare 2

34E2

Compare 2

34E22ED0

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TIM - Timer TIMx PWM input mode

External pulse and period measurement of an external wave Programmable first edge detection Interrupt Generation

Configuration for the PWM input mode CC1S bits of TIMx_CCMR1 register select the input for TIMx_CCR1 (TI1) CC1P bit of TIMx_CCER register selects the active polarity of TI1 (rising edge) CC2S bits of TIMx_CCMR2 register select the input for TIMx_CCR2 (TI1) CC2P bit of TIMx_CCER register selects the active polarity of TI1 (falling edge) TS bits of TIMx_SMCR register select TI1FP1 as trigger for the slave controller SMS bits of TIMx_SMCR register configure the slave controller in reset mode CC1E and CCE2 bits of the TIMx_CCER register enable the captures

Period = TIMx_CCR2

Pulse Length = TIMx_CCR1

0000 0001 0002 34E22ED0 2ED1 … 0000Counter

TI1IC2 capture IC1 capture

34E2

IC1 capture

TIMx_CCR1 = 0x2ED0 TIMx_CCR2 = 0x34E2

CC1S = 0b01CC2S = 0b10CC1P = 0CC2P = 1

MS_uC / fue1 / V01TIMx one pulse mode

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TIMx - Timer

Generation of a pulse synchronized with an external event Particular case of the previous modes

Starting the controller can be controlled by the slave mode controller Generation the waveform can be done in output compare mode

TIMx_CCR1 = 0x2ED0TIMx_ARR = 0x2ED3

CC1P = 0CC1P = 1

FFFC 0001 0002… 2ED0 2ED1 2ED2 2ED3 0000Counter

TI2

OC1 CC1P = 1 CC1P = 1

Compare 1

0000 2ED0

Configuration for the one pulse mode OPM bit of TIMx_CR1 register selects one pulse mode IC2S bits of TIMx_CCMR1 register maps TI2FP2 on TI2 CC2P bits of TIMx_SMCR register select the rising edge detection for TI2FP2 TS bits of TIMx_SMCR register configure TI2FP2 as trigger for the slave mode

controller SMS bits of TIMx_SMCR register enable TI2FP2 signal to start the counter TIMx_CCR1 register defines the passive period TIMx_ARR – TIMx_CCR1 defines the active period CC1P bit of TIMxCCMR1 register fix the polarity of the active signal

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TIM - Timer General purpose timer block diagram

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TIM - Timer Presaler

The prescaler can divide the counter clock frequency by any factor between 1 & 65536

Itis based on a 16-bit counter controlled through a 16-bit register (TIMx_PSC register)

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TIM - Timer Timer Register Map (1/3)RM0008 Reference manual (page 407)

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TIM - Timer Timer Register Map (2/3)

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Timer Register Map (3/3)6- 14

TIM - Timer

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TIM - Timer ARM Peripheral Bus 2 access (APB2)RM0008 Reference manual (page 51)

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TIM - Timer ARM Peripheral Bus 1 access (APB0)