ms_uc / dnd / v08 5- 1 vic - vectored interrupts programming microcontroller vic – vectored...

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VIC - Vectored Interrupts

MS_uC / dnd / V08

Programming MicrocontrollerVIC – Vectored interrupt controller

Autumn term 2007

32K Byte 32K Byte Burst FlashBurst Flash

64K or 96K 64K or 96K Byte SRAM Byte SRAM

256K or 512K 256K or 512K Byte Burst Byte Burst

FlashFlash

OTP OTP MemMem

UARTUARTI2CI2CSPISPITIMTIMRTCRTC

EXT. EXT. Bus Bus

GPIOGPIO

USB USB 2.0FS 2.0FS

CAN CAN 2.0B 2.0B

Enet Enet MAC MAC

PFPFQ Q

BC BC

DMADMA

INTINTR R

CntlCntl

ARM96ARM966E 6E CORE CORE

w/DSPw/DSP96 MHz 96 MHz

CLK CLK CntlCntl

ADCADC

LVD LVD BODBOD

PLLPLL JTAJTAGG

ETMETM99

STR912FW44

Internal system building block

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MS_uC / dnd / V08

Programming without interrupts

Main_Loop UART Tx UART Rx ADC

UART_SendData(ch)

GetAD-Status

ADC Status

LCD

LCD_print("Hello");

LCD_print done

UART_GetFlagStatus()

Nachricht1

The main() function executes all peripheral calls in a fixed sequence

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MS_uC / dnd / V08

What are interrupts?

Interrupts are asynchronous events that may happen any timeInterrupts stop the execution of the current task

The processor jumps into the interrupt service routine (ISR)The short ISR is executedControl is given back to the previously executing task

Interrupts may have priorities.Concurrent interrupts (interrupts that happen at the same time) are serviced according to their priorityInterrupts may be enabled or disabled

Library functions that may be executed by an ISR must be thread-safe (they have to adhere to some specific rules)An ISR should if possible not trigger another interrupt

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MS_uC / dnd / V08

Load the PC with the address contained in PC minus 0x0FF00x0000 0018 LDR PC, [PC, #-0x0FF0]

Load the PC with the address of Label FIQ_Addr:0x0000 001C LDR PC, FIQ_Addr

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Example of interrupt routine assembly code

349: __irq void EXTIT0_IRQHandler(void) 350: { 351: // used to enable LED interrupt 0x0000030C E92D500F STMDB R13!,{R0-R3,R12,R14}…and at the end:0x00000368 E8BD500F LDMIA R13!,{R0-R3,R12,R14}0x0000036C E25EF004 SUBS PC,R14,#0x00000004

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MS_uC / dnd / V08

VIC –Interrupt Controller Features

Two ARM Interrupt Controllers are connected in Daisy Chain

Generates Fast interrupt (FIQ) and Vectored interrupt requests (IRQ) to CPU

32 vectored interrupts, 16 from each VIC

Programmable priority on interrupts

27 interrupts assigned to internal Peripherals

5 interrupts assigned to Wake Up Unit ( external interrupts)

Up to 30 external interrupts from Ports 3 ( 6 inputs), 5, 6 and 7

Wake Up Unit enables/disables external interrupts, generating Wake up event in low power mode

25 other IPInterrupts

Interrupt

Controller

RTC Interrupt

IRQ Interrupt

FIQ Interrupt

RTC Interrupt

USB Resume Intr

USB Resume Intr

ARM9Core

VIC0andVIC1

WakeUpUnit

Port 3

Port 5Port 6

Port 7

30 External InterruptsWake Up Event

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MS_uC / dnd / V08

VIC Features

FIQ is a non-vectored interrupt and is dedicated to a user specified source.

IRQ is an ORed output of up to 32 interrupts. The CPU reads the current IRQ vector address in the VIC and jumps to ISR. Reading of the vector address clears the IRQ request.

Vectored_Intr_0 has the highest and Vectored_Intr_31 has the lowest priority. The interrupt input source to each Vectored Interrupt is software selectable (programmable peripheral interrupt priority).

The VIC hardware resolves the priority when multiple interrupts occur.

The IRQ and FIQ can be generated even when the AHB clock is disabled in a low power mode.

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MS_uC / dnd / V08

VIC-Wake Up Unit Features

Wake Up Unit Generates 5 interrupts to the VIC Interrupt_0 as an ORed interrupt of all 30 external

interrupts, RTC and USB Resume interrupt Interrupt_1 to _3, are interrupts selected from Ports

3,4,5 and 6 (one from each port)

Enables and configures external interrupts as inputs to the VIC

Enables and configures external inputs as Wake Up event to the CPU in Sleep mode

All inputs can be masked individually, and edge polarity is programmable

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MS_uC / dnd / V08

VIC Configuration

A vectored interrupt requires the following VIC register configuration:

Enable interrupt channel by setting the enable bit in VICx_IntEnable register

Clear bit in VICx_Select register to configure input as vectored IRQ interrupt or as FIQ interrupt.

Set the E bit and specify the interrupt source in the VICx_VectCntl (control) register

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MS_uC / dnd / V08

External Intr. Configuration

Up to 30 external interrupts from Ports 3,5,6 and 7 Only one interrupt from each port can be selected at one

time. WIU_TR Register– configure triggering edge of each

interrupt WIU_MR Register – mask out not used interrupt inputs WIU_CTRL Register – define input as interrupt or/and as

wake up event SCU_WKUPSEL Register – select one input from each port

(Ports 3,5,6,7) as interrupt input to the VIC.

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MS_uC / dnd / V08

Interrupt control block

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MS_uC / dnd / V08

Hardware interrupt sources

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Interrupt request logic 1

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Interrupt request logic 2

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Interrupt channels VIC0

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Interrupt channels VIC1

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MS_uC / dnd / V08

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MS_uC / dnd / V08

ms_uc / dnd / v08 5- 1 vic - vectored interrupts programming microcontroller vic – vectored...

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