ms_uc / dnd / v08 5- 1 vic - vectored interrupts programming microcontroller vic – vectored...

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5- 1 VIC - Vectored Interr upts MS_uC / dnd / V08 Programming Microcontroller VIC – Vectored interrupt controller Autumn term 2007 32K Byte 32K Byte Burst Flash Burst Flash 64K or 96K 64K or 96K Byte SRAM Byte SRAM 256K or 512K 256K or 512K Byte Burst Byte Burst Flash Flash OTP OTP Mem Mem UART UART I2C I2C SPI SPI TIM TIM RTC RTC EXT. EXT. Bus Bus GPIO GPIO USB USB 2.0FS 2.0FS CAN CAN 2.0B 2.0B Enet Enet MAC MAC PFQ PFQ BC BC DMA DMA INTR INTR Cntl Cntl ARM966E ARM966E CORE CORE w/DSP w/DSP 96 MHz 96 MHz CLK CLK Cntl Cntl ADC ADC LVD LVD BOD BOD PLL PLL JTAG JTAG ETM9 ETM9 STR912FW44 Internal system building block

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  • Slide 1
  • MS_uC / dnd / V08 5- 1 VIC - Vectored Interrupts Programming Microcontroller VIC Vectored interrupt controller Autumn term 2007 32K Byte Burst Flash 64K or 96K Byte SRAM 256K or 512K Byte Burst Flash OTP Mem UARTI2CSPI TIMRTC EXT. Bus GPIO USB 2.0FS CAN 2.0B Enet MAC PFQ BC DMA INTR Cntl ARM966 E CORE w/DSP 96 MHz CLK Cntl ADC LVD BOD PLL JTAGETM9 STR912FW44 Internal system building block
  • Slide 2
  • MS_uC / dnd / V08 5- 2 VIC - Vectored Interrupts Programming without interrupts The main() function executes all peripheral calls in a fixed sequence
  • Slide 3
  • MS_uC / dnd / V08 5- 3 VIC - Vectored Interrupts What are interrupts? Interrupts are asynchronous events that may happen any time Interrupts stop the execution of the current task The processor jumps into the interrupt service routine (ISR) The short ISR is executed Control is given back to the previously executing task Interrupts may have priorities. Concurrent interrupts (interrupts that happen at the same time) are serviced according to their priority Interrupts may be enabled or disabled Library functions that may be executed by an ISR must be thread-safe (they have to adhere to some specific rules) An ISR should if possible not trigger another interrupt
  • Slide 4
  • MS_uC / dnd / V08 5- 4 VIC - Vectored Interrupts Load the PC with the address contained in PC minus 0x0FF0 0x0000 0018LDR PC, [PC, #-0x0FF0] Load the PC with the address of Label FIQ_Addr: 0x0000 001C LDR PC, FIQ_Addr
  • Slide 5
  • MS_uC / dnd / V08 5- 5 VIC - Vectored Interrupts Example of interrupt routine assembly code 349: __irq void EXTIT0_IRQHandler(void) 350: { 351: // used to enable LED interrupt 0x0000030C E92D500F STMDB R13!,{R0-R3,R12,R14} and at the end: 0x00000368 E8BD500F LDMIA R13!,{R0-R3,R12,R14} 0x0000036C E25EF004 SUBS PC,R14,#0x00000004
  • Slide 6
  • MS_uC / dnd / V08 5- 6 VIC - Vectored Interrupts VIC Interrupt Controller Features zTwo ARM Interrupt Controllers are connected in Daisy Chain zGenerates Fast interrupt (FIQ) and Vectored interrupt requests (IRQ) to CPU z32 vectored interrupts, 16 from each VIC zProgrammable priority on interrupts z27 interrupts assigned to internal Peripherals z5 interrupts assigned to Wake Up Unit ( external interrupts) zUp to 30 external interrupts from Ports 3 ( 6 inputs), 5, 6 and 7 zWake Up Unit enables/disables external interrupts, generating Wake up event in low power mode
  • Slide 7
  • MS_uC / dnd / V08 5- 7 VIC - Vectored Interrupts VIC Features zFIQ is a non-vectored interrupt and is dedicated to a user specified source. zIRQ is an ORed output of up to 32 interrupts. The CPU reads the current IRQ vector address in the VIC and jumps to ISR. Reading of the vector address clears the IRQ request. zVectored_Intr_0 has the highest and Vectored_Intr_31 has the lowest priority. The interrupt input source to each Vectored Interrupt is software selectable (programmable peripheral interrupt priority). zThe VIC hardware resolves the priority when multiple interrupts occur. z The IRQ and FIQ can be generated even when the AHB clock is disabled in a low power mode.
  • Slide 8
  • MS_uC / dnd / V08 5- 8 VIC - Vectored Interrupts VIC-Wake Up Unit Features zWake Up Unit Generates 5 interrupts to the VIC yInterrupt_0 as an ORed interrupt of all 30 external interrupts, RTC and USB Resume interrupt yInterrupt_1 to _3, are interrupts selected from Ports 3,4,5 and 6 (one from each port) zEnables and configures external interrupts as inputs to the VIC zEnables and configures external inputs as Wake Up event to the CPU in Sleep mode zAll inputs can be masked individually, and edge polarity is programmable
  • Slide 9
  • MS_uC / dnd / V08 5- 9 VIC - Vectored Interrupts VIC Configuration zA vectored interrupt requires the following VIC register configuration: zEnable interrupt channel by setting the enable bit in VICx_IntEnable register zClear bit in VICx_Select register to configure input as vectored IRQ interrupt or as FIQ interrupt. zSet the E bit and specify the interrupt source in the VICx_VectCntl (control) register
  • Slide 10
  • MS_uC / dnd / V08 5- 10 VIC - Vectored Interrupts External Intr. Configuration zUp to 30 external interrupts from Ports 3,5,6 and 7 zOnly one interrupt from each port can be selected at one time. zWIU_TR Register configure triggering edge of each interrupt zWIU_MR Register mask out not used interrupt inputs zWIU_CTRL Register define input as interrupt or/and as wake up event zSCU_WKUPSEL Register select one input from each port (Ports 3,5,6,7) as interrupt input to the VIC.
  • Slide 11
  • MS_uC / dnd / V08 5- 11 VIC - Vectored Interrupts Interrupt control block
  • Slide 12
  • MS_uC / dnd / V08 5- 12 VIC - Vectored Interrupts Hardware interrupt sources
  • Slide 13
  • MS_uC / dnd / V08 5- 13 VIC - Vectored Interrupts Interrupt request logic 1
  • Slide 14
  • MS_uC / dnd / V08 5- 14 VIC - Vectored Interrupts Interrupt request logic 2
  • Slide 15
  • MS_uC / dnd / V08 5- 15 VIC - Vectored Interrupts Interrupt channels VIC0
  • Slide 16
  • MS_uC / dnd / V08 5- 16 VIC - Vectored Interrupts Interrupt channels VIC1
  • Slide 17
  • MS_uC / dnd / V08 5- 17 VIC - Vectored Interrupts
  • Slide 18
  • MS_uC / dnd / V08 5- 18 VIC - Vectored Interrupts