modeling system behaviors: a better paradigm on prototyping
TRANSCRIPT
“Modeling System behaviors”….A better Paradigm on prototyping
-Nilesh Ranpura
Electronic System Structure
Hardware development
process
Hardware development
process
Software development
process
Software development
process
System development
process
System development
process
Software input/outputHardware input/output
Abstraction trade offs
System Abstraction and Development Process
System Development happens this way Because,1. “Abstraction layers” ensure
threads running concurrently
2. Different approach of specs due to different types of team
3. More than one customer with different nature/features
SPI 5
Design Flow
Concept
Chip/Block specs
Product Specs
System data/environment
Board/proto specs
Architecturespecs
Not documented
Reference Platforms
Hardware and
proto specs
Which are those System Properties ?
Environmental
System PropertiesMixed Signal
Hardware &
Softwareco-exist
Safety/Standards/Compliance
PerformanceNew
Approaches : Green mode Error injection
Processor
FC FC
Fibre Channel Controller
StorageBlade
Compute Blade
PCIeInter-Domain Switch
I/O Hub
CPU CPUMemoryMemory MemoryMemory
PCIe System Interconnect
Switch
LocalStorage
Processor
SATA / SAS Expander
GbE GbE GbE GbE
Dual GbEController
Dual GbEController
I/O Blade
Processor
Compute Blade
I/O Hub
CPU CPUMemoryMemory MemoryMemory
Compute Blade
PCIeInter-Domain Switch
I/O Hub
CPU CPUMemoryMemory MemoryMemory
(1)PCIe Switch Applications – System Interconnect
Model parameter Values
Parameter Value Remark
MPS 128 Testbench
Payload 128/256/512 Testcase
Packet types MRD,MWR,IRD Testcase
Traffic pattern Multicast, One to one, Many to one
Testbench
Speed 2.5Ghz, 5Ghz Testcase
State PM or non PM Testbench
Active Port 2/4/5/6/8 Testcase
No of packets 20/100/500/5000 Testcase
Misc. ECRC, etc
Model Latency definition
Latency is the delay between starting and completing action Latency Definition:
Throughput (pkts/sec) = (total number of pkts(i.e. 500)/(time_t1 - time_t0)) Throughput (bits/sec) = (throughput (pkts/sec) * length * 32)
In this case, length = Payload size + 3DW headerTheoretical max throughput assumes a 20 byte framing overhead on top of payload.
After removing 8b/10 coding, useful x8 Gen2 unidirectional throughput is 4 GB/s. (4 GBps * payload) / (payload + 20) = theoretical max (second column above)
Payload(Bytes)
Theoretical(GBps) Actual throughput (GBps)Switch efficiency (Actual/Theoretical) %
32 2.462 2.000 81%
64 3.048 2.905 95%
128 3.459 3.360 97%
Usage Model and Error Model
I/O
CPU
NTBP2P
P2P P2P P2P P2P
NTB
I/O I/O I/O I/O
CPU
NTB P2P
P2PP2PP2PP2P
NTB
I/OI/OI/O
.
.
.
Internal Switch Error
I/O1GbE
PCIeSwitch
I/OHub
CPU Memory
.
.
.
I/O1GbE I/O
1GbE
PCIeSwitch
I/OHub
CPU Memory
.
.
.
.
.
.
I/O1GbE
External Error
(2)Modeling Channel properties and Mixed signal for Simple Link
1. Model as much as digital blocks up to last stage2. Last analog Transceiver can be modelled and
converted in to Differential digital by just inverting it.3. Next slide depicts digital noise and
transmission model
(2)Introduce Digital Noise
1. Send 22, 20. 15, 5(which are analog sample’s value) in digital format but in parallal. So no. of data lines = no. of analog samples * 8 bit
2. Introduce noise in numbers by inversion or value changing.
•Inversion•bit stuffing•dummy bits
Noise Model
2220155
43
8 bit value of 20(sample value)
•Inversion•bit stuffing•dummy bits
Noise Model
(2)Actual System
High speed PHY MAC
PAM modulation and Signal path processing block
(2)Actual System
1. Modeled PAM modulation scheme over digital block2. Created noise model to make noise variation between -20dB
to 30dB for high speed signals on Cable.3. Simulated virtual NEXT, FEXT, ISI with predictable noise
model.4. Loop back and system loop back mode tested
High speed PHY MAC
PAM modulation and Signal path processing block
•Inversion•bit stuffing•dummy bits
Noise Model
Thank You, All…!