microprocessor lec

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)Date: 07.10.2005Topic: Assembler DirectivesFaculty: Anita Kanavalli MSRIT

Lecture Notes

Assembler: is a program that accepts an assembly language program as input and converts itinto an object module and prepares for loading the program into memory for execution.Loader (linker) further converts the object module prepared by the assembler into executableform, by linking it with other object modules and library modules.The final executable map of the assembly language program is prepared by the loader at the timeof loading into the primary memory for actual execution.The assembler prepares the relocation and linkages information (subroutine, ISR) for loader.The operating system that actually has the control of the memory, which is to be allotted to theprogram for execution, passes the memory address at which the program is to be loaded forexecution and the map of the available memory to the loader.Based on this information and the information generated by the assembler, the loader generatesan executable map of the program and further physically loads it into the memory and transferscontrol to for execution.Thus the basic task of an assembler is to generate the object module and prepare the loading andlinking information.

Procedure for assembling a program

Assembling a program proceeds statement by statement sequentially.The first phase of assembling is to analyze the program to be converted. This phase is calledPass1 defines and records the symbols, pseudo operands and directives. It also analyses thesegments used by the program types and labels and their memory requirements.The second phase looks for the addresses and data assigned to the labels. It also finds out codesof the instructions from the instruction machine, code database and the program data.It processes the pseudo operands and directives.It is the task of the assembler designer to select the suitable strings for using them as directives,pseudo operands or reserved words and decides syntax.

Directives

Also called as pseudo operations that control the assembly process.They indicate how an operand or section of a program to be processed by the assembler.They generate and store information in the memory.

Assembler Memory models

Each model defines the way that a program is stored in the memory system.Tiny: data fits into one segment written in .COM formatSmall: has two segments data and memory.There are several other models too.

Directive for string data in a memory segment

DB define byte


Lecture NotesDW define wordDD define double wordDQ define 10 bytesExampleData1 DB 10H,11H,12HData2 DW 1234H

SEGMENT: statement to indicate the start of the program and its symbolic name.ExampleName SEGMENTVariable_name DB …….Variable_name DW …….Name ENDS

Data SEGMENTData1 DB …….Data2 DW …….Data ENDS

Code SEGMENTSTART: MOV AX,BX………Code ENDS

Similarly the stack segment is also declared.

For small models.DATA……ENDS

The ENDS directive indicates the end of the segment.Memory is reserved for use in the future by using a ? as an operand for DB DW or DDdirective. The assembler sets aside a location and does not initialize it to any specific value(usually stores a zero). The DUP (duplicate) directive creates an array and stores a zero.ExampleData1 DB 5 DUP(?)This reserves 5 bytes of memory for a array data1 and initializes each location with 05H

ALIGN: memory array is stored in word boundaries.ExampleALIGN 2 means storing from an even address


Lecture Notes

Address 0 XXAddress 1 YYAddress 2 XX

The data XX is aligned to the even address.ASSUME, EQU, ORGASSUME tells the assembler what names have been chosen for Code, Data Extra and Stacksegments. Informs the assembler that the register CS is to be initialized with the address allottedby the loader to the label CODE and DS is similarly initialized with the address of label DATA.ExampleASSUME CS: Name of code segmentASSUME DS: Name of the data segment

ASSUME CS: Code1, DS: Data1

EQU: Equates a numeric, ASCII(American Standard Code for Information Interchange) or labelto another label.ExampleData SEGMENTNum1 EQU 50HNum2 EQU 66HData ENDS

Numeric value 50H and 66H are assigned to Num1 and Num2

ORG: Changes the starting offset address of the data in the data segmentExampleORG 100H100 data1 DB 10Hit can be used for code too.PROC & ENDP: indicate the start and end of the procedure. They require a label to indicate thename of the procedure.NEAR: the procedure resides in the same code segment. (Local)FAR: resides at any location in the memory.ExampleAdd PROC NEARADD AX,BXMOV CX,AXRETAdd ENDP

PROC directive stores the contents of the register in the stack.EXTRN, PUBLIC informs the assembler that the names of procedures and labels declared afterthis directive have been already defined in some other assembly language modules.


Lecture NotesExampleIf you want to call a Factorial procedure of Module1 from Module2 it must be declared asPUBLIC in Module1.

ExampleA sample for full segment definition

Data SEGMENTNum1 DB 10HNum2 DB 20HNum3 EQU 30HData ENDS

ASSUME CS:Code,DS:DataCode SEGMENTSTART: MOV AX,DataMOV DS,AXMOV AX,Num1MOV CX,Num2ADD AX,CXCode ENDSEND START

ExampleA sample for small model

. MODEL SMALL

.DataNum1 DB 10HNum2 DB 20HNum3 EQU 30H

.CodeHERE:MOV AX,@DataMOV DS,AXMOV AX,Num1MOV CX,Num2ADD AX,CX


Lecture Notes

QUESTIONS

1: What is a directive?2: Describe the purpose of DB DW and DQ directive?3: What is the purpose of .386 directive?4: What does START indicate?


Lecture NotesBCD Arithmetic:

The microprocessor allows manipulation of BCD and ASCII dataBCD used in Cash registers and ASCII used by many programs

There are two instructionsDAA decimal adjust after additionDAS decimal adjust after subtractionBoth instructions correct the result. The BCD number is stored as packed form 2 digits/byte andif unpacked form means 1 digit/byte it functions with AL only.DAA decimal adjust after additionThe result is in ALThe Logic of this instruction

If lower nibble>9 or AF=1 add 06After adding 06 if upper nibble>9 or CF=1 add 60DAA instruction follows ADD or ADCExample1

ADD AL,CLDAA

Let AL=53 and CL=29AL=53+29AL=7CAL=7C+06 (as C>9)AL=82

Example 2

Let AL=73 CL=29AL=9CAL=9C+06 (as C>9)AL=A2AL=A2+60=02 and CF=1

The instruction affects AF,CF,PF and ZFExample3

MOV DX,1234HMOV BX,3099HMOV AL,BLADD AL,DLDAA

MOV AL,BHADC AL,DHDAA


Lecture NotesMOV CH,AL

BL=99H DL=34H99+34=CDAL=CD+6(D>9)AL=D3AL=D3+60(D>9)AL=33 and CF=1

BH=30 DH=12AL=30+12+CFAL=43DAA does not do anythingThe result is placed in CX=4333

DAS instruction follows subtractionThe result is in ALLogic of this instruction

If lower nibble>9 or AF=1 subtract 06After subtracting 06 if upper nibble>9 or CF=1 add 60The instruction affects AF,CF,PF and ZF

Example1SUB AL,BHDASLet AL=75 BH=46

AL=75-46=2F AF=1

AL=2F-6(F>9)AL=29

Example 2

SUB AL,CHDASAL=38 CH=61AL=38-61=D7 CF=1(borrow)AL=D7-60(D>9)AL=77 CF=1(borrow)

Example 3

MOV DX,1234HMOV BX,3099H


Lecture NotesMOV AL,BLSUB AL,DLDAS

MOV CL,ALMOV AL,BHSBB AL,DHDASMOV CH,AL

AL=99-34=65DAS will not have affectAL=30-12=1EAL=1E-06(E>9)AL=18The result is 1865 placed in CX

ASCII Arithmetic

Functions with ASCII coded numbersThe numbers range from 30-39H for 0-9AAAAADAAMAAS use AX as source and destination

AAAExample

add 31H and 39H the result is 6AH it should have been 10 decimal which is 31H and 30HAAA is used to correct the answerConverts resulting contents of AL to unpacked decimal digitsAAA instruction examines the lower 4 bits of AL for valid BCD numbers and checks AF=0 setsthe 4 high order bits to 0AH cleared before additionIf lower digit of AL is between 0-9 and AF=1 06 is added

The upper 4 digits are cleared and incremented by 1If the lower value of the lower nibble is greater than 9 then increment AL by 06 AH by 1AF and CF setThe higher 4 bits of AL are cleared to 0AH modifiedTo get the exact sum add 3030H to AXAASCorrect result in AL after subtracting two unpacked ASCII operandsThe result is in unpacked decimal formatIf the lower 4 bits of AL are>9 or if AF=1 then AL=AL-6 and AH=AH-1 CF and AF setotherwise CF and AF set to 0 no correction


Lecture Notes

result the upper nibble of AL is 00 and the lower nibble may be any number from 0-9

AAMFollows multiplication instruction after multiplying two unpacked BCD numbersConverts the product available in AL into unpacked BCDLower byte of result is in AL and upper in AH

Examplelet the product is 5D in ALD>9 so add 6 =13H

LSD of 13H is lower unpacked byteIncrement AH, AH=5+1=6 upper unpacked byteAfter execution AH=06 and AL=03

MOV AL,5MOV CL,5MUL CLAAM

Accomplishes conversion by dividing AX by 10Benefit of AAM –converts from binary to unpacked BCDuse of AAM for conversionXOR DX,DXMOV CX,100DIV CX

AAMADD AX,3030HXCHG AX,DX

AAMADD AX,3030H

AADAppears before divisionrequires AX to contain two digit unpacked BCD number(not ASCII) before executingAfter adjusting AX with AAD it is divided by an unpacked BCD number to generate a singledigit result in AL with remainder in AHExample.MODEL.CODE.STARTUPMOV AL,48HMOV AH,0AAMADD AX,3030H

MOV DL,AHMOV AH,2


Lecture NotesPUSH AXINT 21HPOP AXMOV DL,ALINT 21H

.EXITEND

Logic instructions

ANDORExclusive ORNOTTEST

The above instructions perform bitwise operation and the src and destination could be register ormemory location. Their function is same as logic opeartions

Shift instructionsThey manipulate binary numbersUsed to control I/O Devices. Shift operation moves the number either to left or right within

memory location or a register. There are four instructions.There are two types of shift (1)arithmetic and (2) logical. The shift left operation is equivalent to multiply operation and shiftright is divide operation. The data is shifted to left or right only by one position.

Shift left operation

Logical left: The contents of the register or memory location are shifted left by one position theMSB bit moves to Carry flag bit and a zero is added to the LSB positionExample

SHL AX,1AX=0000 1111 0000 1111 and Carry=1

After the execution of the instruction

AX=0001 1110 0001 1110 and Carry =0Example

MOV CL,3SHL DX,CL

The contents of the DX register are shifted left by three postions

Arithmetical Left: It is same as logical left shift.


Lecture NotesLogical right: The contents of the register or memory location are shifted right by one positionthe LSB bit moves to Carry flag bit and a zero is added to the MSB position

ExampleSHR AX,1AX=0000 1111 0000 1111 and Carry=0

ResultAX=0000 0111 1000 0111 and carry=1

Arithmetic right: The contents of the register or memory location are shifted right by oneposition the LSB bit moves to Carry flag bit and the sign bit is copied through the MSB position

Example

SAL AX,1

AX=1000 0000 0000 1111 and carry=0Result

AX=1100 0000 0000 0111 and carry=1

Example

SAR SI,3

SI= 1010 1100 1010 0101 C=0After first shift SI= 1101 0110 0101 0010 C=1

second shift SI=1110 1011 0010 1001 C=0third shift SI= 1111 0101 1001 0100 C=1

All condition flags are affected

Rotation instructions

There are four rotate instructions.

Rotate left: The contents of the memory location or the register are rotated left by the no ofpositions indicated in the instruction through the carry or without the carry.

ROL BL,4Let BL=0001 0110 C=0After first rotate C= 0 BL= 0010 1100After second rotate C=0 BL= 0101 1000After third rotate C=0 BL= 1011 0000After fourth rotate C=1 BL= 0110 0000


Lecture Notes

Rotate right

The contents of the memory location or the register are rotated right by the no of positionsindicated in the instruction through the carry or without the carry.

String instructions

REP it is a prefix used with instructionREPE/REPZREPNE/REPNZThese are used with CMPS and SCAS instructionsThese instructions are used in the program as prefix.

CMPSCompare string byte or string wordOnly Flags affected

Zero flag set if strings match otherwise resetDS:SI and ES:DI are used to point to the two strings

SCASScans the string of bytes or words for an operand byte or word specified in register AL or AXWhen match found the ZF=1 otherwise it is resetLODSLoad string byte or string wordLoads the AL/AX register by the contents of a string pointed by DS:SI No flag affectedSTOSStores contents of AL/AX register to a location in a string pointed by ES:DINo flag affected

A bus is used to communicate between components in a computer system. They are typicallyspecialized, with (for instance) a memory bus having different characteristics from an IO bus.Communications used in networks are different again.

An important distinction to be drawn early is that between a bus and a point-to-point network. Abus has a single wire, or connection of wires with multiple sources and destinations. A point-to-point network has some sort of interconnection scheme between sources and destinations inwhich the nodes are endpoints. In general a bus is cheaper and slower than other networktopologies; there is a shift in progress in some areas from busses to point-to-point networks; thisis most noticeable in high-speed ethernet and in AMD's multiprocessor system ``busses.''


Lecture NotesBus operations should be thought of in terms of transactions. A bus transaction is an operationon the bus; for instance, a memory read, or an interrupt service, or an IO write. A bus transactionis initiated by a bus master who requests that some operation take place; a slave will respond tothe transaction appropriately. Different busses support different sets of transactions

Bus ComponentsBusses typically have several components in common. In general, dedicated groups of wires areused for the different components (but see multiplexing, below).

1. Data: this is the whole purpose of the bus - to transmit data. Ordinarily, when you talkabout the ``width'' of a bus (8-bit bus, 32-bit bus, etc), you're talking about how manywires are used for data.

2. Address: this is how the components on the bus recognize that data on the bus isintended for them. Ordinarily, whenever a bus transaction takes place, an address is puton the bus... recipient can tell who it's for. Memory and IO busses don't normally put asource address on; that's either implicit in the transaction or irrelevant. Networks, on theother hand, usually do.

3. Control: these wires contain a variety of information about the transaction, for instancewhat type of transaction it is (read, write, interrupt request, etc). Most parallel busses mayalso have a global clock, which would be a control line as well. A serial bus can't verywell do that, so the clock has to be carried with the data somehow.

4. Power and Ground: the bus has to have a ground wire, so the different components havea common voltage reference (they'll normally have lots of ground wires, for electricalimmunity!). Also, all the cards in the bus need to get power from somewhere, so the busitself is a convenient place to distribute it.

PCI Bus

The Peripheral Component Interconnect (PCI) bus is the standard I/O bus on recent computers ingeneral, and PCs in particular.It was developed by Intel in 1993 to replace the various busses which had been in use on both PCs and Macintoshes.It is a 32-bit, 33MHz bus with multiplexed address and data, and very nice capabilities forautoconfiguration ("Plug and Play"). It also supports both old, 5 volt devices and newer, 3.3 voltdevices.

Just as a brief note, it was developed by Intel in 1993 to replace the various busses which hadbeen in use on both PCs and Macintoshes. To Intel's credit, it is a remarkably architecture-neutralbus. A very brief description would be that it is a 32-bit, 33MHz bus with multiplexed addressand data, and very nice capabilities for autoconfiguration ("Plug and Play"). It also supports bothold, 5 volt devices and newer, 3.3 volt devices.

There are many extensions to PCI. Best known is that it has simply been extended to 64 bits and66 MHz. In addition, there is a variant called PC-104+, which is a 32-bit PCI bus in a highly


Lecture Notesshock and vibration resistant packaging. PCI-X is a backward-compatible extension to PCI, withPCI-X itself running at 266MHz and PCI-X 2.0 at 533 MHz. This latter also defines a 16 bitinterface for space-constrained applications, and a new bus mastering protocol (PCI SIG likes tocall this peer-to-peer) that looks a lot like messaging.

All transfers on the PCI bus are "burst" transfers. What this means is that once a device obtainsthe bus to perform a transfer, it is able to hang on to the bus indefinitely, and keep sending moredata every bus cycle (there's actually a time in the bus controller which will take control backafter some configurable time period, to keep transfers from being too long. The longer thetranfers are the better the throughput, but this can cause unacceptable delays for other devices).

Configuration Space

One of the nicest features of PCI is its support for autoconfiguration. In addition to every devicehaving an address on the PCI bus, every card has its own address determined by which slot it isplugged into. This is referred to as the card's configuration space, and can be queried (and partsof it can be written) by the CPU. This normally occurs at boot time; it may be performed by theBIOS prior to starting the boot loader, or it may be performed by the OS as it boots.

Here's a picture of the configuration space for a PCI device

The most important parts of the configuration space are:

Vendor and Device IDThe Vendor ID is a 16 bit number, assigned by the PCI SIG. You can look this numberup in a database to find out who built the card. The device ID is another 16 bit number,assigned by the vendor. You can look this up in a database to find out the device model

Header(64 bytes)

Available(192 bytes)

00H

3FH

FFH

Identification

Status/Command

ClassBIST

Special


Lecture Notesnumber. Put them together and you can know what kind of device you're going to betalking to, so you can run the right device driver.

Class CodeThis is a 24 bit number, assigned by I-don't-know-who, which identifies what kind ofdevice is on the card. The difference between this and the vendor/device id fields is thatthis will specify something like "serial port" You can run the device based on its classcode, but to take advantage of any extra features (like the fact it might be an 8-port cardinstead of a single-port card) requires the vendor and device IDs.

Base RegistersUp to six base registers can be specified, for the devices located on the card. If you havefewer than six logical devices you will actually use fewer than these; if you have more,you will have to get into some ugly hacks (for instance, on an eight port serial card Ihave, six of the ports' base addresses are specified in the base addresses, while two are atfixed offsets from the first two of the six). Unlike the vendor and device ID fields, andthe class codes, the base register addresses are read/write.

PCI Commands

There are a total of 16 possible commands on a PCI cycle. They're in the following table:

Command Command Type0000 Interrupt Acknowledge

0001 Special Cycle

0010 I/O Read

0011 I/O Write

0100 reserved

0101 reserved

0110 Memory Read

0111 Memory Write

1000 reserved

1001 reserved

1010 Configuration Read

1011 Configuration Write

1100 Multiple Memory Read

1101 Dual Address Cycle

1110 Memory-Read Line

1111 Memory Write and Invalidate

Here are some notes on the different transfer types

Interrupt Acknowledge (0000)


Lecture NotesThe interrupt controller automatically recognizes and reacts to the INTA (interruptacknowledge) command. In the data phase, it transfers the interrupt vector to the ADlines.

Special Cycle (0001)AD15-AD0

0x0000 Processor Shutdown

0x0001 Processor Halt

0x0002 x86 Specific Code

0x0003 to 0xFFFF ReservedI/O Read (0010) and I/O Write (0011)

Input/Output device read or write operation. The AD lines contain a byte address (AD0and AD1 must be decoded). PCI I/O ports may be 8 or 16 bits. PCI allows 32 bits ofaddress space. On IBM compatible machines, the Intel CPU is limited to 16 bits of I/Ospace, which is further limited by some ISA cards that may also be installed in themachine (many ISA cards only decode the lower 10 bits of address space, and thus mirrorthemselves throughout the 16 bit I/O space). This limit assumes that the machine supportsISA or EISA slots in addition to PCI slots. The PCI configuration space may also beaccessed through I/O ports 0x0CF8 (Address) and 0x0CFC (Data). The address port mustbe written first.

Memory Read (0110) and Memory Write (0111)A read or write to the system memory space. The AD lines contain a doubleword address.AD0 and AD1 do not need to be decoded. The Byte Enable lines (C/BE) indicate whichbytes are valid.

Configuration Read (1010) and Configuration Write (1011)A read or write to the PCI device configuration space, which is 256 bytes in length. It isaccessed in doubleword units. AD0 and AD1 contain 0, AD2-7 contain the doublewordaddress, AD8-10 are used for selecting the addressed unit a the malfunction unit, and theremaining AD lines are not used.

Multiple Memory Read (1100)This is an extension of the memory read bus cycle. It is used to read large blocks ofmemory without caching, which is beneficial for long sequential memory accesses.

Dual Address Cycle (1101)Two address cycles are necessary when a 64 bit address is used, but only a 32 bit physicaladdress exists. The least significant portion of the address is placed on the AD lines first,followed by the most significant 32 bits. The second address cycle also contains thecommand for the type of transfer (I/O, Memory, etc). The PCI bus supports a 64 bit I/Oaddress space, although this is not available on Intel based PCs due to limitations of theCPU.

Memory-Read Line (1110)This cycle is used to read in more than two 32 bit data blocks, typically up to the end of acache line. It is more effecient than normal memory read bursts for a long series ofsequential memory accesses.

Memory Write and Invalidate (1111)


Lecture NotesThis indicates that a minimum of one cache line is to be transferred. This allows mainmemory to be updated, saving a cache write-back cycle.

Interrupt Handling

PCI uses four pins, called INTA-INTD, for interrupt requests.When an interrupt is required, the proper pin is asserted.A card which only has a single interrupt will normally use INTAIn the modern systems BIOS exists which support PCI bus

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Port detailsThe parallel port LPT1 is normally at I/O port addresses 378H, 379H and 37AHThe secondary port(if present) is located at 278H, 279H and 27AHThe parallel printer interface is located on the rear of the PCLPT stands for Line printerThe printer interface gives access to eight lines that can be programmed to receive or send data

The Centronics interface implemented by the parallel port uses two connectersOne is 25 pin D type on the back of the PCThe other one is 36 pin on the back of the PrinterThe parallel port can work as both transmitter and as well as receiverOther than printers CD ROMs can also be interfaced through parallel port.

Universal Serial Bus (USB) allows the addition of a new device to a PC by plugging it into theback of the machine or daisy-chaining it from another device on the bus. The device isimmediately available for use (no rebooting required) and often does not need a device driver tobe installed (depending on the operating system being used.

USB 1.1 allows communication speeds of 12 Megabits per second (or 1.5 Megabytes persecond). The enhanced USB 2.0 will use the same cables, connectors, and software interfacesand will be backward compatible with older devices. USB 2.0 carries data at 360 to 480 Mbps(60 MBps). All cables use four wires; the distance between two devices can be up to five meters.

A big advantage of USB devices, apart from their much greater speed, is that USB devicesconfigure themselves automatically: gone are the days when you had to fiddle with IRQ settings,DMA channels, and I/O addresses to make a gadget work. Another benefit is that because USBdevices do not require IRQ settings, DMA channels, or I/O settings, COM and LPT portscurrently occupying an IRQ can be freed up, making more IRQ interrupts available for otheruses.

Another advantage of USB is that it is a standard port and can support just about any type ofdevice, including keyboards, mice, serial peripherals (e.g. modems), printers, audio input/output,joysticks, digital cameras, scanners, external hard disks and CD burners. Soon, the collection ofspace-consuming and costly dedicated ports for keyboards, printers, mice, modems etc will


Lecture Notesdisappear and replaced by USB. USB can be built into most chipsets for about $1. The otheradvantage is that you can mix and match devices as much as you like. In the old days, if you hada parallel port scanner and a printer, they had to share the single printer port (and neither of themwould work properly for long.)

If you have several USB devices, it is best to use a USB hub. This is a little box that splits asingle USB port into 4 or more ports

USB uses a four-wire cable interface. Two of the wires are used in a differential mode for bothtransmitting and receiving data, and the remaining two wires are power and ground. The sourceof the power to a USB device can come from the host, a hub, or the device can be "selfpowered." There are two different connector types on each end of a USB cable. One of theseconnectors is for upstream communications, and the other for downstream. Each cable length islimited to about 5 meters.

USB has four types of communication transfer modes:

control,

interrupt,

bulk, and

isochronous.

Control mode is initiated by the host. In this mode, every data transfer must send data in bothdirections, but only in one direction at a time. The control mode is used mainly for initializationof devices, but it can also be used to transfer small amounts of data.

In interrupt mode, interrupts do not occur in the usual sense. As in control mode, the host has toinitiate the transfer of data. Interrupt mode works by the host querying devices to see if they need

To be serviced

Bulk mode and isochronous mode complement each other in a sense. Bulk mode is used whendata accuracy is of prime importance, but the rate of data transfer is not guaranteed. An exampleof this would be disk drive storage. Isochronous mode sacrifices data accuracy in favor ofguaranteed timing of data delivery. An example of this would be USB audio speakers.

These four modes will be discussed in more detail below.


Lecture Notes

Above is an example of USB ports found on PCs and on some USB peripherals includingkeyboards and monitors.

The PC host typically has connections for two external USB ports. Each of these two connectorson the PC is actually a connection to a separate root hub inside the PC. If either of the two roothubs needs to have more than one device connected to it, a downstream USB hub is required toexpand connections. Hubs are used to add to the number of devices that can be connected to oneUSB port. They can be considered to be a repeater of sorts and also a controller. When a deviceis connected downstream of a hub, the hub does the connect detection of the new device andnotifies the host.

Hubs can be inside the device itself -- for example, in a keyboard that may have an additionaltwo downstream USB connectors for additional devices. A hub can have a combination of highand low speed devices connected to it, up to a maximum of four additional hubs downstreamfrom itself. A hub's upstream port to the PC must be high speed. The hub acts as a traffic cop,handling communication to downstream devices as either high or low speed. A hub can ignore adownstream device that is not behaving properly. Hubs can be either self-powered or receivepower from the USB bus. USB 1.x hubs support both low and high-speed data transfers.There are several hardware requirements for devices that are placed on the USB bus. Five voltsis the nominal supply voltage on the bus. A device that requires 100mA or less can be poweredfrom the host or any hub, provided that the total available power hasn't already been exhaustedby other devices. A device on the bus can draw up to 500mA from it. However, not all USBhosts (especially a battery powered PC) or bus-powered hubs will allow a device to draw morethan 100mA from the bus. For this reason, a USB device that draws more than 100mA should, inmost cases, be self-powered .A device tells the host how much current is required for its operation. Self-powered devicesusually get their power from a separate power supply or batteries. A battery-powered deviceplugged into the bus can get its power from the bus if it meets the tests above, and it can thenswitch back over to battery power when it is disconnected from the bus or when the host is shutdown. When a device is in suspend mode, it cannot draw any more than 500uA from the bus if itis bus-powered. Also, if a device has not seen any activity on its bus in 3 mS, it needs to go intosuspend mode. A host can initiate a resume command to a device that is in suspend mode. Adevice can also issue a remote wakeup to an inactive host to make it active.All devices have endpoints, which are memory buffers. An endpoint can be as simple as anaddressable single register, or it can be a block of memory that is used to store incoming and/oroutgoing data. There may be multiple endpoints inside a device. Each device has at least oneendpoint -- "endpoint 0"-- which is used as a control endpoint. It must be able to both send andreceive data, but can only communicate in one direction at a time. Typically, when a device


Lecture Notesreceives data such as an Out or Setup command from the host, this data is stored in the endpointand the device's microprocessor is interrupted and works on this data. When a device receives anIn command that is addressed to it from the host, data for the host that is stored in the endpoint issent to the host.The host is considered to be the master in most all cases. One exception is when a device issues aremote wakeup to the host as discussed above. There are time limits for both the host and deviceto respond to each other. For example, if the host requests data from a device using an Incommand, the device must send the data back to the host within 500mS, in some cases.Depending on the transaction type, the host and/or the device may respond to data received withan acknowledgement. Data transfer involves quite a bit of error-checking and handshaking. Thedifferent types of data packets sent and received use different ways to verify correct data transfer.A logical connection link needs to be set up between the host and a device before a transactioncan occur. This connection is referred to as a Pipe. It is set up as soon as possible after a host hasrecognized a device as being connected. When the host responds to a connect signal from thedevice, one of the parameters that is sent to the host is the device's required data transfer type andspeed. The host can refuse to establish a Pipe if the host does not have enough bandwidth tosupport the device's request or if its power requirements cannot be met. The device at itsdiscretion can lower its requested data rate and try again until the host accepts it and initiates aPipe.When a device is connected, it also sends to the host descriptor information on the types ofendpoints in the device, the type of data transfer it uses, size of data packets, endpoint addresseswithin the device, and if used, the time required between data transfers.The following describes a typical data flow for a device when it is initially plugged into a host'sbus while the host is active. Remember here that the host has an internal USB hub, andadditional hubs may be connected downstream from the host's hub.

1. The host recognizes that a device has been attached to one of its USB hubs. It realizesthis by a simple resistive divider that is connected to the differential data pair of wires inthe USB bus. These resistors are inside the USB hubs and devices.

2. The host sends a Get_Port_Status request to the hub to find out more about what has beenplugged in. It could be another hub, a device connected directly to the host hub, or adevice that has been plugged into one of the downstream hubs.

3. After receiving a response from the hub, the host issues a Set_Port_Feature command inwhich the hub issues a reset over the data pair but only to the newly connected device onthe USB bus.

4. The host then checks to see if the device has come out of the reset state by issuing aGet_Port_Status command to the hub. After reset, the device is in the Default state andcan only draw a maximum of 100mA. In Default state, the device can communicate withthe host through Endpoint 0.

5. The hub now detects the device's speed by using the resistive dividers that are attached tothe USB bus. The hub sends the speed of this device back to the host.


Lecture Notes6. The host then sends a Get_Descriptor command to the hub in which the hub gets the

packet size needed from this particular device and sends the result back to the host.

7. The host now issues a Set_Address command to the hub which sends this information tothe device. The device in turn acknowledges the command back through the hub to thehost and sets up this address internally.

8. To learn more about this device, the host sends a Get_Descriptor command to the addressthat the device has been given. The information that is returned to the host consists ofvarious details of the device that the host needs to know for its operation. These queriesby the host continue two more times to retrieve all the information needed.

9. Based on the information received from the device, the host determines the best devicedriver to use for communications with it.

10. The device driver in the host now takes over by requesting a Set_Configurationcommand. There can be several configurations for one device, and the device driverdetermines which to use based on information received from the device in response to theGet_Descriptor command.

11. The device is now ready for use.

As you can see, the USB protocol is a fairly complex arrangement. This strict pattern of queryand response, however, is important in alleviating potential conflicts on the bus.--------------------------------------------------------------------------------------------------------------------

Addition:

There are two instructions ADD and ADC

Register Addition:

ADD AL,BL AL=AL+BLADD CX,DI CX=CX+DIADD CL,10H CL=CL+10ADD [BX],AL the contents of AL are added with the contents of a memory locationaddressed by BX and the result is stored in the same memory location

Example

ADD AL,BL AL=10H BL=30H the result AL=40H


Lecture NotesADD AX,[SI+2] the word content of the data segment memory location addressed by sum ofSI+2 is added with AX and the result is stored in AX

Example

AX=1234H SI=2000 SI+2=2002 and let the word stored in memory location 2002 be1122H The result AX=2356HADD BYTE PTR [DI],3 –3 is added to the byte contents of the data segment memorylocation addressed by DI

Example

DI=2000 and the contents of that memory location is 11HThe contents of address 2000 will be 14H after the execution of this instruction

The contents of the flag register change after the addition operation. The flags affected areSIGN,CARRY,ZERO, AUX CARRY,PARITY,OVERFLOWThe INTR,TRAP and other flags not affected.

Immediate Addition

An 8 bit immediate data is added.

Example

MOV AL,10HADD AL,30HThe result AL=40H

Memory to Register addition

ExampleMOV AX,0ADD AX,DIADD AX,DI+1Let DI=2000 the contents of this memory location is 22HAfter first add AX will have 22+0=22HThen DI+1=2001 let the contents be 11HThe result will be 33H

Array addition The offset address of the array is moved to the SI or DI register

Example

MOV AL,0MOV SI,OFFSET of Array


Lecture NotesADD AL,[SI]ADD AL,[SI+2]ADD AL,[SI+4]

ArrayOffsetaddr

2000 10H

2001 11H2002 22H2003 33H2004 44H

After first add the contents AL will be 0+10=10HAfter the second add instruction AL will be 10+22=32HAfter the third add instruction AL will be 32+44=76H

Increment addition

INC adds a 1 to a register or a memory location used for memory incrementsExample

INC AXThis instruction adds one to the contents ox AX let Ax=1234H the result will be AX=1235HINC BYTE PTR [DI]This instruction adds one to the byte contents of the data segment location addressed by DI

Addition with carry

ADC adds the bit in carry flag to the operand data.

Example

ADC AL,BH AL=AL+BH+CARRYADC CX,AX CX=CX+AX+CARRYADC BX,[BP+2] the word contents of the stack segment memory location addressed byBP+2 is added to BX with carry and the result is stored in BX.

SubtractionMany forms of subtraction appears to use with any addressing mode 8 16 and 32 bit dataSUBSBB subtract with borrowRegister Subtraction:SUB AL,BL AL=AL-BLSUB CL,10H CL=CL-10The carry flag holds the borrow.


Lecture Notes

Decrement

A 1 is subtracted from the register or the memory location.

ExampleDEC AXDEC BYTE PTR [DI]DEC CLDEC BL

Subtracts 1 to from a register or a memory location

CMP

This changes only the flag the destination operand never changesThis instruction is usually followed by conditional jump instructionsand tests the condition against the flags

Multiplication

The multiplication is performed on bytes words or double words and can be a signed integer orunsigned integerMUL: unsignedIMUL: signedFlags CARRY,OVERFLOW

8 Bit multiplicationExample

MOV BL,05HMOV AL,10HMUL BL

The multiplicand is in ALThe multiplier is in BL (even a memory location can be used)

8 Bit multiplicationExample

IMUL BYTE PTR [BX]AL is multiplied by the byte contents of the data segment memory location addressed by BX thesigned product is placed in AX

For signed multiplication the product is in true binary form if positive and in two’s complementform if negativeExampleAL 00000010 BL 10000100


Lecture NotesAL contains +2 and BL contains -4IMUL BLThe product is -8The product is in two’s complement form stored in AXAX 11111000

Division

DIV,IDIVThe dividend is always a double width dividend that is divided by the operandAn 8 bit division devides a 16 bit number by a 8 bit numberErrors: Divide by zero,devide overflow

AX register stores the dividend that is divided by contents of any 8 bit register or memorylocation.the Quotient(result) moves to AL and AH has the remainder.For signed division the remainder always assumes sign of dividend and is an integerAX=0010H equivalent to +16BL=FDH equivalent to -3DIV BLAL=05H and AH=-1 11111111HAX=1111111100000101H

AX=0010H equivalent to +16BL=FDH equivalent to -3DIV BLAL=-5 11111011 and AH=1AX=0000000111111011H

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