Microprocessor History

• PMOS technology – slow and awkward to interface with TTL family

• 4 bit processor• Instructions were executed in about 20 µs.• Intel 4004 the first MP. 4K nibbles address

space.• Intel 8008- can manipulate a whole byte.• 16Kbytes address space• 50,000 operations/second.

Early microprocessors

N-channel MOSFET

• 1970.

• Faster than P-MOS.

• Work with +ve supply; easy to interface with TTL.

• 1973 Intel 8080 MP.

• 500,000 operations/second.

• 64K bytes memory.

• Upward software compatible with 8008.

• Other brands are MC6800, Fairchild’s F-8 etc.

Basic types of MP

• Two types– Single component microprocessors– Bit sliced microprocessors

• Can be cascaded to allow functioning systems with word size from 4 bits to 200 bits.

Single component M Computer

• Composed of– A processor– read only memory (for program storage)– Read/Write memory (for data storage)– Input/output connections for interfacing– Timer as event counter

• Intel 8048, Motorola 6805R2.– Oven, washing machine, dish washer etc.

Modern MP

• 8, 16, 32, 64 bits are available.• Intel 8085, Motorola 6800 – 8 bit word 16 bit

address.• Intel 8088, 8086, Motorola 68000 – 16 bits word,

20 bits address.• 80186 – never used.• 286 – real mode and protected mode; 16MB

memory• 386 – paging, 4GB memory, 32 bits word• 486 – math coprocessor, L1 cache

Modern MP

• Pentium – 64 bits i/o off the chip but process 32bits word, exception floating

point processed 64 bits, cache doubled, instruction pipelining.• Pentium Pro

– L2 cache, Improved pipelining• Pentium MMX

– Multi-Media extensions, 57 new inter instruc mostly used for multimedia programming

• Pentium II, III, IV– Pentium pro with MMX tech, increased L2 cache, full 64 bit

operation• RISC

– Reduced instruction set processor, uniform length instruc, faster in operation, cannot perform may different thing as CISC.

MP based system

MP memory IO device

Basic MP architecture

• Fetch, decode, execute.

• PC increment.

• First instruction is a fetch– 0000H for 8085– FFFF0H for

8086, 8088

Register Array

control

InstructionRegister A

LU

Data Bus

Address Bus

ControlBus

AF, BC, DE, HL, SP, PCmany more

Memory Interfacing and IO decoding

• Interfacing needs bus

• Isolation and separation of signals from different devices connected to MP. – Unidirectional– Bidirectional

• LS373, 244

Memory map

• Pictorial representation of the whole range of memory address space.– Defines which memory system is where, their

sizes etc.

• Address space or range.– 8086 has 1M address space in minimum

mode.– 8085 has 64K address sspace.

Address Decoding

• Address decoder is a digital ckt that indicates that a particular area of memory is being addressed, or pointed to, by the MP.

• Absolute address decoding– Decode an address to one single output– Decode 10110 so that u can get a signal from the

decoder when it receives exactly that bit pattern.

• Partial address decoding– Some bits are used as don’t care so that decoder

gives a signal for a range of consecutive bit patterns.

1 0 1 1 0 1 0 1 1 0

a b c d e

a b c d e

Can use decoder IC with gates to achieve exact decoded o/p

Logic 1

8 input NAND gate implementation

Active low o/p signal

Absolute decoding

3 to 8 line dcd1 0

1

0

7

o/p

Partial decoding

• When a range of addresses are deconded then it is called partial decoding. For example, if we need to generate a control signal for an address generated by the MP within the range FFF0 – FFFF, then it is called partial decoding.

• Decoder, multiplexer can be used for address decoding

1 1 1 1 1 1 1 1 1 1 1 1 x x x x

A15

A14

A4

Bus control signals

8085

IO/M

RD

WR

MEMR

MEMWR

IOWR

IOWR

Interfacing A Memory Chip

MemoryChip

3 to 8decoder

E1 E2 E3

A15A14IO/M

A13

A12

A11Q1

CEA10

A9

A0

D7

D0

D6

RDWR

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

• 2K Byte memory• Memory address space of the chip:8800H to 8FFFH

1 0 0 0 1 X X X X X X X X X X X

MEMSEL

8 8 - F 0 - F 0 - F

Reading a byte from memory

• Reading an Opcode 4Fh in memory location 2005H.– PC places the 16bit address 2005H of the

memory location on the address bus.– Control unit sends the memory read signal

(MEMR) to enable O/P buffer of the memory chip.

– The value 4Fh stored in location 2005H is placed on the data bus and transferred to instruction decoder of the MP.

8085 functional block diagram

WTemp Reg (8)

ZTemp Reg (8)

H(8)

L (8)

B(8)

C(8)

D(8)

E(8)

Stack pointer(16)

Program counter (16)

Incrementer/decrementer Latch (16)

Reg

Se

lect

MUX

Address buffer (8) Data/Add buffer (8)

InstruRegister (8)

InstruDecoderFlags

Accumu Temp Reg

Timing & control

Interrupt control Serial I/O control

External Address bus(8)

External Add/data bus(8)

MP operations

1. MP initiated Operations• Memory/IO read/write

2. Internal operations• Store 8-bit data• Arithmetic and logical operations• Test for conditions• Sequence the execution of Instruction• Stack operation

3. Peripheral operations• Reset, Interrupt, ready and hold

Flag register

S Z AC P CY 1. S : after the execution of an arithmetic operation, if bit 7 of the result is 1, then sign flag is set.

2. Z : bit is set if ALU operation results a zero in the Acc or registers.

3. AC: bit is set, when a carry is generated by bit 3 and passed on bit 4.

4. P: parity bit is set when the result has even number of 1s.

5. CY = carry is set when result generates a carry. Also a borrow flag.

Accumulator

• Hold data for manipulation (arithmetic, logical).• Whenever the operation combines two words,

either arithmetically or logically, the accumulator contains one word (say A) and the other word (say B) may be contained in a register or in memory location. After the operation the result is placed in the Acc replacing the word A.

• Major working register. MP can directly work on Acc.

• Programmed data transfer.

General purpose registers

• Six registers.

• B, C, D, E, H and L can store 8 bit data.

• They can be combined to perform some 16 bit operation.

ALU

• Arithmetic logic unit.• Two input ports, one output port.• Perform AND, OR, ExOR, Add, subtract,

complement, Increment, Decrement, shift left, shift right.

• ALUs one temporary registers are connected to MPs internal bus from which it can take data from any registers. It can place data directly to data bus through its single output port.

Program counter

• Its job is to keep track of what instruction is being used and what the next instruction will be.

• For 8085 it is 16 bit long.• Can get data from internal bus as well as

memory location.• PC automatically increments to point to the next

memory during the execution of the present instruction.

• PC value can be changed by some instructions.

Stack pointer

• 16 bit register acts as memory pointer.

• Can save the value of the program counter for later use.

• points to a region of memory which is called stack. follows LIFO algorithm.

• After every stack operation SP points to next available location of the stack. Usually decrements.

Memory address register

• PC sends address to MAR. MAR points to the location of the memory where the content is to be fetched from.

• PC increments but MAR does not.• If the content is an instruction, IR decodes it.

During execution if it is required to fetch another word from memory, PC is loaded with the value

• PC again sends it to the MAR and fetch operation starts.

Instruction register

• Holds instruction the microprocessor is currently being executed.

• 8 bit long.

others

• Instruction decoder.

• Control logic.

• Internal data bus.

Machine cycle and Timing dia

• MP works in steps of clock. Each clock cycle is called T-state.

• A machine cycle is composed a few T-states and performs either read or write operations.

• All MP instructions are divided into few machine cycles.– Opcode fetch– Memory read– Memory write– IO read– IO write

Timing diaga. of Memory cycle

CLK

A15-A8

AD7-AD0

IO/M

RD

MEMRD

A7-A0 A7-A0Data from MPU

Data from memory

WR

MEMWR

T1 T2 T3

ALE

T1 T2 T3

READ Cycle WRITE Cycle

MVI A,32H Instruction2000H 3EH ;MVI A, 32H

2001H 32H

00H; low-order Add

3E; opcode

T1 T2 T3 T4 T1 T2 T3

20H; high-order address

01H; low-order Add

32H; Data

Unspecified 20H; High-order address

Status IO/M=0,S1=1,S0=1; opcode fetch Status IO/M=0,S1=1,S0=0; data read

RD

ALE

AD7-AD0

A15-A8

M1 (Opcode-fetch) M2 (Memory Read)

Execution time

• Clock frequency f = 2 MHz• T-state = (1/f) = 0.5 µs• Exec time for opcode fetch= (4Tx0.5)=2 µs.• Exec time for memory read = 3Tx0.5=1.5 µs.• Exec time for instruction = 7Tx0.5 = 3.5 µs.

8085

• 40 pin DIP.

• +5V

• 3 - 5MHz– ADD BUS– DATA BUS– CONTROL STATUS– POWER SUPPLY AND

FREQ– EXTERNALLY INITIATED

SIGNALS– SERIAL I/O PORTS

21 – 28HIGH ORDER

ADD BUS

5V GND

30 ALE

29 S0

33 S1

34 IO/M’

32 RD’

31 WR’

CLK OUTRESET OUT

HLDA 38

INTA 11

RESET IN 36

HOLD 39

READY 35

INTR 10

RST5.5 9

RST6.5 8

RST7.5 7

TRAP 6

SOD 4

SID 5

12 – 19MUX ADD/ DATA BUS

2040

X1 X2

3 37

• 8085 has the clock generation circuit on the chip. 8085 can operate maximum 3.03 MHz and 8085A-2 can operate maximum 5 MHz clock.

• crystal, LC tuned, external clock ckt.

• the frequency at x1x2 is divided by 2 internally. This means that in order to obtain 3.03MHz, a clock source of 6.06MHz must be connected to X1X2.

• for crystals with less than 4MHz, a capacitor of 20pF should be connected X2 and ground.

X1

X2

GND

X1

X2f =12π LextC extC int

• Address bus 16 bits– A8 to A15 unidirectional. Higher 8 bit– AD0 to AD7 multiplexed with data. This pins

are bidirectional when used as data bus.

• Data bus 8 bit long: AD0 to AD7

ADD/DATA bus

Data bus

D

G

Q’

OC

AD7

AD6

AD5

AD0

ALE

GND

Address bus. Lower 8 bit

Address bus. higher 8 bit

A8

A15

Control signals

• ALE – active high output used to latch the lower 8 address bits.

• RD, WR - active low output signals.

• IO/M – output signal to differentiate memory and IO operation.

• S1 and S0 – status output signal. Identify various operations.

Machine cycleIO/M’ S1 S0 Control signals

Opcode fetch0 1 1 RD=0

Memory read0 1 0 RD=0

Memory write0 0 1 WR=0

I/O read 1 1 0 RD=0

I/O write 1 0 1 WR=0

Interrupt Ackn1 1 1 INTA=0

Halt Z 0 0

RD, WR =Z and INTA=1Hold Z X X

Reset Z X X

External control signals

• INTR – interrupt request. Input signal• INTA – interrupt acknowledge. o/p signal.• RST7.5,RST 6.5, RST5.5 – restart interrupts.

Vectored interrupts. Higher priority.• TRAP - Nonmaskable interrupt. Highest priority.• Hold – request for the control of buses. I/P signal• HLDA – Hold Acknowledge. O/P signal• READY – I/P signal. When low, Mp waits for

integral number of clock cycles until it goes high.

Interfacing I/O devices

• Port address

• Two ways to interface– IO mapped I/O– Memory mapped IO

• 8085– IO address space 256 (i.e 28)– Memory address space 64K (i.e 216)

Interfacing approach• Port address

– An address where a buffer or latch is connected through which actual data transfer takes place between MP and IO device.

– Input port or output port.• IO mapped IO

– The port address of the IO devices is mapped into the IO address space

– Port address is an eight bit binary number. IN/OUT instructions are used data transfer.

• Memory Mapped IO– The port address of the IO device is mapped into the memory

address space.– Port address is a 16 bit binary number. LDA, STA etc memory

related instructions are used for data transfer.

Logic devices for interfacing• Tri-state buffer

– At input port– 74LS244: unidirectional octal buffer– 74LS245: bidirectional octal buffer

• Latches– At output port– 74LS373: Octal D type latch

• Decoder– For address decoding, port selection, but control signal– 74LS138: 3-to-8 decoder most commonly used.

• Encoder– For interfacing keyboard– 74LS148: 8 to 3 priority encoder

Peripheral I/O instructions

• port address: 50H

2050D3

205150

• Let input port address is 30H

2150DB

215130

OUT 50H sends acc content to I/O address 50H

IN 30H reads content from I/O address 30H and stores the value in accum

Device selection & Data Transfer

• Decode the IO address.• Combine it with control

the signal to generate a unique IO select pulse that is generated only when both signals are asserted.

• Use it to activate the IO port

• Address decoding can be absolute or partial

Decoder

Address lines

Enable

Data bus

IOR or IOW

NOR

To

Peripherals

LatchOr

Tri-stateBuffer

IN 30H instruction

50H DB from memory

21H Port add 30H

Data from Accumula

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

21H unspecified

Port addre30H

51H Port add 30H

IO/M

M1 M2 M3

RD

MEMRD

IORD

ALE

AD7-AD0

A15-A8

CLK

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

20H Port add, 50H20H unspecified

IO/M

OUT 50H instruction

M1 M2 M3

50H Port addre50H

Data from Accumula51H

Port add 50H

OpcodeD3

RD

MEMRD

WR

ALE

AD7-AD0

A15-A8

CLK

IOWR

Interfacing LED for display

• Given port add: FFH

• Use octal latch as o/p port.

• Steps for IO select pulse:– Decode FF– Use IO/M to make the port I/O mapped

only– Use WR signal to write data to the port

IO/M

A7

A0

D7

D6

D0

+5 V

WR

IOSEL

A1

G

OE

D FF

MVI A, dataOUT FFHHLT

* To interface a 7-segment display you need to decide about the type of 7-segment: common anode or common cathode* Power supply connection to the LED segments will be opposite.* For common cathode a 0 is sent to the respective pin to lit it up.

Octal D

- latch

IOADR

Interfacing DIP switches

•Let port address: 07H – 00H•Partial decoding•Must use pull-up resistors.

IN 07H instruction reads a byte into accumulator from port 07H

3 to 8decoder

E1 E2 E3

IO/M

A7

A5

Q0

D0

+5 V

RD

IOSELA6

OE

A4A3

D1

D7

Interfacing 7 segment LED

3 to 8decoder

E1 E2 E3

IO/M

A2

A0

Q5WR

IOSELA1

A7

A6

A5

A4

A3

o/p address F9h

74LS377

D7

D6

D0

OE

D FF

7-Segment

+5V

A7 A6 A5 A4 A3 A2 A1 A0

1 1 1 1 1 1 0 1

8085 Interrupts

• 5 interrupt pins• Maskable

– INTR– RST5.5, RST6.5, RST7.5

• Non-Maskable– TRAP: cannot be disabled by instruction.

• TRAP has highest priority• Once a interrupt is serviced all interrupts except

TRAP is disabled

TRAP

• cannot be disabled by instruction

• Requires a High level with a leading eadge at the pin.

• braches to location 0024H.

• disabled at the falling edge of the signal at the pin.

RST7.5,6.5,5.5

• can be enabled or disabled by SIM (Set Interrupt Mask).

• 7.5 – Leading edge. branches to 003CH.

• 6.5,5.5 – High level.– 6.5: branches to 0034H– 5.5: branches to 0020H

INTR Interrupt process

• enable by writing EI.• mp checks INTR line at each instruction.• if INTR is high, mp completes the current instr, disables

Interrupt Flip-flop, sends INTA signal.• An RST instru is inserted by INTA through external

hardware.• Mp saves the memory address of the next instru into

stack. Program control is transferred to CALL location. The service routine starts at CALL location.

• At the end of the subroutine Int Flag is enabled again by EI instru.

• The last instr of the subroutine is RET to trasfer back the prog control to its orginal address.

RST instructions

• 8 RST instructionsMnemonics

Binary code

Hex Call LocationD7 D6

D5

D4

D3

D2

D1

D0

RST0 1 1 0 0 0 1 1 1 C7 0000

RST1 1 1 0 0 1 1 1 1 CF 0008

RST2 1 1 0 1 0 1 1 1 D7 0010

RST3 1 1 0 1 1 1 1 1 DF 0018

RST4 1 1 1 0 0 1 1 1 E7 0020

RST5 1 1 1 0 1 1 1 1 EF 0028

RST6 1 1 1 1 0 1 1 1 F7 0030

RST7 1 1 1 1 1 1 1 1 FF 0038

+5v

Enable

1

1

1

1

1011 E

F to data bus

LXI SP, FFFFH (stack region)

EI

MVI A, 00H

NXTCNT: OUT PORT1

CALL DELAY (not defined here)

INR A

JMP NXTCNT

8070: SERV: PUSH BPUSH PSWMVI B, 0AHMVI A, 00H

FLASH: OUT PORT1CALL DELAYCMADCR BJNZ FLASHPOP PSWPOP BEIRET

Main program Service routine

At 0028H JMP 8070H

0028 C30029 70002A 80

Write a program to count continuously in binary with some delay between each Count. Service routine at 8070H to flush FFH five times when the interrupt occurs (on INTR lines) with some appropriate delay between flash

+5V111011

11

RST 5 code EFD7

D0

INTA from µP

Interrupt instr: EFto data bus

Description• main program initializes stack pointer at FFFF and enables

the interrupts. program will count continuously from 00 to FF with some delay between each count.

• To interrupt the process, a switch at INTR us pushed.

• the processor will complete the current instruction and senses the interrupt. Say the next instruction is INR A.

• µP disables the interrupt flip-flop, and sends out INTA signal.

• INTA enables the tri-state buffer and, and RST 5 (ie EF) is placed on the data bus.

• µP saves the address of the INR A instruction on the stack at locations FFFE and FFFD, and the program is transferred to memory location 0028. The location 0028 has the JMP 8070 instruction to transfer the program to the service routine.

Description contd.• The program jumps to the service routine at 8070.• The service routing saves the registers that are being

used in the subroutine and loads the count ten in register B to output five flashes and five blanks.

• the service routine enables the interrupt before returning to main program.

• When the service routine executes the RET instruction, the µP retrieves the address of the instruction INR A from the stack and continues the binary counting.

Short Questions• Ins there a minimum pulse width required for the INTR

signal?– 17.5 T states. CALL requir 18T states. µP check INTR signal

one clock period before the last T states.

• How long can the INTR pulse stay high?– until the interrupt flip-flop is set by EI instruction in the

subroutine.

• Can the µP be interrupted again before the completion of the first interrupt service routine?

Vectored interrupts• TRAP, RST 7.5,6.5 and 5.5 do not require

external instruction to jump to its call locations. these interrupts are called vectored interrupts.

• maskable interrupts are enabled by two instructions: EI and SIM.

SIM• Set Interrupt Mask.

7SOD

6SDE

5XX

4R7.5

3MSE

2M7.5

1M6.5

0M5.5

0=available, 1=masked

0 = ignore mask bits1 = mask bits are enabled

if 1, Reset 7.5

no use

if 1, bit 7 is serial data out

serial out data: ignored if bit 6 is 0

Enabling all interrupts:

EI ; enable interruptsMVI A, 08h ; load bit patters for intrSIM ; Enables 7.5,6.5,5.5

RIM• Read Interrupt Mask.

– read to sense the pending interrupts.

• RIM loads accumulator with 8 bits indicating status of the interrupt masks.

• RIM can also be used to read serial data.

7SID

6I7.5

5I6.5

4I5.5

3IE

2M7.5

1M6.5

0M5.5

1 = masked

1 = Interrupt enabled

1 = pending

Serial input data, if any

RIM example• Assuming the µP is completing an RST7.5 interrupt

request, check to see if RST6.5 is pending. If it is pending, enable RST6.5 without affecting any other interrupts; otherwise return to main program.

RIM ; Read interrupt maskMOV B, A ; save mask infoANI 20h ;check if RST6.5 is pendingJNZ NEXT ;EIRET ; RST6.5 is not pending; return to main program

NEXT: MOV A,B ;get bit pattern; RST6.5 pendingANI 0Dh ; enables RST6.5 by setting D1=0ORI 08h ;enable SIM by setting D3=1SIMJMP SERV ; Jump service routing for RST6.5 at SERV

DMA• Direct Memory Access

– IO device can transfer data from (to) memory directly.– When µP controlled data transfer is too slow

• HOLD– an input high signal to this pin initiated DMA. µP releases bus in

the following machine cycle. gets back the control when HOLD is low.

• HLDA– HOLD Ackn. After releasing the bus µP sends a high signal at

this pin to inform the IO device.

DMA contd.• Usually a DMA controller sends the DMA request to MP. The

processor completes the current machine cycle; floats all the bus lines, and sends a ackn signal to HLDA. DMA controller takes the control of the buses and transfer data directly to memory from the external source by-passing µP. After data transfer DMA controller sends a low signal at HOLD pin to terminate the request for DMA. MP gets back its control over the buses.

MPUMemory IO

DMA controller

HOLD

HLDA

Address

control

Data Bus

8086/8088 Architecture

• Seven categories of signals.

• Max/min mode: min mode is used for single procss. Max mode is used for multiprocss

• Test: synchronize multiple processors

• Data Enable: generally connected to biriectional buffer to isolate MPU from system bus.

• Data tran/rcvr: controls data flow.

• IO or memory: indicates whether the proc cycle is memory operation or IO operation.

• Bus High Enable: enble the higher order byte of 16 bit data

Power & clock

External rqst

Response to External

rqst

Multipro envrnmnt

GND

INTRNMIHOLDREADYRESET

INTAHOLDA

TESTMN/MX

VCCCLK

BHE/S7A19/S6

A16/S3

AD15

AD0

ALEM/IORDWRDENDT/R

MuX add& status signals

Mux add and data

buses

Control & status signals

Max/min mode control signals

Pin Min mode Max mode

24 INTA QS1: queue status signal

25 ALE QS0: queue stat signal

26 DEN S0: input sig to bus control

27 DT/R S1: “

28 M/IO S2: “

29 WRLock: to prvnt another proc from gaining control

30 HLDARQ/GT1: enable another processor to gain control

31 HOLD RQ/GT0: “

8086 Programming model

•segment registers work together with general purpose register to access any memory value. For example if we would like to access memory at the physical address 12345h (hexadecimal), we should set the DS = 1230h and SI = 0045h. This is good, since this way we can access much more memory than with a single register that is limited to 16 bit values.CPU makes a calculation of physical address by multiplying the segment register by 10h and adding general purpose register to it (1230h * 10h + 45h = 12345h): by default BX, SI and DI registers work with DS segment register;BP and SP work with SS segment register. Other general purpose registers cannot form an effective address! also, although BX can form an effective address, BH and BL cannot.

• special purpose registers– IP - the instruction pointer. – flags register - determines the current state

of the microprocessor.

• IP register always works together with CS segment register and it points to currently executing instruction.

Memory Access

[BX + SI][BX + DI][BP + SI][BP + DI]

[SI][DI]d16 (variable offset only)[BX]

[BX + SI + d8][BX + DI + d8][BP + SI + d8][BP + DI + d8]

[SI + d8][DI + d8][BP + d8][BX + d8]

[BX + SI + d16][BX + DI + d16] [BP + SI + d16][BP + DI + d16]

[SI + d16][DI + d16][BP + d16][BX + d16]

• for example, let's assume that DS = 100, BX = 30, SI = 70.The following addressing mode: [BX + SI] + 25 is calculated by processor to this physical address: 100 * 16 + 30 + 70 + 25 = 1725.

by default DS segment register is used for all modes except those with BP register, for these SS segment register is used.

there is an easy way to remember all those possible combinations using this chart:

you can form all valid combinations by taking only one item from each column or skipping the column by not taking anything from it. as you see BX and BP never go together. SI and DI also don't go together. here are an examples of a valid addressing modes:     [BX+5]     ,     [BX+SI]     ,     [DI+BX-4]

80286

• 16 bit• Eliminates the multiplexing of buses.• Has 24 bit linear address bus support 16M bytes

address directly.• Supports memory management through which it

can support 1Gbytes of virtual memory.• Protects system software from user programs,

protects users’ program, and restricts access to some memory regions.

• Supports multiuser systems.

80386/486

• 32 bit processor.• Support following multiuser system requirement

– High speed of execution– Ability to handle different types of tasks efficiently– Large memory space that can be shared by multiuser– Appropriate memory allocations and the management

of memory access– Data security and data access– Limited and selected access to part of the system– Resource sharing and management

• 32bit non-multiplexed address bus

• Can address 4G physical memory and through a memory management unit 64 (246) terabytes of virtual memory.

• Two modes:real mode, and protected mode.

• Execution is highly pipelined.

80386 Programming model

• 8-general purpose registers can be accessed as 8, 16 or 32 bit

• 6-segment selector registers.

• IP can used as 16/32 bits• Flag is 31 bits but 14 are

used at present.• 6 for data, 3 operation,2 io

previl, 1 nested task, 2 for VM

AX

BX

CX

DXSP

BP

SI

DI

FLAGSIP

FS

CS

SS

DS

ES

GS

071531

Temperature control

Internal architecture of 8085

ALU