microprocessor 8085 pdf

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8/5/2015 1 UNIT I THE 8085 MICROPROCESSOR The salient features of 8085 µp It is a 8 bit microprocessor. It is manufactured with N-MOS technology. It has 16 bit address bus Can address upto 216 = 65536 bytes (64KB) memory locations through A0- A15 The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7 Data bus is a group of 8 lines D0 – D7 It supports external interrupt request. D.Shiloah Elizabeth, DCSE/AU 2 The salient features of 8085 µp It has the following registers A 16 bit program counter (PC) A 16 bit stack pointer (SP) Six 8-bit general purpose register arranged in pairs: BC, DE, HL. It requires a signal +5V power supply and operates at 6.144 MHZ single phase clock. It is enclosed with 40 pins Dual in line package (DIP). D.Shiloah Elizabeth, DCSE/AU 3 The salient features of 8085 µp Memory: Program, data and stack memories occupy the same memory space. The total addressable memory size is 64 KB. Program memory - program can be located anywhere in memory. Jump, branch and call instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB. All jump/branch instructions use absolute addressing. Data memory - the processor always uses 16-bit addresses so that data can be placed anywhere. Stack memory is limited only by the size of memory. Stack grows downward. First 64 bytes in a zero memory page should be reserved for vectors used by RST instructions. D.Shiloah Elizabeth, DCSE/AU 4

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Page 1: Microprocessor 8085 pdf

8/5/2015

1

UNIT I THE 8085 MICROPROCESSOR

The salient features of 8085 µp

• It is a 8 bit microprocessor. • It is manufactured with N-MOS technology. • It has 16 bit address bus

• Can address upto 216 = 65536 bytes (64KB) memory locations through A0-A15

• The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 –AD7

• Data bus is a group of 8 lines D0 – D7• It supports external interrupt request.

D.Shiloah Elizabeth, DCSE/AU 2

The salient features of 8085 µp

• It has the following registers• A 16 bit program counter (PC)• A 16 bit stack pointer (SP) • Six 8-bit general purpose register arranged in pairs: BC, DE, HL.

• It requires a signal +5V power supply and operates at 6.144 MHZ single phase clock.

• It is enclosed with 40 pins Dual in line package (DIP).

D.Shiloah Elizabeth, DCSE/AU 3

The salient features of 8085 µp

• Memory: • Program, data and stack memories occupy the same memory space. The total

addressable memory size is 64 KB. • Program memory - program can be located anywhere in memory.

• Jump, branch and call instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB.

• All jump/branch instructions use absolute addressing.• Data memory - the processor always uses 16-bit addresses so that data can

be placed anywhere.• Stack memory is limited only by the size of memory.

• Stack grows downward. • First 64 bytes in a zero memory page should be reserved for vectors used

by RST instructions.

D.Shiloah Elizabeth, DCSE/AU 4

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8085 Pin diagramSignal Groups:

• Address bus

• A15-A8, AD7-AD0• Multiplexed address/data bus:

• AD7-AD0

• Control and status signals• ALE, RD, WR, IO/M, S1, S0

• Power supply and clock frequency• VCC, VSS, X1, X2, CLK (OUT)

• Externally initiated signals: • Input: TRAP, RST 7.5, RST 6.5, RST 5.5,

INTR, READY, HOLD• Output: INTA, HLDA• Reset: RESET IN, RESET OUT

• Serial I/O ports: • SID, SOD

D.Shiloah Elizabeth, DCSE/AU 5 D.Shiloah Elizabeth, DCSE/AU 6

Data flow from memory to the MPU

MOV C,AOpcode: 4FH

D.Shiloah Elizabeth, DCSE/AU 7

Steps For Fetching an Instruction

• Instruction at memory location 2005. i.e., program counter: 2005H.• The following is the sequence of operations:

• The program counter places the address value on the address bus.

• The control unit issues a RD signal. • The byte in the memory location is placed on the data bus.• The value on the data bus is read into the instruction decoder

inside the microprocessor.• After decoding the instruction, the control unit issues the

proper control signals to perform the operation.

D.Shiloah Elizabeth, DCSE/AU 8

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Timing: Transfer of byte from memory to MPU

MOV C,AOpcode: 4FH

D.Shiloah Elizabeth, DCSE/AU 9

Timing Signals For Fetching an Instruction

• At T1 , • The high order 8 address bits (20H) are placed on the address lines

A8 – A15 and the low order bits are placed on AD7–AD0• The ALE signal goes high to indicate that AD0 – AD8 are carrying

an address• The IO/M signal goes low to indicate a memory operation

• At the beginning of the T2 cycle, • The low order 8 address bits are removed from AD7– AD0• The control unit sends the Read (RD) signal to the memory. The

signal remains low (active) for two clock periods to allow for slow devices

D.Shiloah Elizabeth, DCSE/AU 10

Timing Signals For Fetching an Instruction (Contd.)

• During T2 , • Memory places the data from the memory location on the lines

AD7– AD0• During T3,

• The RD signal is Disabled (goes high). This turns off the output Tri-state buffers in the memory. That makes the AD7– AD0 lines go to high impedence mode

• During T4• The machine code or the byte is decoded by the instruction

decoder and the task is carried out based on the bit patternD.Shiloah Elizabeth, DCSE/AU 11

Demultiplexingthe bus AD7-AD0

Schematic of latching low-order address bus

D.Shiloah Elizabeth, DCSE/AU 12

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Cycles and States

• From the above discussion, we can define terms that will become handylater on:

• T- State: One subdivision of an operation. A T-state lasts for one clockperiod.

• An instruction’s execution length is usually measured in a number ofT-states. (clock periods).

• Machine Cycle: The time required to complete one operation ofaccessing memory, I/O, or acknowledging an external request.

• This cycle may consist of 3 to 6 T-states.• Instruction Cycle: The time required to complete the execution of an

instruction.• In the 8085, an instruction cycle may consist of 1 to 6 machine

cycles.D.Shiloah Elizabeth, DCSE/AU 13

Schematic to generate Read/ write control signals for M and I/O

Demultiplexed address and data bus with control signals

D.Shiloah Elizabeth, DCSE/AU 14

8085A Microprocessor: Functional Block diagram

D.Shiloah Elizabeth, DCSE/AU 15

D7 D6 D5 D4 D3 D2 D1 D0

S Z Ac P CY

Flag Register

D.Shiloah Elizabeth, DCSE/AU 16

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Instruction decoding and ExecutionD.Shiloah Elizabeth, DCSE/AU 17

Programming ModelHardware Model

D.Shiloah Elizabeth, DCSE/AU 18

Instruction classification

• Data transfer operations• Arithmetic operations• Logical operations• Branching operations• Machine control operations

D.Shiloah Elizabeth, DCSE/AU 19

Instruction word size

• One-byte instructions• Two-byte instructions• Three-byte instructions

D.Shiloah Elizabeth, DCSE/AU 20

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Data transfer instructions

• Copy from source to destination

MOV Rd, RsMOV M, RsMOV Rd, M

MOV B,CMOV B,M

• Move immediate 8-bit

MVI Rd, dataMVI M, data

MVI B, 57MVI M, 57

D.Shiloah Elizabeth, DCSE/AU 21

Data transfer instructions

• Load accumulator

LDA 16-bit address

LDA 4200H

• Load accumulator indirect

LDAX B/D register pair

LDAX B

• Load register pair immediate

LXI Reg. pair, 16-bit data

LXI H, 2034

• Load H and L registers direct

LHLD 16-bit address

LHLD 2040

D.Shiloah Elizabeth, DCSE/AU 22

Data transfer instructions

• Store accumulator directSTA 16-bit addressSTA 4350STA XYZ

• Store accumulator indirectSTAX Reg. pairSTAX B

• Store H and L registers directSHLD 16-bit addressSHLD 2470

• Exchange H and L with D and EXCHG noneXCHG

D.Shiloah Elizabeth, DCSE/AU 23

Data transfer instructions

• Copy H and L registers to the stack pointer

SPHL noneSPHL

• Exchange H and L with top of stack

XTHL noneXTHL

• Push register pair onto stackPUSH Reg. pairPUSH BPUSH A

• Exchange H and L with D and EPOP Reg. pairPOP HPOP A

D.Shiloah Elizabeth, DCSE/AU 24

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Data transfer instructions

• Output data from accumulator to a port with 8-bit address

OUT 8-bit port address

OUT 87

• Input data to accumulator from a port with 8-bit address

IN 8-bit port address

IN 82

D.Shiloah Elizabeth, DCSE/AU 25

Arithmetic instructions

• Add register or memory to accumulator

ADD R ADD MADD B ADD M

• Add register to accumulator with carry

ADC R ADC MADC B ADC M

• Add immediate to accumulatorADI 8-bit data

ADI 45

• Add immediate to accumulator with carry

ACI 8-bit data

ACI 45

D.Shiloah Elizabeth, DCSE/AU 26

Arithmetic instructions

• Add register pair to H and L registers

DAD Reg. pairDAD H

If the result is larger than 16 bits, the CY flag is set. No other flags are affected.

• Decimal adjust accumulator

DAA noneDAA

D.Shiloah Elizabeth, DCSE/AU 27

Arithmetic instructions

• Subtract register or memory from accumulator

SUB R SUB MSUB B SUB M

• Subtract source and borrow from accumulator

SBB R SBB MSBB B SBB M

• Subtract immediate from accumulator

SUI 8-bit data

SUI 45

• Subtract immediate from accumulator with borrow

SBI 8-bit data

SBI 45

D.Shiloah Elizabeth, DCSE/AU 28

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Arithmetic instructions

• Increment register or memory by 1

INR R INR MINR B INR M

• Increment register pair by 1 INX RINX H

• Decrement register or memory by 1

DCR R DCR MDCR B DCR M

• Decrement register pair by 1 DCX RDCX H

D.Shiloah Elizabeth, DCSE/AU 29

Branching instructions

• Jump unconditionally

JMP 16-bit address

JMP 2034JMP label

• Jump conditionallyOperand: 16-bit address

Opcode Description Flag Status JC Jump on Carry CY = 1 JNC Jump on no Carry CY = 0 JP Jump on positive S = 0 JM Jump on minus S = 1 JZ Jump on zero Z = 1 JNZ Jump on no zero Z = 0 JPE Jump on parity even P = 1 JPO Jump on parity odd P = 0

D.Shiloah Elizabeth, DCSE/AU 30

Branching instructions

• Unconditional subroutine call

CALL 16-bit address

CALL 2034CALL label

• Call conditionally Operand: 16-bit address

Opcode Description Flag Status CC Call on Carry CY = 1CNC Call on no Carry CY = 0CP Call on positive S = 0CM Call on minus S = 1CZ Call on zero Z = 1CNZ Call on no zero Z = 0CPE Call on parity even P = 1CPO Call on parity odd P = 0

D.Shiloah Elizabeth, DCSE/AU 31

Branching instructions

• Return from subroutine unconditionally

RET none

RET

• Return from subroutine conditionallyOperand: none

Opcode Description Flag Status RC Return on Carry CY = 1RNC Return on no Carry CY = 0RP Return on positive S = 0RM Return on minus S = 1RZ Return on zero Z = 1RNZ Return on no zero Z = 0RPE Return on parity even P = 1RPO Return on parity odd P = 0

D.Shiloah Elizabeth, DCSE/AU 32

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Branching instructions

• Load program counter with HL contents

PCHL nonePCHL

• RestartInstr Restart AddrRST 0 0000HRST 1 0008HRST 2 0010HRST 3 0018HRST 4 0020HRST 5 0028HRST 6 0030HRST 7 0038H

• RestartInterrupt Rst AddrTRAP 0024HRST 5.5 002CHRST 6.5 0034HRST 7.5 003CH

these interrupts generate RSTinstructions internally andthus do not require anyexternal hardware.

• generally used inconjunction withinterrupts andinserted usingexternal hardware.

• can be used assoftware instructionsin a program totransfer programexecution to one ofthe eight locations.

D.Shiloah Elizabeth, DCSE/AU 33

Logical instructions

• Compare register or memory with accumulator

CMP R CMP MCMP B CMP M

• Compare immediate with accumulator

CPI 8-bit dataCPI 45

• Logical AND register or memory with accumulator

ANA R ANA MANA B ANA M

• Logical AND immediate with accumulator

ANI 8-bit dataANI 07

S, Z, P are modified.CY is reset. AC is set.

S, Z, P are modified.CY is reset. AC is set.

D.Shiloah Elizabeth, DCSE/AU 34

Logical instructions

• Exclusive OR register or memory with accumulator

XRA R XRA MXRA B XRA M

• Exclusive OR immediate with accumulator

XRI 8-bit dataXRI 86

• Logical OR register or memory with accumulator

ORA R ORA MORA B ORA M

• Logical OR immediate with accumulator

ORI 8-bit dataORI 07

S, Z, P are modified.CY and AC are reset.

S, Z, P are modified.CY and AC are reset.

S, Z, P are modified.CY and AC are reset.

S, Z, P are modified.CY and AC are reset.

D.Shiloah Elizabeth, DCSE/AU 35

Logical instructions

• Rotate accumulator leftRLC noneRLC

• Rotate accumulator right RRC noneRRC

• Rotate accumulator left through carry

RAL none RAL

• Rotate accumulator right through carry

RAR noneRAR

D.Shiloah Elizabeth, DCSE/AU 36

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Logical instructions

• Complement accumulator CMA noneCMA

• Complement carry CMC noneCMC

• Set CarrySTC none STC

D.Shiloah Elizabeth, DCSE/AU 37

CONTROL INSTRUCTIONS

• No operationNOP none• Halt and enter wait stateHLT none• Disable interruptsDI none• Enable interruptsEI none

• Read interrupt maskRIM none• Set interrupt maskSIM none

D.Shiloah Elizabeth, DCSE/AU 38

Rotate accumulator left

• Each binary bit of the accumulator is rotated left by one position.• D7 is placed in the position of D0 as well as in CY.• CY is modified according to D7.

RLC

CY D7 D6 D5 D4 D3 D2 D1 D0

CY B7 B6 B5 B4 B3 B2 B1 B0

CY D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0 B7

Before execution of RLC

After execution of RLC

D.Shiloah Elizabeth, DCSE/AU 39

Rotate accumulator right

• Each binary bit of the accumulator is rotated right by one position.• D0 is placed in the position of D7 as well as in CY.• CY is modified according to bit D0.

RRC

D7 D6 D5 D4 D3 D2 D1 D0 CY

B7 B6 B5 B4 B3 B2 B1 B0 CY

D7 D6 D5 D4 D3 D2 D1 D0 CY

B0 B7 B6 B5 B4 B3 B2 B1 B0

Before execution of RRC

After execution of RRC

D.Shiloah Elizabeth, DCSE/AU 40

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• Each binary bit of the accumulator is rotated left by one position throughthe Carry flag.

• D7 is placed in CY, and CY is placed in D0.• CY is modified according to D7.

Rotate accumulator left through carry RAL

CY D7 D6 D5 D4 D3 D2 D1 D0

CY B7 B6 B5 B4 B3 B2 B1 B0

CY D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0 CY

Before execution of RAL

After execution of RAL

D.Shiloah Elizabeth, DCSE/AU 41

Rotate accumulator right through carry

• Each binary bit of the accumulator is rotated right by one position through the Carry flag.

• D0 is placed in CY, and CY is placed in D7. • CY is modified according to D0.

RAR

D7 D6 D5 D4 D3 D2 D1 D0 CY

B7 B6 B5 B4 B3 B2 B1 B0 CY

D7 D6 D5 D4 D3 D2 D1 D0 CY

CY B7 B6 B5 B4 B3 B2 B1 B0

Before execution of RAR

After execution of RAR

D.Shiloah Elizabeth, DCSE/AU 42

ADDRESSING MODES

D.Shiloah Elizabeth, DCSE/AU 43

Addressing Modes of 8085

• To perform any operation, we have to give the correspondinginstructions to the microprocessor.

• In each instruction, programmer has to specify 3 things:• Operation to be performed• Address of source of data• Address of destination of result

D.Shiloah Elizabeth, DCSE/AU 44

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Addressing Modes of 8085

• The method by which the address of source of data or the address ofdestination of result is given in the instruction is called AddressingModes of 8085.

• The term addressing mode refers to the way in which the operand ofthe instruction is specified.

D.Shiloah Elizabeth, DCSE/AU 45

Addressing Modes of 8085

• Intel 8085 uses the following addressing modes: 1. Direct Addressing Mode 2. Register Addressing Mode 3. Register Indirect Addressing Mode 4. Immediate Addressing Mode 5. Implicit Addressing Mode

D.Shiloah Elizabeth, DCSE/AU 46

Addressing Modes of 8085

• Direct Addressing Mode • In this mode, the address of the operand is given in the instruction

itself.• LDA 4500H• LDA is the operation. • 4500 H is the address of source. • Accumulator is the destination.

D.Shiloah Elizabeth, DCSE/AU 47

Addressing Modes of 8085

• Register Addressing Mode • In this mode, the operand is in general purpose register. • MOV A,B• MOV is the operation. • B is the source of data. • A is the destination.

D.Shiloah Elizabeth, DCSE/AU 48

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Addressing Modes of 8085

• Register Indirect Addressing Mode• In this mode, the address of operand is specified by a register pair. • MOV A,M• MOV is the operation. • M is the memory location specified by H-L register pair. • A is the destination.

D.Shiloah Elizabeth, DCSE/AU 49

Addressing Modes of 8085

• Immediate Addressing Mode• In this mode, the operand is specified within the instruction itself. • MVI A,05H• MVI is the operation. • 05 H is the immediate data (source). • A is the destination.

D.Shiloah Elizabeth, DCSE/AU 50

Addressing Modes of 8085

• Implicit/Implied Addressing Mode • If address of source of data as well as address of destination of result

is fixed, then there is no need to give any operand along with the instruction.

• CMA• CMA is the operation. • A is the source. • A is the destination.

D.Shiloah Elizabeth, DCSE/AU 51

Timing DiagramTiming diagram is the display of initiation of read/write and transfer of data operations under the control of 3-status signals IO / M , S1, and S0.

D.Shiloah Elizabeth, DCSE/AU 52

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Cycles and States

• T- State: One subdivision of an operation. A T-state lasts for one clockperiod.

• An instruction’s execution length is usually measured in a number of T-states.(clock periods).

• Machine Cycle: The time required to complete one operation ofaccessing memory, I/O, or acknowledging an external request.

• This cycle may consist of 3 to 6 T-states.

• Instruction Cycle: The time required to complete the execution of aninstruction.

• In the 8085, an instruction cycle may consist of 1 to 6 machine cycles.

D.Shiloah Elizabeth, DCSE/AU 53

Operations

• Opcode Fetch• Memory Read• Memory Write• I/O Read• I/O Write

D.Shiloah Elizabeth, DCSE/AU 54

D.Shiloah Elizabeth, DCSE/AU 55

Opcode Fetch Machine Cycle

D.Shiloah Elizabeth, DCSE/AU 56

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Memory Read Machine Cycle

D.Shiloah Elizabeth, DCSE/AU 57

Memory Write Machine Cycle

D.Shiloah Elizabeth, DCSE/AU 58

I/O Read Machine Cycle

D.Shiloah Elizabeth, DCSE/AU 59

I/O Write Machine Cycle

D.Shiloah Elizabeth, DCSE/AU 60

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• MVI A, 45H• M1: opcode fetch• M2: memory read• 2 MCs• 4+3 = 7 T-states

• STA 5000H• M1: opcode fetch• M2: memory read• M3: memory read• M4: memory write• 4 MCs• 4+3+3+3 = 13 T-states

D.Shiloah Elizabeth, DCSE/AU 61

• LHLD• SHLD• STA• STAX• LDA• LDAX• LXI

D.Shiloah Elizabeth, DCSE/AU 62

Counters & Time Delays

D.Shiloah Elizabeth, DCSE/AU 63

Counters - Using a Register as a Loop Counter

• A loop counter is set up by loading a register with a certain value• Then using the DCR (to decrement) or INR (to increment) the

contents of the register are updated.• A loop is set up with a conditional jump instruction that loops

back or not depending on whether the count has reached thetermination count.

D.Shiloah Elizabeth, DCSE/AU 64

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Counters

• Operation of a loop counter

D.Shiloah Elizabeth, DCSE/AU 65

Counters

• Sample ALP for implementing a loop• using DCR instruction

MVI C, 15HLOOP DCR C

JNZ LOOP

• Using a single register, one can repeat a loop for a maximumcount of 255 times.

D.Shiloah Elizabeth, DCSE/AU 66

Counters - Using a Register Pair as a Loop Counter

• It is possible to increase the count by using a register pair for theloop counter instead of the single register.

• Problem: how to test for the final count since DCX and INX do notmodify the flags?

• However, if the loop is looking for when the count becomeszero, we can apply OR between the two registers in the pairand then check the zero flag.

D.Shiloah Elizabeth, DCSE/AU 67

Counters

• The following is an example of a loop set up with a register pairas the loop counter.

LXI B, 1000HLOOP DCX B

MOV A, CORA BJNZ LOOP

D.Shiloah Elizabeth, DCSE/AU 68

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Delays

• Each instruction passes through different combinations of Fetch,Memory Read, and Memory Write cycles.

• Knowing the combinations of cycles, one can calculate how long suchan instruction would require to complete.

• Let• B be Number of Bytes• M be Number of Machine Cycles• T be Number of T-State.

D.Shiloah Elizabeth, DCSE/AU 69

Delays

• Knowing how many T-States an instruction requires, and keeping inmind that a T-State is one clock cycle long, we can calculate the timeusing the following formula:

Delay = No. of T-States / Frequency• For example

• “MVI” instruction uses 7 T-States.• Therefore, if the Microprocessor is running at 2 MHz, the instruction would

require 3.5 µSeconds to complete.

D.Shiloah Elizabeth, DCSE/AU 70

Delays – Using a register

• Delay loops• We can use a loop to produce a certain amount of time delay

in a program.• The following is an example of a delay loop:

MVI C, FFHLOOP DCR C

JNZ LOOP

D.Shiloah Elizabeth, DCSE/AU 71

Delays – Using a register

MVI C, FFH 7 T-StatesLOOP DCR C 4 T-States

JNZ LOOP 10 T-States• The first instruction initializes the loop counter and is

executed only once requiring only 7 T-States.• The following two instructions form a loop that requires 14 T-

States to execute and is repeated 255 times until C becomes 0.

D.Shiloah Elizabeth, DCSE/AU 72

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Delays – Using a register

• In the last iteration of the loop, the JNZ instruction will fail and require only 7 T-States rather than the 10.

• Therefore, we must deduct 3 T-States from the total delay to get an accurate delay calculation.

• To calculate the delay, we use the following formula:Tdelay= TO+ TL

Tdelay= total delayTO= delay outside the loopTL= delay of the loopTOis the sum of all delays outside the loop

D.Shiloah Elizabeth, DCSE/AU 73

Delays – Using a register

• Using these formulas, we can calculate the time delay for the previous example:

• TO= 7 T-States• Delay of the MVI instruction

• TL= (14 X 255) -3 = 3567 T-States• 14 T-States for the 2 instructions repeated 255 times (FF16= 25510) reduced by the 3 T-

States for the final JNZ.

D.Shiloah Elizabeth, DCSE/AU 74

Delays – Using a register pair

• Using a Register Pair as a Loop Counter• The following is an example of a delay loop set up with a register pair as the

loop counter.LXI B, 1000H ;10 T-States

LOOP DCX B6 ;T-StatesMOV A, C ;4 T-StatesORA B ;4 T-StatesJNZ LOOP ;10 T-States

D.Shiloah Elizabeth, DCSE/AU 75

Delays – Using a register pair

• Using the same formula from before, we can calculate:

• TO= 10 T-States• The delay for the LXI instruction

• TL= (24 X 4096) -3 = 98301 T-States• 24 T-States for the 4 instructions in the loop repeated 4096 times (100016= 409610)

reduced by the 3 T-States for the JNZ in the last iteration.

D.Shiloah Elizabeth, DCSE/AU 76

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Delays – Using nested loops

• Nested Loops for Delay• Instead (or in conjunction with) Register Pairs, a nested loop structure can be

used to increase the total delay produced.MVI B, 10H ;7 T-States

LOOP2 MVI C, FFH ;7 T-StatesLOOP1 DCR C ;4 T-States

JNZ LOOP1 ;10 T-StatesDCR B ;4 T-StatesJNZ LOOP2 ;10 T-States

D.Shiloah Elizabeth, DCSE/AU 77

Delays – Using nested loops

• The calculation remains the same except that it the formula must be applied recursively to each loop.

• Start with the inner loop, then plug that delay in the calculation of the outer loop.

• Delay of inner loop• TO1= 7 T-States

• MVI C, FFH instruction

• TL1= (255 X 14) -3 = 3567 T-States• 14 T-States for the DCR C and JNZ instructions repeated 255 times (FF16= 25510) minus 3

for the final JNZ

D.Shiloah Elizabeth, DCSE/AU 78

Delays – Using nested loops

• Delay of outer loop• TO2= 7 T-States

• MVI B, 10H instruction

• TL1= (16 X (14 + 3574)) -3 = 57405 T-States• 14 T-States for the DCR B and JNZ instructions and 3574 T-States for loop1 repeated 16 times

(1016= 1610) minus 3 for the final JNZ.

• TDelay= 7 + 57405 = 57412 T-States

• Total Delay TDelay= 57412 X 0.5 µSec = 28.706 mSec

D.Shiloah Elizabeth, DCSE/AU 79

Delays – Larger delays

• Increasing the delay• The delay can be further increased by using register pairs for each of the loop

counters in the nested loops setup.• It can also be increased by adding dummy instructions (like NOP) in the body

of the loop.

D.Shiloah Elizabeth, DCSE/AU 80

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Delay Subroutine

• The delay time is given by the total time taken to execute the delay routine.

• Eg. If the 8085 microprocessor has 5 MHz quartz crystal then, the internal clock frequency = 5 /2 = 2.5 MHz

• Time for one T-state= 1 / 2.5 x 106= 0.4µsec• For small time delays (< 0.5 ms) an 8- bit register can be used.• For large time delays (< 0.5 s) l6-bit register should be used.• For very large time delays (> 0.5 s), a delay routine can be repeatedly called in

the main program.

D.Shiloah Elizabeth, DCSE/AU 81

Delay Subroutine

• Disadvantage in delay routines:• processor time is wasted

• Solution:• use dedicated timer like 8253/8254 to produce time delays or

to maintain timings of various operations.

D.Shiloah Elizabeth, DCSE/AU 82

Delay Subroutine - Example

• A delay routine to produce a time delay of 0.5 ms in 8085processor-based system whose clock source is 6 MHz quartzcrystal.

• The delay required is 0.5 ms, hence an 8-bit register of 8085 canbe used to store a Count value and then decrement to zero.

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Delay Subroutine - Example

• Delay routineMVI D, N ; N: count

Loop: DCR DJNZ Loop RET

Instruction T-State requiredfor execution of an instruction

Number of times the instruction isexecuted

Total T-States

CALL addr16 18 1 18 x 1 = 18

MVI D, N 7 1 7 x 1 = 7

DCR D 4 N 4 x N = 4N

JNZ LOOP 10 N-1 10 x (N-1) = 10N –10

7 1 7 x 1 = 7

RET 10 1 10 x 1 = 10

TOTAL T-STATES FOR DELAY SUBROUTINE 14N + 32

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Delay Subroutine - Calculation to find the count value, N

• External clock frequency = 6 MHz• Internal clock frequency

= External Frequency / 2= 6 / 2= 3 MHz• Time period for 1 T-State

= 1 / Internal clock frequency= 1 / 3x106= 0.333µs• No. of T-states required for delay of 0.5ms

= Required time delay / Time for one T-state= 0.5ms / 0.333µs= 1500.10≈ 1500 = 150010

• From above table,• 14N + 32 = 1500• N = (1500 – 32) / 14 = 104.85710≈ 10510= 69H• Therefore by replacing the count value, N by 69H in the above program , a delay of

0.5ms can be producedD.Shiloah Elizabeth, DCSE/AU 85

Counters

• ALP for 8085 to count from AAH to 00H, with a time delay of 2ms for each count. Assume the external frequency given to the processor is 2MHz.

• Internal Frequency in 8085 = External frequency/2= 2MHz / 2= 1MHz

• T-State= 1 / f (internal frequency)= 1µs

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Counters

• Main program for counting from AA to 00

MVI C, AAHLoop: CALL Delay

DCR CJNZ LoopHLT

• Delay subroutine for delay of 2msDelay: MVI D, 4AHNext: NOP

NOPNOPNOPDCR DJNZ NextRET

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Counters

• Hexadecimal counter to count from FFH to 00HMVI B, 00H

NEXT: DCR BMVI C, 05

DELAY: DCR CJNZ DELAYMOV A, BOUT PORT1JMP NEXT

D.Shiloah Elizabeth, DCSE/AU 88

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Counters

• Modulo-10 counterSTART: MVI B, 00H

MOV A, BDISPLAY: OUT PORT1

LXI H, 16 BITLOOP: DCX H

MOV A, LORA HJNZ LOOPINR BMOV A, BCPI 0AHJNZ DISPLAYJZ START

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Delay Calculation

L

OD

LOD

LOD

l

O

D

TTTCount

CountTTT

CountTTT

pairregisterorregisterinstoredcountCountlooptheinsidedelaytimeT

looptheoutsidedelaytimeTmsindelaytimeT

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STACK & SUBROUTINEs

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Stack

• The stack is an area of memory identified by the programmer fortemporary storage of information.

• The stack is a Last In First Out (LIFO) structure.• The stack normally grows backwards into memory.

• the programmer defines the bottom of the stack and the stack grows up intoreducing address range.

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Stack

Memory

Bottom of stack

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Stack

• It is customary to place the bottom of the stack at the end of memoryto keep it as far away from user programs as possible.

• In the 8085, the stack is defined by setting the SP (Stack Pointer)register.

• LXI SP, 6000H• This sets the Stack Pointer to location 6000H (end of memory for the 8085).• The Size of the stack is limited only by the available memory

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Stack - Operations

• Information is saved on the stack by PUSHing it on.• It is retrieved from the stack by POPing it off.• The 8085 provides two instructions:

• PUSH and POP for storing information on the stack and retrieving it back.• Both PUSH and POP work with register pairs only.

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Stack – Operations - PUSH

• PUSH B(1 Byte Instruction)

• Decrement SP• Copy the contents of register B to

the memory location pointed to bySP

• Decrement SP• Copy the contents of register C to

the memory location pointed to bySP

5FFC

5FFD

5FFE 34

5FFF 12

6000 SP (initially)

B C

12 34

SP (after Push)

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Stack – Operations - POP

• POP D• (1 Byte Instruction)

• Copy the contents of the memorylocation pointed to by the SP toregister E

• Increment SP• Copy the contents of the memory

location pointed to by the SP toregister D

• Increment SPSP (after Pop)

D E

12 34

SP (initially)

5FFC

5FFD

5FFE 34

5FFF 12

6000

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Stack - Operations

• During pushing, the stack operates in a “decrement then store” style.• The stack pointer is decremented first, then the information is placed on the

stack.

• During poping, the stack operates in a “use then increment” style.• The information is retrieved from the top of the stack and then the pointer is

incremented.

• The SP pointer always points to “the top of the stack”.

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Stack - Operations

• The order of PUSHs and POPs must be opposite of each other in orderto retrieve information back into its original location.

PUSH BPUSH D...POP DPOP B

• Reversing the order of the POP instructions will result in the exchangeof the contents of BC and DE.

D.Shiloah Elizabeth, DCSE/AU 99

Stack - Operations

• The 8085 recognizes one additional register pair called the PSW(Program Status Word).

• This register pair is made up of the Accumulator and the Flags registers.

• It is possible to push the PSW onto the stack, do whatever operationsare needed, then POP it off of the stack.

• The result is that the contents of the Accumulator and the status of the Flagsare returned to what they were before the operations were executed.

D.Shiloah Elizabeth, DCSE/AU 100

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Stack - Operations

• PUSH PSW (1 Byte Instruction) • Decrement SP • Copy the contents of register A to the memory location pointed to by SP • Decrement SP • Copy the contents of Flag register to the memory location pointed to by SP

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Stack - Operations

• POP PSW (1 Byte Instruction) • Copy the contents of the memory location pointed to by the SP to Flag

register • Increment SP • Copy the contents of the memory location pointed to by the SP to register A • Increment SP

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Modify Flag Content using PUSH/POP

• If we want to Reset the Zero Flag • 8085 Flag :• Program:

LXI SP 5FFF PUSH PSW POP H MOV A,L ANI BFH (BFH= 1011 1111) ;Masking MOV L,A PUSH H POP PSW

7 6 5 4 3 2 1 0

S Z X AC X P X CY

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Subroutines

• A subroutine is a group of instructions that will be used repeatedly indifferent locations of the program.

• Rather than repeat the same instructions several times, they can be groupedinto a subroutine that is called from the different locations.

• In Assembly language, a subroutine can exist anywhere in the code.• However, it is customary to place subroutines separately from the main

program.

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Subroutines - Instructions

• The 8085 has two instructions for dealing with subroutines.• The CALL instruction is used to redirect program execution to the subroutine.• The RET instruction is used to return the execution to the calling routine.

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Subroutines – Instructions - CALL

• CALL 4000H (3 byte instruction)

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Subroutines – Instructions - CALL

Microprocessor • Reads the subroutine address from the next two memory location and stores

the higher order 8bit of the address in the W register and stores the lower order 8bit of the address in the Z register

• Pushes the address of the instruction immediately following the CALL onto the stack [Return address]

• Loads the program counter with the 16-bit address supplied with the CALL instruction from WZ register.

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Subroutines – Instructions - RET

• RET (1 byte instruction)

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Subroutines – Instructions - RET

• The CALL instruction places the return address at the two memory locations immediately before where the Stack Pointer is pointing.

• You must set the SP correctly BEFORE using the CALL instruction.

• The RET instruction takes the contents of the two memory locations at the top of the stack and uses these as the return address.

• Do not modify the stack pointer in a subroutine. You will lose the return address.

D.Shiloah Elizabeth, DCSE/AU 109

Passing Data to a Subroutine

• In Assembly Language data is passed to a subroutine through registers.

• The data is stored in one of the registers by the calling program and the subroutine uses the value from the register.

• The other possibility is to use agreed upon memory locations.• The calling program stores the data in the memory location and the

subroutine retrieves the data from the location and uses it.

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Call by Reference and Call by Value

• If the subroutine performs operations on the contents of theregisters, then these modifications will be transferred back to thecalling program upon returning from a subroutine.

• Call by reference

• If this is not desired, the subroutine should PUSH all the registers itneeds on the stack on entry and POP them on return.

• The original values are restored before execution returns to the callingprogram.

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Cautions with PUSH and POP

• PUSH and POP should be used in opposite order.• There has to be as many POPs as there are PUSHs.

• If not, the RET statement will pick up the wrong information from the top ofthe stack and the program will fail.

• It is not advisable to place PUSH or POP inside a loop.

D.Shiloah Elizabeth, DCSE/AU 112